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dmtbinfo2.c
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dmtbinfo2.c
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/******************************************************************************
*
* Module Name: dmtbinfo2 - Table info for non-AML tables
*
*****************************************************************************/
/******************************************************************************
*
* 1. Copyright Notice
*
* Some or all of this work - Copyright (c) 1999 - 2023, Intel Corp.
* All rights reserved.
*
* 2. License
*
* 2.1. This is your license from Intel Corp. under its intellectual property
* rights. You may have additional license terms from the party that provided
* you this software, covering your right to use that party's intellectual
* property rights.
*
* 2.2. Intel grants, free of charge, to any person ("Licensee") obtaining a
* copy of the source code appearing in this file ("Covered Code") an
* irrevocable, perpetual, worldwide license under Intel's copyrights in the
* base code distributed originally by Intel ("Original Intel Code") to copy,
* make derivatives, distribute, use and display any portion of the Covered
* Code in any form, with the right to sublicense such rights; and
*
* 2.3. Intel grants Licensee a non-exclusive and non-transferable patent
* license (with the right to sublicense), under only those claims of Intel
* patents that are infringed by the Original Intel Code, to make, use, sell,
* offer to sell, and import the Covered Code and derivative works thereof
* solely to the minimum extent necessary to exercise the above copyright
* license, and in no event shall the patent license extend to any additions
* to or modifications of the Original Intel Code. No other license or right
* is granted directly or by implication, estoppel or otherwise;
*
* The above copyright and patent license is granted only if the following
* conditions are met:
*
* 3. Conditions
*
* 3.1. Redistribution of Source with Rights to Further Distribute Source.
* Redistribution of source code of any substantial portion of the Covered
* Code or modification with rights to further distribute source must include
* the above Copyright Notice, the above License, this list of Conditions,
* and the following Disclaimer and Export Compliance provision. In addition,
* Licensee must cause all Covered Code to which Licensee contributes to
* contain a file documenting the changes Licensee made to create that Covered
* Code and the date of any change. Licensee must include in that file the
* documentation of any changes made by any predecessor Licensee. Licensee
* must include a prominent statement that the modification is derived,
* directly or indirectly, from Original Intel Code.
*
* 3.2. Redistribution of Source with no Rights to Further Distribute Source.
* Redistribution of source code of any substantial portion of the Covered
* Code or modification without rights to further distribute source must
* include the following Disclaimer and Export Compliance provision in the
* documentation and/or other materials provided with distribution. In
* addition, Licensee may not authorize further sublicense of source of any
* portion of the Covered Code, and must include terms to the effect that the
* license from Licensee to its licensee is limited to the intellectual
* property embodied in the software Licensee provides to its licensee, and
* not to intellectual property embodied in modifications its licensee may
* make.
*
* 3.3. Redistribution of Executable. Redistribution in executable form of any
* substantial portion of the Covered Code or modification must reproduce the
* above Copyright Notice, and the following Disclaimer and Export Compliance
* provision in the documentation and/or other materials provided with the
* distribution.
*
* 3.4. Intel retains all right, title, and interest in and to the Original
* Intel Code.
*
* 3.5. Neither the name Intel nor any other trademark owned or controlled by
* Intel shall be used in advertising or otherwise to promote the sale, use or
* other dealings in products derived from or relating to the Covered Code
* without prior written authorization from Intel.
*
* 4. Disclaimer and Export Compliance
*
* 4.1. INTEL MAKES NO WARRANTY OF ANY KIND REGARDING ANY SOFTWARE PROVIDED
* HERE. ANY SOFTWARE ORIGINATING FROM INTEL OR DERIVED FROM INTEL SOFTWARE
* IS PROVIDED "AS IS," AND INTEL WILL NOT PROVIDE ANY SUPPORT, ASSISTANCE,
* INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY
* UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A
* PARTICULAR PURPOSE.
*
* 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES
* OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR
* COSTS OF PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, OR FOR ANY INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THIS AGREEMENT, UNDER ANY
* CAUSE OF ACTION OR THEORY OF LIABILITY, AND IRRESPECTIVE OF WHETHER INTEL
* HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. THESE LIMITATIONS
* SHALL APPLY NOTWITHSTANDING THE FAILURE OF THE ESSENTIAL PURPOSE OF ANY
* LIMITED REMEDY.
*
* 4.3. Licensee shall not export, either directly or indirectly, any of this
* software or system incorporating such software without first obtaining any
* required license or other approval from the U. S. Department of Commerce or
* any other agency or department of the United States Government. In the
* event Licensee exports any such software from the United States or
* re-exports any such software from a foreign destination, Licensee shall
* ensure that the distribution and export/re-export of the software is in
* compliance with all laws, regulations, orders, or other restrictions of the
* U.S. Export Administration Regulations. Licensee agrees that neither it nor
* any of its subsidiaries will export/re-export any technical data, process,
* software, or service, directly or indirectly, to any country for which the
* United States government or any agency thereof requires an export license,
* other governmental approval, or letter of assurance, without first obtaining
* such license, approval or letter.
*
*****************************************************************************
*
* Alternatively, you may choose to be licensed under the terms of the
* following license:
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
* substantially similar to the "NO WARRANTY" disclaimer below
* ("Disclaimer") and any redistribution must be conditioned upon
* including a substantially similar Disclaimer requirement for further
* binary redistribution.
* 3. Neither the names of the above-listed copyright holders nor the names
* of any contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Alternatively, you may choose to be licensed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
*****************************************************************************/
#include "acpi.h"
#include "accommon.h"
#include "acdisasm.h"
#include "actbinfo.h"
/* This module used for application-level code only */
#define _COMPONENT ACPI_CA_DISASSEMBLER
ACPI_MODULE_NAME ("dmtbinfo2")
/*
* How to add a new table:
*
* - Add the C table definition to the actbl1.h or actbl2.h header.
* - Add ACPI_xxxx_OFFSET macro(s) for the table (and subtables) to list below.
* - Define the table in this file (for the disassembler). If any
* new data types are required (ACPI_DMT_*), see below.
* - Add an external declaration for the new table definition (AcpiDmTableInfo*)
* in acdisam.h
* - Add new table definition to the dispatch table in dmtable.c (AcpiDmTableData)
* If a simple table (with no subtables), no disassembly code is needed.
* Otherwise, create the AcpiDmDump* function for to disassemble the table
* and add it to the dmtbdump.c file.
* - Add an external declaration for the new AcpiDmDump* function in acdisasm.h
* - Add the new AcpiDmDump* function to the dispatch table in dmtable.c
* - Create a template for the new table
* - Add data table compiler support
*
* How to add a new data type (ACPI_DMT_*):
*
* - Add new type at the end of the ACPI_DMT list in acdisasm.h
* - Add length and implementation cases in dmtable.c (disassembler)
* - Add type and length cases in dtutils.c (DT compiler)
*/
/*
* Remaining tables are not consumed directly by the ACPICA subsystem
*/
/*******************************************************************************
*
* AGDI - Arm Generic Diagnostic Dump and Reset Device Interface
*
* Conforms to "ACPI for Arm Components 1.1, Platform Design Document"
* ARM DEN0093 v1.1
*
******************************************************************************/
ACPI_DMTABLE_INFO AcpiDmTableInfoAgdi[] =
{
{ACPI_DMT_UINT8, ACPI_AGDI_OFFSET (Flags), "Flags (decoded below)", 0},
{ACPI_DMT_FLAG0, ACPI_AGDI_FLAG_OFFSET (Flags, 0), "Signalling mode", 0},
{ACPI_DMT_UINT24, ACPI_AGDI_OFFSET (Reserved[0]), "Reserved", 0},
{ACPI_DMT_UINT32, ACPI_AGDI_OFFSET (SdeiEvent), "SdeiEvent", 0},
{ACPI_DMT_UINT32, ACPI_AGDI_OFFSET (Gsiv), "Gsiv", 0},
ACPI_DMT_TERMINATOR
};
/*******************************************************************************
*
* APMT - ARM Performance Monitoring Unit Table
*
* Conforms to:
* ARM Performance Monitoring Unit Architecture 1.0 Platform Design Document
* ARM DEN0117 v1.0 November 25, 2021
*
******************************************************************************/
ACPI_DMTABLE_INFO AcpiDmTableInfoApmtNode[] =
{
{ACPI_DMT_UINT16, ACPI_APMTN_OFFSET (Length), "Length of APMT Node", 0},
{ACPI_DMT_UINT8, ACPI_APMTN_OFFSET (Flags), "Node Flags", 0},
{ACPI_DMT_FLAG0, ACPI_APMTN_FLAG_OFFSET (Flags, 0), "Dual Page Extension", 0},
{ACPI_DMT_FLAG1, ACPI_APMTN_FLAG_OFFSET (Flags, 0), "Processor Affinity Type", 0},
{ACPI_DMT_FLAG2, ACPI_APMTN_FLAG_OFFSET (Flags, 0), "64-bit Atomic Support", 0},
{ACPI_DMT_UINT8, ACPI_APMTN_OFFSET (Type), "Node Type", 0},
{ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (Id), "Unique Node Identifier", 0},
{ACPI_DMT_UINT64, ACPI_APMTN_OFFSET (InstPrimary), "Primary Node Instance", 0},
{ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (InstSecondary), "Secondary Node Instance", 0},
{ACPI_DMT_UINT64, ACPI_APMTN_OFFSET (BaseAddress0), "Page 0 Base Address", 0},
{ACPI_DMT_UINT64, ACPI_APMTN_OFFSET (BaseAddress1), "Page 1 Base Address", 0},
{ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (OvflwIrq), "Overflow Interrupt ID", 0},
{ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (Reserved), "Reserved", 0},
{ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (OvflwIrqFlags), "Overflow Interrupt Flags", 0},
{ACPI_DMT_FLAG0, ACPI_APMTN_FLAG_OFFSET (OvflwIrqFlags, 0), "Interrupt Mode", 0},
{ACPI_DMT_FLAG1, ACPI_APMTN_FLAG_OFFSET (OvflwIrqFlags, 0), "Interrupt Type", 0},
{ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (ProcAffinity), "Processor Affinity", 0},
{ACPI_DMT_UINT32, ACPI_APMTN_OFFSET (ImplId), "Implementation ID", 0},
ACPI_DMT_TERMINATOR
};
/*******************************************************************************
*
* IORT - IO Remapping Table
*
******************************************************************************/
ACPI_DMTABLE_INFO AcpiDmTableInfoIort[] =
{
{ACPI_DMT_UINT32, ACPI_IORT_OFFSET (NodeCount), "Node Count", 0},
{ACPI_DMT_UINT32, ACPI_IORT_OFFSET (NodeOffset), "Node Offset", 0},
{ACPI_DMT_UINT32, ACPI_IORT_OFFSET (Reserved), "Reserved", 0},
ACPI_DMT_TERMINATOR
};
/* Optional padding field */
ACPI_DMTABLE_INFO AcpiDmTableInfoIortPad[] =
{
{ACPI_DMT_RAW_BUFFER, 0, "Optional Padding", DT_OPTIONAL},
ACPI_DMT_TERMINATOR
};
/* Common Subtable header (one per Subtable) */
ACPI_DMTABLE_INFO AcpiDmTableInfoIortHdr[] =
{
{ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Type), "Type", 0},
{ACPI_DMT_UINT16, ACPI_IORTH_OFFSET (Length), "Length", DT_LENGTH},
{ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Revision), "Revision", 0},
{ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (Identifier), "Reserved", 0},
{ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingCount), "Mapping Count", 0},
{ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingOffset), "Mapping Offset", 0},
ACPI_DMT_TERMINATOR
};
/* Common Subtable header (one per Subtable)- Revision 3 */
ACPI_DMTABLE_INFO AcpiDmTableInfoIortHdr3[] =
{
{ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Type), "Type", 0},
{ACPI_DMT_UINT16, ACPI_IORTH_OFFSET (Length), "Length", DT_LENGTH},
{ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Revision), "Revision", 0},
{ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (Identifier), "Identifier", 0},
{ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingCount), "Mapping Count", 0},
{ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingOffset), "Mapping Offset", 0},
ACPI_DMT_TERMINATOR
};
ACPI_DMTABLE_INFO AcpiDmTableInfoIortMap[] =
{
{ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (InputBase), "Input base", DT_OPTIONAL},
{ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (IdCount), "ID Count", 0},
{ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (OutputBase), "Output Base", 0},
{ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (OutputReference), "Output Reference", 0},
{ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (Flags), "Flags (decoded below)", 0},
{ACPI_DMT_FLAG0, ACPI_IORTM_FLAG_OFFSET (Flags, 0), "Single Mapping", 0},
ACPI_DMT_TERMINATOR
};
ACPI_DMTABLE_INFO AcpiDmTableInfoIortAcc[] =
{
{ACPI_DMT_UINT32, ACPI_IORTA_OFFSET (CacheCoherency), "Cache Coherency", 0},
{ACPI_DMT_UINT8, ACPI_IORTA_OFFSET (Hints), "Hints (decoded below)", 0},
{ACPI_DMT_FLAG0, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Transient", 0},
{ACPI_DMT_FLAG1, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Write Allocate", 0},
{ACPI_DMT_FLAG2, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Read Allocate", 0},
{ACPI_DMT_FLAG3, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Override", 0},
{ACPI_DMT_UINT16, ACPI_IORTA_OFFSET (Reserved), "Reserved", 0},
{ACPI_DMT_UINT8, ACPI_IORTA_OFFSET (MemoryFlags), "Memory Flags (decoded below)", 0},
{ACPI_DMT_FLAG0, ACPI_IORTA_FLAG_OFFSET (MemoryFlags, 0), "Coherency", 0},
{ACPI_DMT_FLAG1, ACPI_IORTA_FLAG_OFFSET (MemoryFlags, 0), "Device Attribute", 0},
ACPI_DMT_TERMINATOR
};
/* IORT subtables */
/* 0x00: ITS Group */
ACPI_DMTABLE_INFO AcpiDmTableInfoIort0[] =
{
{ACPI_DMT_UINT32, ACPI_IORT0_OFFSET (ItsCount), "ItsCount", 0},
ACPI_DMT_TERMINATOR
};
ACPI_DMTABLE_INFO AcpiDmTableInfoIort0a[] =
{
{ACPI_DMT_UINT32, 0, "Identifiers", DT_OPTIONAL},
ACPI_DMT_TERMINATOR
};
/* 0x01: Named Component */
ACPI_DMTABLE_INFO AcpiDmTableInfoIort1[] =
{
{ACPI_DMT_UINT32, ACPI_IORT1_OFFSET (NodeFlags), "Node Flags", 0},
{ACPI_DMT_IORTMEM, ACPI_IORT1_OFFSET (MemoryProperties), "Memory Properties", 0},
{ACPI_DMT_UINT8, ACPI_IORT1_OFFSET (MemoryAddressLimit), "Memory Size Limit", 0},
{ACPI_DMT_STRING, ACPI_IORT1_OFFSET (DeviceName[0]), "Device Name", 0},
ACPI_DMT_TERMINATOR
};
ACPI_DMTABLE_INFO AcpiDmTableInfoIort1a[] =
{
{ACPI_DMT_RAW_BUFFER, 0, "Padding", DT_OPTIONAL},
ACPI_DMT_TERMINATOR
};
/* 0x02: PCI Root Complex */
ACPI_DMTABLE_INFO AcpiDmTableInfoIort2[] =
{
{ACPI_DMT_IORTMEM, ACPI_IORT2_OFFSET (MemoryProperties), "Memory Properties", 0},
{ACPI_DMT_UINT32, ACPI_IORT2_OFFSET (AtsAttribute), "ATS Attribute", 0},
{ACPI_DMT_UINT32, ACPI_IORT2_OFFSET (PciSegmentNumber), "PCI Segment Number", 0},
{ACPI_DMT_UINT8, ACPI_IORT2_OFFSET (MemoryAddressLimit), "Memory Size Limit", 0},
{ACPI_DMT_UINT16, ACPI_IORT2_OFFSET (PasidCapabilities), "PASID Capabilities", 0},
{ACPI_DMT_UINT8, ACPI_IORT2_OFFSET (Reserved[0]), "Reserved", 0},
ACPI_DMT_TERMINATOR
};
/* 0x03: SMMUv1/2 */
ACPI_DMTABLE_INFO AcpiDmTableInfoIort3[] =
{
{ACPI_DMT_UINT64, ACPI_IORT3_OFFSET (BaseAddress), "Base Address", 0},
{ACPI_DMT_UINT64, ACPI_IORT3_OFFSET (Span), "Span", 0},
{ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (Model), "Model", 0},
{ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (Flags), "Flags (decoded below)", 0},
{ACPI_DMT_FLAG0, ACPI_IORT3_FLAG_OFFSET (Flags, 0), "DVM Supported", 0},
{ACPI_DMT_FLAG1, ACPI_IORT3_FLAG_OFFSET (Flags, 0), "Coherent Walk", 0},
{ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (GlobalInterruptOffset), "Global Interrupt Offset", 0},
{ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (ContextInterruptCount), "Context Interrupt Count", 0},
{ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (ContextInterruptOffset), "Context Interrupt Offset", 0},
{ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (PmuInterruptCount), "PMU Interrupt Count", 0},
{ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (PmuInterruptOffset), "PMU Interrupt Offset", 0},
ACPI_DMT_TERMINATOR
};
ACPI_DMTABLE_INFO AcpiDmTableInfoIort3a[] =
{
{ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgIrpt), "NSgIrpt", 0},
{ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgIrptFlags), "NSgIrpt Flags (decoded below)", 0},
{ACPI_DMT_FLAG0, ACPI_IORT3a_FLAG_OFFSET (NSgIrptFlags, 0), "Edge Triggered", 0},
{ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgCfgIrpt), "NSgCfgIrpt", 0},
{ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgCfgIrptFlags), "NSgCfgIrpt Flags (decoded below)", 0},
{ACPI_DMT_FLAG0, ACPI_IORT3a_FLAG_OFFSET (NSgCfgIrptFlags, 0), "Edge Triggered", 0},
ACPI_DMT_TERMINATOR
};
ACPI_DMTABLE_INFO AcpiDmTableInfoIort3b[] =
{
{ACPI_DMT_UINT64, 0, "Context Interrupt", DT_OPTIONAL},
ACPI_DMT_TERMINATOR
};
ACPI_DMTABLE_INFO AcpiDmTableInfoIort3c[] =
{
{ACPI_DMT_UINT64, 0, "PMU Interrupt", DT_OPTIONAL},
ACPI_DMT_TERMINATOR
};
/* 0x04: SMMUv3 */
ACPI_DMTABLE_INFO AcpiDmTableInfoIort4[] =
{
{ACPI_DMT_UINT64, ACPI_IORT4_OFFSET (BaseAddress), "Base Address", 0},
{ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Flags), "Flags (decoded below)", 0},
{ACPI_DMT_FLAG0, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "COHACC Override", 0},
{ACPI_DMT_FLAG1, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "HTTU Override", 0},
{ACPI_DMT_FLAG3, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "Proximity Domain Valid", 0},
{ACPI_DMT_FLAG4, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "DeviceID Valid", 0},
{ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Reserved), "Reserved", 0},
{ACPI_DMT_UINT64, ACPI_IORT4_OFFSET (VatosAddress), "VATOS Address", 0},
{ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Model), "Model", 0},
{ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (EventGsiv), "Event GSIV", 0},
{ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (PriGsiv), "PRI GSIV", 0},
{ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (GerrGsiv), "GERR GSIV", 0},
{ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (SyncGsiv), "Sync GSIV", 0},
{ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Pxm), "Proximity Domain", 0},
{ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (IdMappingIndex), "Device ID Mapping Index", 0},
ACPI_DMT_TERMINATOR
};
/* 0x05: PMCG */
ACPI_DMTABLE_INFO AcpiDmTableInfoIort5[] =
{
{ACPI_DMT_UINT64, ACPI_IORT5_OFFSET (Page0BaseAddress), "Page 0 Base Address", 0},
{ACPI_DMT_UINT32, ACPI_IORT5_OFFSET (OverflowGsiv), "Overflow Interrupt GSIV", 0},
{ACPI_DMT_UINT32, ACPI_IORT5_OFFSET (NodeReference), "Node Reference", 0},
{ACPI_DMT_UINT64, ACPI_IORT5_OFFSET (Page1BaseAddress), "Page 1 Base Address", 0},
ACPI_DMT_TERMINATOR
};
/* 0x06: RMR */
ACPI_DMTABLE_INFO AcpiDmTableInfoIort6[] =
{
{ACPI_DMT_UINT32, ACPI_IORT6_OFFSET (Flags), "Flags (decoded below)", 0},
{ACPI_DMT_FLAG0, ACPI_IORT6_FLAG_OFFSET (Flags, 0), "Remapping Permitted", 0},
{ACPI_DMT_FLAG1, ACPI_IORT6_FLAG_OFFSET (Flags, 0), "Access Privileged", 0},
{ACPI_DMT_FLAGS8_2, ACPI_IORT6_FLAG_OFFSET (Flags, 0), "Access Attributes", 0},
{ACPI_DMT_UINT32, ACPI_IORT6_OFFSET (RmrCount), "Number of RMR Descriptors", 0},
{ACPI_DMT_UINT32, ACPI_IORT6_OFFSET (RmrOffset), "RMR Descriptor Offset", 0},
ACPI_DMT_TERMINATOR
};
ACPI_DMTABLE_INFO AcpiDmTableInfoIort6a[] =
{
{ACPI_DMT_UINT64, ACPI_IORT6A_OFFSET (BaseAddress), "Base Address of RMR", DT_OPTIONAL},
{ACPI_DMT_UINT64, ACPI_IORT6A_OFFSET (Length), "Length of RMR", 0},
{ACPI_DMT_UINT32, ACPI_IORT6A_OFFSET (Reserved), "Reserved", 0},
ACPI_DMT_TERMINATOR
};
/*******************************************************************************
*
* IVRS - I/O Virtualization Reporting Structure
*
******************************************************************************/
ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs[] =
{
{ACPI_DMT_UINT32, ACPI_IVRS_OFFSET (Info), "Virtualization Info", 0},
{ACPI_DMT_UINT64, ACPI_IVRS_OFFSET (Reserved), "Reserved", 0},
ACPI_DMT_TERMINATOR
};
/* IVRS subtables */
/* 0x10: I/O Virtualization Hardware Definition (IVHD) Block */
ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHware1[] =
{
{ACPI_DMT_IVRS, ACPI_IVRSH_OFFSET (Type), "Subtable Type", 0},
{ACPI_DMT_UINT8, ACPI_IVRSH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG},
{ACPI_DMT_FLAG0, ACPI_IVRS_FLAG_OFFSET (Flags,0), "HtTunEn", 0},
{ACPI_DMT_FLAG1, ACPI_IVRS_FLAG_OFFSET (Flags,0), "PassPW", 0},
{ACPI_DMT_FLAG2, ACPI_IVRS_FLAG_OFFSET (Flags,0), "ResPassPW", 0},
{ACPI_DMT_FLAG3, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Isoc Control", 0},
{ACPI_DMT_FLAG4, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Iotlb Support", 0},
{ACPI_DMT_FLAG5, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Coherent", 0},
{ACPI_DMT_FLAG6, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Prefetch Support", 0},
{ACPI_DMT_FLAG7, ACPI_IVRS_FLAG_OFFSET (Flags,0), "PPR Support", 0},
{ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (Length), "Length", DT_LENGTH},
{ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (DeviceId), "DeviceId", 0},
{ACPI_DMT_UINT16, ACPI_IVRS0_OFFSET (CapabilityOffset), "Capability Offset", 0},
{ACPI_DMT_UINT64, ACPI_IVRS0_OFFSET (BaseAddress), "Base Address", 0},
{ACPI_DMT_UINT16, ACPI_IVRS0_OFFSET (PciSegmentGroup), "PCI Segment Group", 0},
{ACPI_DMT_UINT16, ACPI_IVRS0_OFFSET (Info), "Virtualization Info", 0},
{ACPI_DMT_UINT32, ACPI_IVRS0_OFFSET (FeatureReporting), "Feature Reporting", 0},
ACPI_DMT_TERMINATOR
};
/* 0x11, 0x40: I/O Virtualization Hardware Definition (IVHD) Block */
ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHware23[] =
{
{ACPI_DMT_IVRS, ACPI_IVRSH_OFFSET (Type), "Subtable Type", 0},
{ACPI_DMT_UINT8, ACPI_IVRSH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG},
{ACPI_DMT_FLAG0, ACPI_IVRS_FLAG_OFFSET (Flags,0), "HtTunEn", 0},
{ACPI_DMT_FLAG1, ACPI_IVRS_FLAG_OFFSET (Flags,0), "PassPW", 0},
{ACPI_DMT_FLAG2, ACPI_IVRS_FLAG_OFFSET (Flags,0), "ResPassPW", 0},
{ACPI_DMT_FLAG3, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Isoc Control", 0},
{ACPI_DMT_FLAG4, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Iotlb Support", 0},
{ACPI_DMT_FLAG5, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Coherent", 0},
{ACPI_DMT_FLAG6, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Prefetch Support", 0},
{ACPI_DMT_FLAG7, ACPI_IVRS_FLAG_OFFSET (Flags,0), "PPR Support", 0},
{ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (Header.Length), "Length", DT_LENGTH},
{ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (Header.DeviceId), "DeviceId", 0},
{ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (CapabilityOffset), "Capability Offset", 0},
{ACPI_DMT_UINT64, ACPI_IVRS01_OFFSET (BaseAddress), "Base Address", 0},
{ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (PciSegmentGroup), "PCI Segment Group", 0},
{ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (Info), "Virtualization Info", 0},
{ACPI_DMT_UINT32, ACPI_IVRS01_OFFSET (Attributes), "Attributes", 0},
{ACPI_DMT_UINT64, ACPI_IVRS01_OFFSET (EfrRegisterImage), "EFR Image", 0},
{ACPI_DMT_UINT64, ACPI_IVRS01_OFFSET (Reserved), "Reserved", 0},
ACPI_DMT_TERMINATOR
};
/* 0x20, 0x21, 0x22: I/O Virtualization Memory Definition (IVMD) Device Entry Block */
ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsMemory[] =
{
{ACPI_DMT_IVRS, ACPI_IVRSH_OFFSET (Type), "Subtable Type", 0},
{ACPI_DMT_UINT8, ACPI_IVRSH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG},
{ACPI_DMT_FLAG0, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Unity", 0},
{ACPI_DMT_FLAG1, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Readable", 0},
{ACPI_DMT_FLAG2, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Writeable", 0},
{ACPI_DMT_FLAG3, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Exclusion Range", 0},
{ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (Length), "Length", DT_LENGTH},
{ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (DeviceId), "DeviceId", 0},
{ACPI_DMT_UINT16, ACPI_IVRS1_OFFSET (AuxData), "Auxiliary Data", 0},
{ACPI_DMT_UINT64, ACPI_IVRS1_OFFSET (Reserved), "Reserved", 0},
{ACPI_DMT_UINT64, ACPI_IVRS1_OFFSET (StartAddress), "Start Address", 0},
{ACPI_DMT_UINT64, ACPI_IVRS1_OFFSET (MemoryLength), "Memory Length", 0},
ACPI_DMT_TERMINATOR
};
/* Device entry header for IVHD block */
#define ACPI_DMT_IVRS_DE_HEADER \
{ACPI_DMT_IVRS_DE, ACPI_IVRSD_OFFSET (Type), "Subtable Type", 0}, \
{ACPI_DMT_UINT16, ACPI_IVRSD_OFFSET (Id), "Device ID", 0}, \
{ACPI_DMT_UINT8, ACPI_IVRSD_OFFSET (DataSetting), "Data Setting (decoded below)", 0}, \
{ACPI_DMT_FLAG0, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "INITPass", 0}, \
{ACPI_DMT_FLAG1, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "EIntPass", 0}, \
{ACPI_DMT_FLAG2, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "NMIPass", 0}, \
{ACPI_DMT_FLAG3, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "Reserved", 0}, \
{ACPI_DMT_FLAGS4, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "System MGMT", 0}, \
{ACPI_DMT_FLAG6, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "LINT0 Pass", 0}, \
{ACPI_DMT_FLAG7, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "LINT1 Pass", 0}
/* 4-byte device entry (Types 1,2,3,4) */
ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs4[] =
{
ACPI_DMT_IVRS_DE_HEADER,
ACPI_DMT_TERMINATOR
};
/* 8-byte device entry (Type Alias Select, Alias Start of Range) */
ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs8a[] =
{
ACPI_DMT_IVRS_DE_HEADER,
{ACPI_DMT_UINT8, ACPI_IVRS8A_OFFSET (Reserved1), "Reserved", 0},
{ACPI_DMT_UINT16, ACPI_IVRS8A_OFFSET (UsedId), "Source Used Device ID", 0},
{ACPI_DMT_UINT8, ACPI_IVRS8A_OFFSET (Reserved2), "Reserved", 0},
ACPI_DMT_TERMINATOR
};
/* 8-byte device entry (Type Extended Select, Extended Start of Range) */
ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs8b[] =
{
ACPI_DMT_IVRS_DE_HEADER,
{ACPI_DMT_UINT32, ACPI_IVRS8B_OFFSET (ExtendedData), "Extended Data", 0},
ACPI_DMT_TERMINATOR
};
/* 8-byte device entry (Type Special Device) */
ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs8c[] =
{
ACPI_DMT_IVRS_DE_HEADER,
{ACPI_DMT_UINT8, ACPI_IVRS8C_OFFSET (Handle), "Handle", 0},
{ACPI_DMT_UINT16, ACPI_IVRS8C_OFFSET (UsedId), "Source Used Device ID", 0},
{ACPI_DMT_UINT8, ACPI_IVRS8C_OFFSET (Variety), "Variety", 0},
ACPI_DMT_TERMINATOR
};
/* Variable-length Device Entry Type 0xF0 */
ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHid[] =
{
ACPI_DMT_IVRS_DE_HEADER,
ACPI_DMT_TERMINATOR
};
ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsUidString[] =
{
{ACPI_DMT_UINT8, 0, "UID Format", DT_DESCRIBES_OPTIONAL},
{ACPI_DMT_UINT8, 1, "UID Length", DT_DESCRIBES_OPTIONAL},
{ACPI_DMT_IVRS_UNTERMINATED_STRING, 2, "UID", DT_OPTIONAL},
ACPI_DMT_TERMINATOR
};
ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsUidInteger[] =
{
{ACPI_DMT_UINT8, 0, "UID Format", DT_DESCRIBES_OPTIONAL},
{ACPI_DMT_UINT8, 1, "UID Length", DT_DESCRIBES_OPTIONAL},
{ACPI_DMT_UINT64, 2, "UID", DT_OPTIONAL},
ACPI_DMT_TERMINATOR
};
ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHidString[] =
{
{ACPI_DMT_NAME8, 0, "ACPI HID", 0},
ACPI_DMT_TERMINATOR
};
ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHidInteger[] =
{
{ACPI_DMT_UINT64, 0, "ACPI HID", 0},
ACPI_DMT_TERMINATOR
};
ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsCidString[] =
{
{ACPI_DMT_NAME8, 0, "ACPI CID", 0},
ACPI_DMT_TERMINATOR
};
ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsCidInteger[] =
{
{ACPI_DMT_UINT64, 0, "ACPI CID", 0},
ACPI_DMT_TERMINATOR
};
/*******************************************************************************
*
* LPIT - Low Power Idle Table
*
******************************************************************************/
/* Main table consists only of the standard ACPI table header */
/* Common Subtable header (one per Subtable) */
ACPI_DMTABLE_INFO AcpiDmTableInfoLpitHdr[] =
{
{ACPI_DMT_LPIT, ACPI_LPITH_OFFSET (Type), "Subtable Type", 0},
{ACPI_DMT_UINT32, ACPI_LPITH_OFFSET (Length), "Length", DT_LENGTH},
{ACPI_DMT_UINT16, ACPI_LPITH_OFFSET (UniqueId), "Unique ID", 0},
{ACPI_DMT_UINT16, ACPI_LPITH_OFFSET (Reserved), "Reserved", 0},
{ACPI_DMT_UINT32, ACPI_LPITH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG},
{ACPI_DMT_FLAG0, ACPI_LPITH_FLAG_OFFSET (Flags, 0), "State Disabled", 0},
{ACPI_DMT_FLAG1, ACPI_LPITH_FLAG_OFFSET (Flags, 0), "No Counter", 0},
ACPI_DMT_TERMINATOR
};
/* LPIT Subtables */
/* 0: Native C-state */
ACPI_DMTABLE_INFO AcpiDmTableInfoLpit0[] =
{
{ACPI_DMT_GAS, ACPI_LPIT0_OFFSET (EntryTrigger), "Entry Trigger", 0},
{ACPI_DMT_UINT32, ACPI_LPIT0_OFFSET (Residency), "Residency", 0},
{ACPI_DMT_UINT32, ACPI_LPIT0_OFFSET (Latency), "Latency", 0},
{ACPI_DMT_GAS, ACPI_LPIT0_OFFSET (ResidencyCounter), "Residency Counter", 0},
{ACPI_DMT_UINT64, ACPI_LPIT0_OFFSET (CounterFrequency), "Counter Frequency", 0},
ACPI_DMT_TERMINATOR
};
/*******************************************************************************
*
* MADT - Multiple APIC Description Table and subtables
*
******************************************************************************/
ACPI_DMTABLE_INFO AcpiDmTableInfoMadt[] =
{
{ACPI_DMT_UINT32, ACPI_MADT_OFFSET (Address), "Local Apic Address", 0},
{ACPI_DMT_UINT32, ACPI_MADT_OFFSET (Flags), "Flags (decoded below)", DT_FLAG},
{ACPI_DMT_FLAG0, ACPI_MADT_FLAG_OFFSET (Flags,0), "PC-AT Compatibility", 0},
ACPI_DMT_TERMINATOR
};
/* Common Subtable header (one per Subtable) */
ACPI_DMTABLE_INFO AcpiDmTableInfoMadtHdr[] =
{
{ACPI_DMT_MADT, ACPI_MADTH_OFFSET (Type), "Subtable Type", 0},
{ACPI_DMT_UINT8, ACPI_MADTH_OFFSET (Length), "Length", DT_LENGTH},
ACPI_DMT_TERMINATOR
};
/* MADT Subtables */
/* 0: processor APIC */
ACPI_DMTABLE_INFO AcpiDmTableInfoMadt0[] =
{
{ACPI_DMT_UINT8, ACPI_MADT0_OFFSET (ProcessorId), "Processor ID", 0},
{ACPI_DMT_UINT8, ACPI_MADT0_OFFSET (Id), "Local Apic ID", 0},
{ACPI_DMT_UINT32, ACPI_MADT0_OFFSET (LapicFlags), "Flags (decoded below)", DT_FLAG},
{ACPI_DMT_FLAG0, ACPI_MADT0_FLAG_OFFSET (LapicFlags,0), "Processor Enabled", 0},
{ACPI_DMT_FLAG1, ACPI_MADT0_FLAG_OFFSET (LapicFlags,0), "Runtime Online Capable", 0},
ACPI_DMT_TERMINATOR
};
/* 1: IO APIC */
ACPI_DMTABLE_INFO AcpiDmTableInfoMadt1[] =
{
{ACPI_DMT_UINT8, ACPI_MADT1_OFFSET (Id), "I/O Apic ID", 0},
{ACPI_DMT_UINT8, ACPI_MADT1_OFFSET (Reserved), "Reserved", 0},
{ACPI_DMT_UINT32, ACPI_MADT1_OFFSET (Address), "Address", 0},
{ACPI_DMT_UINT32, ACPI_MADT1_OFFSET (GlobalIrqBase), "Interrupt", 0},
ACPI_DMT_TERMINATOR
};
/* 2: Interrupt Override */
ACPI_DMTABLE_INFO AcpiDmTableInfoMadt2[] =
{
{ACPI_DMT_UINT8, ACPI_MADT2_OFFSET (Bus), "Bus", 0},
{ACPI_DMT_UINT8, ACPI_MADT2_OFFSET (SourceIrq), "Source", 0},
{ACPI_DMT_UINT32, ACPI_MADT2_OFFSET (GlobalIrq), "Interrupt", 0},
{ACPI_DMT_UINT16, ACPI_MADT2_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG},
{ACPI_DMT_FLAGS0, ACPI_MADT2_FLAG_OFFSET (IntiFlags,0), "Polarity", 0},
{ACPI_DMT_FLAGS2, ACPI_MADT2_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0},
ACPI_DMT_TERMINATOR
};
/* 3: NMI Sources */
ACPI_DMTABLE_INFO AcpiDmTableInfoMadt3[] =
{
{ACPI_DMT_UINT16, ACPI_MADT3_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG},
{ACPI_DMT_FLAGS0, ACPI_MADT3_FLAG_OFFSET (IntiFlags,0), "Polarity", 0},
{ACPI_DMT_FLAGS2, ACPI_MADT3_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0},
{ACPI_DMT_UINT32, ACPI_MADT3_OFFSET (GlobalIrq), "Interrupt", 0},
ACPI_DMT_TERMINATOR
};
/* 4: Local APIC NMI */
ACPI_DMTABLE_INFO AcpiDmTableInfoMadt4[] =
{
{ACPI_DMT_UINT8, ACPI_MADT4_OFFSET (ProcessorId), "Processor ID", 0},
{ACPI_DMT_UINT16, ACPI_MADT4_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG},
{ACPI_DMT_FLAGS0, ACPI_MADT4_FLAG_OFFSET (IntiFlags,0), "Polarity", 0},
{ACPI_DMT_FLAGS2, ACPI_MADT4_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0},
{ACPI_DMT_UINT8, ACPI_MADT4_OFFSET (Lint), "Interrupt Input LINT", 0},
ACPI_DMT_TERMINATOR
};
/* 5: Address Override */
ACPI_DMTABLE_INFO AcpiDmTableInfoMadt5[] =
{
{ACPI_DMT_UINT16, ACPI_MADT5_OFFSET (Reserved), "Reserved", 0},
{ACPI_DMT_UINT64, ACPI_MADT5_OFFSET (Address), "APIC Address", 0},
ACPI_DMT_TERMINATOR
};
/* 6: I/O Sapic */
ACPI_DMTABLE_INFO AcpiDmTableInfoMadt6[] =
{
{ACPI_DMT_UINT8, ACPI_MADT6_OFFSET (Id), "I/O Sapic ID", 0},
{ACPI_DMT_UINT8, ACPI_MADT6_OFFSET (Reserved), "Reserved", 0},
{ACPI_DMT_UINT32, ACPI_MADT6_OFFSET (GlobalIrqBase), "Interrupt Base", 0},
{ACPI_DMT_UINT64, ACPI_MADT6_OFFSET (Address), "Address", 0},
ACPI_DMT_TERMINATOR
};
/* 7: Local Sapic */
ACPI_DMTABLE_INFO AcpiDmTableInfoMadt7[] =
{
{ACPI_DMT_UINT8, ACPI_MADT7_OFFSET (ProcessorId), "Processor ID", 0},
{ACPI_DMT_UINT8, ACPI_MADT7_OFFSET (Id), "Local Sapic ID", 0},
{ACPI_DMT_UINT8, ACPI_MADT7_OFFSET (Eid), "Local Sapic EID", 0},
{ACPI_DMT_UINT24, ACPI_MADT7_OFFSET (Reserved[0]), "Reserved", 0},
{ACPI_DMT_UINT32, ACPI_MADT7_OFFSET (LapicFlags), "Flags (decoded below)", DT_FLAG},
{ACPI_DMT_FLAG0, ACPI_MADT7_FLAG_OFFSET (LapicFlags,0), "Processor Enabled", 0},
{ACPI_DMT_UINT32, ACPI_MADT7_OFFSET (Uid), "Processor UID", 0},
{ACPI_DMT_STRING, ACPI_MADT7_OFFSET (UidString[0]), "Processor UID String", 0},
ACPI_DMT_TERMINATOR
};
/* 8: Platform Interrupt Source */
ACPI_DMTABLE_INFO AcpiDmTableInfoMadt8[] =
{
{ACPI_DMT_UINT16, ACPI_MADT8_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG},
{ACPI_DMT_FLAGS0, ACPI_MADT8_FLAG_OFFSET (IntiFlags,0), "Polarity", 0},
{ACPI_DMT_FLAGS2, ACPI_MADT8_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0},
{ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (Type), "InterruptType", 0},
{ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (Id), "Processor ID", 0},
{ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (Eid), "Processor EID", 0},
{ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (IoSapicVector), "I/O Sapic Vector", 0},
{ACPI_DMT_UINT32, ACPI_MADT8_OFFSET (GlobalIrq), "Interrupt", 0},
{ACPI_DMT_UINT32, ACPI_MADT8_OFFSET (Flags), "Flags (decoded below)", DT_FLAG},
{ACPI_DMT_FLAG0, ACPI_MADT8_OFFSET (Flags), "CPEI Override", 0},
ACPI_DMT_TERMINATOR
};
/* 9: Processor Local X2_APIC (ACPI 4.0) */
ACPI_DMTABLE_INFO AcpiDmTableInfoMadt9[] =
{
{ACPI_DMT_UINT16, ACPI_MADT9_OFFSET (Reserved), "Reserved", 0},
{ACPI_DMT_UINT32, ACPI_MADT9_OFFSET (LocalApicId), "Processor x2Apic ID", 0},
{ACPI_DMT_UINT32, ACPI_MADT9_OFFSET (LapicFlags), "Flags (decoded below)", DT_FLAG},
{ACPI_DMT_FLAG0, ACPI_MADT9_FLAG_OFFSET (LapicFlags,0), "Processor Enabled", 0},
{ACPI_DMT_UINT32, ACPI_MADT9_OFFSET (Uid), "Processor UID", 0},
ACPI_DMT_TERMINATOR
};
/* 10: Local X2_APIC NMI (ACPI 4.0) */
ACPI_DMTABLE_INFO AcpiDmTableInfoMadt10[] =
{
{ACPI_DMT_UINT16, ACPI_MADT10_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG},
{ACPI_DMT_FLAGS0, ACPI_MADT10_FLAG_OFFSET (IntiFlags,0), "Polarity", 0},
{ACPI_DMT_FLAGS2, ACPI_MADT10_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0},
{ACPI_DMT_UINT32, ACPI_MADT10_OFFSET (Uid), "Processor UID", 0},
{ACPI_DMT_UINT8, ACPI_MADT10_OFFSET (Lint), "Interrupt Input LINT", 0},
{ACPI_DMT_UINT24, ACPI_MADT10_OFFSET (Reserved[0]), "Reserved", 0},
ACPI_DMT_TERMINATOR
};
/* 11: Generic Interrupt Controller (ACPI 5.0) */
ACPI_DMTABLE_INFO AcpiDmTableInfoMadt11[] =
{
{ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (Reserved), "Reserved", 0},
{ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (CpuInterfaceNumber), "CPU Interface Number", 0},
{ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (Uid), "Processor UID", 0},
{ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (Flags), "Flags (decoded below)", DT_FLAG},
{ACPI_DMT_FLAG0, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Processor Enabled", 0},
{ACPI_DMT_FLAG1, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Performance Interrupt Trigger Mode", 0},
{ACPI_DMT_FLAG2, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Virtual GIC Interrupt Trigger Mode", 0},
{ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (ParkingVersion), "Parking Protocol Version", 0},
{ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (PerformanceInterrupt), "Performance Interrupt", 0},
{ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ParkedAddress), "Parked Address", 0},
{ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (BaseAddress), "Base Address", 0},
{ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicvBaseAddress), "Virtual GIC Base Address", 0},
{ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GichBaseAddress), "Hypervisor GIC Base Address", 0},
{ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (VgicInterrupt), "Virtual GIC Interrupt", 0},
{ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicrBaseAddress), "Redistributor Base Address", 0},
{ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ArmMpidr), "ARM MPIDR", 0},
{ACPI_DMT_UINT8, ACPI_MADT11_OFFSET (EfficiencyClass), "Efficiency Class", 0},
{ACPI_DMT_UINT8, ACPI_MADT11_OFFSET (Reserved2[0]), "Reserved", 0},
{ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (SpeInterrupt), "SPE Overflow Interrupt", 0},
{ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (TrbeInterrupt), "TRBE Interrupt", 0},
ACPI_DMT_TERMINATOR
};
/* 12: Generic Interrupt Distributor (ACPI 5.0) */
ACPI_DMTABLE_INFO AcpiDmTableInfoMadt12[] =
{
{ACPI_DMT_UINT16, ACPI_MADT12_OFFSET (Reserved), "Reserved", 0},
{ACPI_DMT_UINT32, ACPI_MADT12_OFFSET (GicId), "Local GIC Hardware ID", 0},
{ACPI_DMT_UINT64, ACPI_MADT12_OFFSET (BaseAddress), "Base Address", 0},
{ACPI_DMT_UINT32, ACPI_MADT12_OFFSET (GlobalIrqBase), "Interrupt Base", 0},
{ACPI_DMT_UINT8, ACPI_MADT12_OFFSET (Version), "Version", 0},
{ACPI_DMT_UINT24, ACPI_MADT12_OFFSET (Reserved2[0]), "Reserved", 0},
ACPI_DMT_TERMINATOR
};
/* 13: Generic MSI Frame (ACPI 5.1) */
ACPI_DMTABLE_INFO AcpiDmTableInfoMadt13[] =
{
{ACPI_DMT_UINT16, ACPI_MADT13_OFFSET (Reserved), "Reserved", 0},
{ACPI_DMT_UINT32, ACPI_MADT13_OFFSET (MsiFrameId), "MSI Frame ID", 0},
{ACPI_DMT_UINT64, ACPI_MADT13_OFFSET (BaseAddress), "Base Address", 0},
{ACPI_DMT_UINT32, ACPI_MADT13_OFFSET (Flags), "Flags (decoded below)", DT_FLAG},
{ACPI_DMT_FLAG0, ACPI_MADT13_FLAG_OFFSET (Flags,0), "Select SPI", 0},
{ACPI_DMT_UINT16, ACPI_MADT13_OFFSET (SpiCount), "SPI Count", 0},
{ACPI_DMT_UINT16, ACPI_MADT13_OFFSET (SpiBase), "SPI Base", 0},
ACPI_DMT_TERMINATOR
};
/* 14: Generic Redistributor (ACPI 5.1) */
ACPI_DMTABLE_INFO AcpiDmTableInfoMadt14[] =
{
{ACPI_DMT_UINT16, ACPI_MADT14_OFFSET (Reserved), "Reserved", 0},
{ACPI_DMT_UINT64, ACPI_MADT14_OFFSET (BaseAddress), "Base Address", 0},
{ACPI_DMT_UINT32, ACPI_MADT14_OFFSET (Length), "Length", 0},
ACPI_DMT_TERMINATOR
};
/* 15: Generic Translator (ACPI 6.0) */
ACPI_DMTABLE_INFO AcpiDmTableInfoMadt15[] =
{
{ACPI_DMT_UINT16, ACPI_MADT15_OFFSET (Reserved), "Reserved", 0},
{ACPI_DMT_UINT32, ACPI_MADT15_OFFSET (TranslationId), "Translation ID", 0},
{ACPI_DMT_UINT64, ACPI_MADT15_OFFSET (BaseAddress), "Base Address", 0},
{ACPI_DMT_UINT32, ACPI_MADT15_OFFSET (Reserved2), "Reserved", 0},
ACPI_DMT_TERMINATOR
};
/* 16: Multiprocessor wakeup structure (ACPI 6.4) */
ACPI_DMTABLE_INFO AcpiDmTableInfoMadt16[] =
{
{ACPI_DMT_UINT16, ACPI_MADT16_OFFSET (MailboxVersion), "Mailbox Version", 0},
{ACPI_DMT_UINT32, ACPI_MADT16_OFFSET (Reserved), "Reserved", 0},
{ACPI_DMT_UINT64, ACPI_MADT16_OFFSET (BaseAddress), "Mailbox Address", 0},
ACPI_DMT_TERMINATOR
};
/* 17: core interrupt controller */
ACPI_DMTABLE_INFO AcpiDmTableInfoMadt17[] =
{
{ACPI_DMT_UINT8, ACPI_MADT17_OFFSET (Version), "Version", 0},
{ACPI_DMT_UINT32, ACPI_MADT17_OFFSET (ProcessorId), "ProcessorId", 0},
{ACPI_DMT_UINT32, ACPI_MADT17_OFFSET (CoreId), "CoreId", 0},
{ACPI_DMT_UINT32, ACPI_MADT17_OFFSET (Flags), "Flags", 0},
ACPI_DMT_TERMINATOR
};
/* 18: Legacy I/O interrupt controller */
ACPI_DMTABLE_INFO AcpiDmTableInfoMadt18[] =
{
{ACPI_DMT_UINT8, ACPI_MADT18_OFFSET (Version), "Version", 0},
{ACPI_DMT_UINT64, ACPI_MADT18_OFFSET (Address), "Address", 0},
{ACPI_DMT_UINT16, ACPI_MADT18_OFFSET (Size), "Size", 0},
{ACPI_DMT_UINT16, ACPI_MADT18_OFFSET (Cascade), "Cascade", 0},
{ACPI_DMT_UINT64, ACPI_MADT18_OFFSET (CascadeMap), "CascadeMap", 0},
ACPI_DMT_TERMINATOR
};
/* 19: HT interrupt controller */
ACPI_DMTABLE_INFO AcpiDmTableInfoMadt19[] =
{
{ACPI_DMT_UINT8, ACPI_MADT19_OFFSET (Version), "Version", 0},
{ACPI_DMT_UINT64, ACPI_MADT19_OFFSET (Address), "Address", 0},
{ACPI_DMT_UINT16, ACPI_MADT19_OFFSET (Size), "Size", 0},
{ACPI_DMT_UINT64, ACPI_MADT19_OFFSET (Cascade), "Cascade", 0},
ACPI_DMT_TERMINATOR
};
/* 20: Extend I/O interrupt controller */
ACPI_DMTABLE_INFO AcpiDmTableInfoMadt20[] =
{
{ACPI_DMT_UINT8, ACPI_MADT20_OFFSET (Version), "Version", 0},
{ACPI_DMT_UINT8, ACPI_MADT20_OFFSET (Cascade), "Cascade", 0},
{ACPI_DMT_UINT8, ACPI_MADT20_OFFSET (Node), "Node", 0},
{ACPI_DMT_UINT64, ACPI_MADT20_OFFSET (NodeMap), "NodeMap", 0},
ACPI_DMT_TERMINATOR
};
/* 21: MSI controller */
ACPI_DMTABLE_INFO AcpiDmTableInfoMadt21[] =
{
{ACPI_DMT_UINT8, ACPI_MADT21_OFFSET (Version), "Version", 0},
{ACPI_DMT_UINT64, ACPI_MADT21_OFFSET (MsgAddress), "MsgAddress", 0},
{ACPI_DMT_UINT32, ACPI_MADT21_OFFSET (Start), "Start", 0},
{ACPI_DMT_UINT32, ACPI_MADT21_OFFSET (Count), "Count", 0},
ACPI_DMT_TERMINATOR
};
/* 22: BIO interrupt controller */
ACPI_DMTABLE_INFO AcpiDmTableInfoMadt22[] =
{
{ACPI_DMT_UINT8, ACPI_MADT22_OFFSET (Version), "Version", 0},
{ACPI_DMT_UINT64, ACPI_MADT22_OFFSET (Address), "Address", 0},
{ACPI_DMT_UINT16, ACPI_MADT22_OFFSET (Size), "Size", 0},
{ACPI_DMT_UINT16, ACPI_MADT22_OFFSET (Id), "Id", 0},
{ACPI_DMT_UINT16, ACPI_MADT22_OFFSET (GsiBase), "GsiBase", 0},
ACPI_DMT_TERMINATOR
};
/* 23: LPC interrupt controller */
ACPI_DMTABLE_INFO AcpiDmTableInfoMadt23[] =
{
{ACPI_DMT_UINT8, ACPI_MADT23_OFFSET (Version), "Version", 0},
{ACPI_DMT_UINT64, ACPI_MADT23_OFFSET (Address), "Address", 0},