Default SPI clock speed dropped from SPI_CLOCK_DIV2 to SPI_CLOCK_DIV128, causing intermittent SPI communication issues

[tdicola]

I've been debugging a few recent intermittent lockup issues and found the recent change to add support for the Due (this one f1172f2 ) accidentally dropped the default SPI clock speed from CPU clock speed div 2, to clock speed div 128. This value is likely right on the edge of being too slow to communicate with the CC3000 reliably and explains the intermittent nature of the issue. The fix should be straight forward, for the non-Due platforms set the default SPI clock speed back to div 2. Opening this as an issue first and then sending a pull request with the fix separately.