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PPC building of openjdk could be better optimized for pwr5+ #2560

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andrew-m-leonard opened this issue Apr 9, 2021 · 7 comments
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enhancement Issues that enhance the code or documentation of the repo in any way Reported to OpenJDK / JBS Issues that have been reported upstream to the OpenJDK community

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@andrew-m-leonard
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andrew-m-leonard commented Apr 9, 2021

Current openjdk compiles ppc xlc platforms using:

$1_CFLAGS_CPU_JVM="-qarch=ppc64"

https://github.com/openjdk/jdk/blob/3bb6a3d2ab96373baa4e18f4e61173f11225fd4e/make/autoconf/flags-cflags.m4#L720
better optimization could be achieved using -qarch=pwr5

@andrew-m-leonard andrew-m-leonard added enhancement Issues that enhance the code or documentation of the repo in any way Reported to OpenJDK / JBS Issues that have been reported upstream to the OpenJDK community labels Apr 9, 2021
@aixtools
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aixtools commented Apr 9, 2021

And, I think also adding -qtune=pwr8 (although that is the default behavior on POWER8).

The key item -qarch=XYZ changes is the instruction set availability. -qarch=ppc64 goes back to the very VERY first 64-bit processor (POWER3 iirc).

  • Actually: starting with xlc-13.1.3 the meaning has changed:
    image
  • So, the builds re actually -qarch=pwr4
  • So the question is (imho) -qarch=pwr7 or -qarch=pwr6.
pwr4
Produces object code containing instructions that will run on the POWER4,
POWER5, POWER5+, POWER6®, POWER7®, POWER7+™, POWER8®, or
PowerPC® 970 hardware platforms.
pwr5
Produces object code containing instructions that will run on the POWER5,
POWER5+, POWER6, POWER7, POWER7+, or POWER8 hardware platforms.
pwr5x
Produces object code containing instructions that will run on the POWER5+,
POWER6, POWER7, POWER7+, or POWER8 hardware platforms.
pwr6
Produces object code containing instructions that will run on the POWER6,
POWER7, POWER7+, or POWER8 hardware platforms running in POWER6,
POWER7, POWER7+, or POWER8 architected mode. If you would like support
for decimal floating-point instructions, be sure to specify this suboption during
compilation.
pwr6e
Produces object code containing instructions that will run on the POWER6
hardware platforms running in POWER6 enhanced mode.
pwr7
Produces object code containing instructions that will run on the POWER7,
POWER7+, or POWER8 hardware platforms.
pwr8
Produces object code containing instructions that will run on the POWER8
hardware platforms.
  • xlc-13 does not know about pwr9

@aixtools
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aixtools commented Apr 9, 2021

FYI: POWER Linux LE:

image

@aixtools
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aixtools commented Apr 9, 2021

This is what we need to 'fix': eliminate messages such as:

14:23:16  /home/jenkins/workspace/build-scripts/jobs/jdk/jdk-aix-ppc64-openj9/workspace/build/src/build/aix-ppc64-server-release/vm/runtime/codert_vm/pnathelp.s: line 11609: Instruction lxvd2x is not implemented in the current assembly mode PPC64.
14:23:16  /home/jenkins/workspace/build-scripts/jobs/jdk/jdk-aix-ppc64-openj9/workspace/build/src/build/aix-ppc64-server-release/vm/runtime/codert_vm/pnathelp.s: line 11611: Instruction lxvd2x is not implemented in the current assembly mode PPC64.
14:23:16  /home/jenkins/workspace/build-scripts/jobs/jdk/jdk-aix-ppc64-openj9/workspace/build/src/build/aix-ppc64-server-release/vm/runtime/codert_vm/pnathelp.s: line 11613: Instruction lxvd2x is not implemented in the current assembly mode PPC64.

@M-Davies M-Davies added this to TODO in temurin-build via automation Apr 9, 2021
@sxa
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sxa commented Apr 12, 2021

Are those errors new in the JDK17 builds only? I'd be a little wary of changing things in previous releases in cae people are using our builds on older systems and we introduce customer problems. Can we check which series of processor lxvd2x was introduced in? We don't currently list a minimum supported level for AIX systems on our supported platforms page/

@sxa
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sxa commented Jul 12, 2021

@andrew-m-leonard If this has been reported upstream to we have a bug reference?

@aixtools
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aixtools commented Jan 7, 2022

The assembly language instruction is part of the VSX instructions (a co-processor in the POWER core, iirc).

From: http://cdn.openpowerfoundation.org/wp-content/uploads/resources/openpower-isa-thts-V2-1/content/ch08s01.html

VSX Vector Load Instructions: lxvb16x lxvd2x lxv lxvx lxvh8x lxvw4x

So, the code in runtime/codert_vm/pnathelp.s requires, at a minimum, POWER7.

From the XLC compiler reference (PDF): -qarch description and Usage:

Table 22. Feature support in processor architectures
Architecture Graphics
support
Square root
support
64-bit support Vector
processing
support
Large page
support
pwr4 yes yes yes no yes
pwr5 yes yes yes no yes
pwr5x yes yes yes no yes
ppc yes yes yes no yes
ppc64 yes yes yes no yes
ppc64gr yes yes yes no yes
ppc64grsq yes yes yes no yes
ppc64v yes yes yes VMX yes
ppc970 yes yes yes VMX yes
pwr6 yes yes yes VMX yes
pwr6e yes yes yes VMX yes
pwr7 yes yes yes VMX, VSX yes
pwr8 yes yes yes VMX, VSX yes

As picture (I hope):
image

@aixtools
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aixtools commented Jan 7, 2022

@andrew-m-leonard - perhaps the title should be changed to pwr7 rather than pwr5x (for pwr5+).

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