Fixed incorrect synthesis by arbitrarily removing debug video color

src/fpga/apf/build_id.mif

@@ -9,8 +9,8 @@ DATA_RADIX = HEX;
 CONTENT
 BEGIN
 
-   0E0 : 20220810;
-   0E1 : 00201116;
-   0E2 : 3d85da7e;
+   0E0 : 20220813;
+   0E1 : 00195651;
+   0E2 : fd62f57e;
 
 END;

src/fpga/core/pong/ic/555_timer.vhd

@@ -14,7 +14,7 @@ entity ic555 is
 end entity;
 
 architecture rtl of ic555 is
-  signal counter : unsigned (31 downto 0) := x"00000000";
+  signal counter : unsigned (31 downto 0) := 32b"0";
 
   constant timeout : unsigned (31 downto 0) := to_unsigned(7_159_000 / 1000 * duration_ms, 32);
 begin

src/fpga/core/pong/ic/74153_mux.vhd

@@ -20,7 +20,7 @@ end entity;
 
 architecture rtl of ic74153 is
 begin
-  process (select_a, select_b, not_enable)
+  process (select_a, select_b, not_enable, in_0, in_1, in_2, in_3)
     variable selector : unsigned (1 downto 0);
   begin
     if not_enable = '1' then

src/fpga/core/pong/paddle.vhd

@@ -25,7 +25,7 @@ end entity;
 
 architecture rtl of paddle is
   signal trigger_555 : std_logic;
-  signal count_555 : unsigned (8 downto 0);
+  signal count_555 : unsigned (8 downto 0) := 9b"0";
 
   signal b8_count : unsigned (3 downto 0);
 

src/fpga/core/pong/pong.vhd

@@ -25,7 +25,6 @@ end entity;
 architecture rtl of pong is
   signal h_sync : std_logic;
   signal h_blank : std_logic;
-  signal h_reset : std_logic;
 
   signal v_sync : std_logic;
   signal v_blank : std_logic;
@@ -89,7 +88,6 @@ begin
 
     h_sync => h_sync,
     h_blank => h_blank,
-    h_reset => h_reset,
     h_count => h_count,
     v_sync => v_sync,
     v_blank => v_blank,

src/fpga/core/pong/score/counter.vhd

@@ -85,7 +85,7 @@ begin
   s1_out <= c8a_out & c7_out;
   s2_out <= c8b_out & d7_out;
 
-  process (s1_out, s2_out)
+  process (s1_out, s2_out, score_stop_at_15)
     variable s1_met_score : std_logic;
     variable s2_met_score : std_logic;
   begin

src/fpga/core/pong/test/pong_tb.vhd

@@ -9,7 +9,7 @@ end entity;
 architecture tb of pong_tb is
   signal clk : std_logic := '0';
 
-  constant period : time := 2 ns;
+  constant period : time := 140 ns;
   constant half_period : time := period / 2;
 begin
   UUT : entity work.pong port map (
@@ -25,9 +25,10 @@ begin
 
   process
   begin
-    for i in 0 to 454 * 261 * 100 loop
-      wait for period;
-    end loop;
+    -- for i in 0 to 454 * 261 * 50 loop
+    --   wait for period;
+    -- end loop;
+    wait for 200 ms;
 
     stop;
   end process;

src/fpga/core/pong/video/video.vhd

@@ -16,7 +16,6 @@ entity video is
 
     h_sync : out std_logic;
     h_blank : out std_logic;
-    h_reset : out std_logic;
 
     v_sync : out std_logic;
     v_blank : out std_logic;
@@ -36,7 +35,7 @@ end entity;
 architecture rtl of video is
   signal h_count_int : unsigned (8 downto 0);
   signal h_blank_int : std_logic;
-  signal h_reset_int : std_logic;
+  signal h_reset : std_logic;
 
   signal v_count_int : unsigned (8 downto 0);
   signal v_blank_int : std_logic;
@@ -48,13 +47,13 @@ architecture rtl of video is
   signal combined_ball_g1b_out : std_logic;
 
   -- Generated video
-  signal combined_sync : std_logic;
+  -- signal combined_sync : std_logic;
   signal combined_pads_net_ball : std_logic;
 
   signal video : unsigned (7 downto 0);
 begin
-  HCOUNTER : entity work.hcounter port map (clk_7_159 => clk_7_159, h_reset => h_reset_int, h_count => h_count_int);
-  VCOUNTER : entity work.vcounter port map (h_reset_clk => h_reset_int, v_reset => v_reset_int, v_count => v_count_int);
+  HCOUNTER : entity work.hcounter port map (clk_7_159 => clk_7_159, h_reset => h_reset, h_count => h_count_int);
+  VCOUNTER : entity work.vcounter port map (h_reset_clk => h_reset, v_reset => v_reset_int, v_count => v_count_int);
 
   HSYNC : entity work.hsync port map (
     clk_7_159 => clk_7_159,
@@ -63,7 +62,7 @@ begin
     h32 => h_count_int(5),
     h64 => h_count_int(6),
 
-    h_reset => h_reset_int,
+    h_reset => h_reset,
     h_blank => h_blank_int,
     h_sync => h_sync
     );
@@ -106,23 +105,19 @@ begin
 
   h_blank <= h_blank_int;
   h_count <= h_count_int;
-  h_reset <= h_reset_int;
   v_blank <= v_blank_int;
   v_count <= v_count_int;
   v_reset <= v_reset_int;
 
   process (h_blank_int, v_blank_int, combined_pads_net_ball, score_video)
   begin
-    if h_blank_int = '1' or v_blank_int = '1' then
-      video <= x"00";
-    elsif score_video = '1' then
+    video <= x"00";
+    if score_video = '1' then
       -- TODO: Find right color
       video <= x"BB";
     elsif combined_pads_net_ball = '1' then
       -- TODO: Find right color
       video <= x"FF";
-    else
-      video <= x"55";
     end if;
   end process;
 end architecture;