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Fixing the connection between IQ and ASG #1

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ahesse93 opened this issue Jan 16, 2019 · 3 comments
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Fixing the connection between IQ and ASG #1

ahesse93 opened this issue Jan 16, 2019 · 3 comments
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ahesse93 commented Jan 16, 2019 •
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When the oscillation outputted by the IQ module outputs negative values (= every half cycle) the output of ASG 0 looks really crappy, and absolutely not what it is supposed to look like
Seems to be an error in the signed addition / the conversion of the output of the IQ module
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ahesse93 commented Jan 16, 2019 •
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The problem seems to be somewhere in the signed addition of the modulation from the IQ module and the constant phase step that's taken at each clock cycle

@ahesse93 ahesse93 self-assigned this Jan 16, 2019
@ahesse93 ahesse93 added the bug Something isn't working label Jan 16, 2019
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It looks like an additional 180° are added every clock cycle if the output of the IQ module is negative...

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The issue was in the padding of phase_mod in the ASG module - now everything should work

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