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About axil-interconnect #26
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And, in this code below, I see when arvalid is received, s_axil_arready is set to 1. Did you verify whether the slave was idle during this process? What happens if the slave is not free? |
In AXI and AXI lite, if you start a write operation by setting For the second question, it doesn't matter if the slave is idle or not, the interconnect accepts the address, decodes it, and then presents it to the slave, then waits for the slave to accept it. The ready signal question is going to the upstream master that's issuing the request. |
Just to make sure, Should I connect a ram (also from axi_ram.v in your repo) to the axi_interconnect's slave port or master port? My understanding is that I should connect axi_ram to the axi_interconnect's master interface, since the interconnect acts as the master and the ram acts as the slave? and the signals slave and master ports in the axi_connect should be identical? In the current implementation they are different, for example, the awregion, arregion presented in the master but not missed from the slave port. |
Yes, that is correct - connect the RAM (which is an AXI slave) to a master interface on the interconnect. The awregion/arregion signals are used to address multiple regions within the same slave so that the slave doesn't need to do a second round of address decoding, it can simply use the region indication from the interconnect. Currently, I don't have any devices that take advantage of that feature, but it is part of the AXI spec. |
Hello sir, Thank you :) |
Nvm, #16 answered my questions. |
Hi sir,
In axi lite interconnect, if a write operation is performed first and awvalid and awready shake hands already, but the write operation is not required , I want to start a read operation. Will the write operation be invalid and the read operation be performed?
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