Minor nits. Default state in mdio state case

[secworks]

Running the VCU118 10G example design with Vivado and linter. One nits highlighted is the case statement implementing the mdio command FSM engine starting at 1043 in fpga.v. That case statement end with:

            4'd12: begin
                // done
                state_reg <= 4'd12;
            end
        endcase

Which of course ensure that it stops when done. But since the state space is incomplete the toots gets annoyed. How abot simply adding a

default:
state_reg <= 4d0;