-
Notifications
You must be signed in to change notification settings - Fork 29
/
wb_arbiter.py
executable file
·184 lines (147 loc) · 5.95 KB
/
wb_arbiter.py
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
#!/usr/bin/env python
"""
Generates a Wishbone arbiter with the specified number of ports
"""
from __future__ import print_function
import argparse
import math
from jinja2 import Template
def main():
parser = argparse.ArgumentParser(description=__doc__.strip())
parser.add_argument('-p', '--ports', type=int, default=2, help="number of ports")
parser.add_argument('-n', '--name', type=str, help="module name")
parser.add_argument('-o', '--output', type=str, help="output file name")
args = parser.parse_args()
try:
generate(**args.__dict__)
except IOError as ex:
print(ex)
exit(1)
def generate(ports=2, name=None, output=None):
if name is None:
name = "wb_arbiter_{0}".format(ports)
if output is None:
output = name + ".v"
print("Opening file '{0}'...".format(output))
output_file = open(output, 'w')
print("Generating {0} port Wishbone arbiter {1}...".format(ports, name))
select_width = int(math.ceil(math.log(ports, 2)))
t = Template(u"""/*
Copyright (c) 2015-2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
/*
* Wishbone {{n}} port arbiter
*/
module {{name}} #
(
parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
parameter ADDR_WIDTH = 32, // width of address bus in bits
parameter SELECT_WIDTH = (DATA_WIDTH/8), // width of word select bus (1, 2, 4, or 8)
parameter ARB_TYPE_ROUND_ROBIN = 0, // select round robin arbitration
parameter ARB_LSB_HIGH_PRIORITY = 1 // LSB priority selection
)
(
input wire clk,
input wire rst,
{%- for p in ports %}
/*
* Wishbone master {{p}} input
*/
input wire [ADDR_WIDTH-1:0] wbm{{p}}_adr_i, // ADR_I() address input
input wire [DATA_WIDTH-1:0] wbm{{p}}_dat_i, // DAT_I() data in
output wire [DATA_WIDTH-1:0] wbm{{p}}_dat_o, // DAT_O() data out
input wire wbm{{p}}_we_i, // WE_I write enable input
input wire [SELECT_WIDTH-1:0] wbm{{p}}_sel_i, // SEL_I() select input
input wire wbm{{p}}_stb_i, // STB_I strobe input
output wire wbm{{p}}_ack_o, // ACK_O acknowledge output
output wire wbm{{p}}_err_o, // ERR_O error output
output wire wbm{{p}}_rty_o, // RTY_O retry output
input wire wbm{{p}}_cyc_i, // CYC_I cycle input
{%- endfor %}
/*
* Wishbone slave output
*/
output wire [ADDR_WIDTH-1:0] wbs_adr_o, // ADR_O() address output
input wire [DATA_WIDTH-1:0] wbs_dat_i, // DAT_I() data in
output wire [DATA_WIDTH-1:0] wbs_dat_o, // DAT_O() data out
output wire wbs_we_o, // WE_O write enable output
output wire [SELECT_WIDTH-1:0] wbs_sel_o, // SEL_O() select output
output wire wbs_stb_o, // STB_O strobe output
input wire wbs_ack_i, // ACK_I acknowledge input
input wire wbs_err_i, // ERR_I error input
input wire wbs_rty_i, // RTY_I retry input
output wire wbs_cyc_o // CYC_O cycle output
);
wire [{{n-1}}:0] request;
wire [{{n-1}}:0] grant;
{% for p in ports %}
assign request[{{p}}] = wbm{{p}}_cyc_i;
{%- endfor %}
{% for p in ports %}
wire wbm{{p}}_sel = grant[{{p}}] & grant_valid;
{%- endfor %}
{%- for p in ports %}
// master {{p}}
assign wbm{{p}}_dat_o = wbs_dat_i;
assign wbm{{p}}_ack_o = wbs_ack_i & wbm{{p}}_sel;
assign wbm{{p}}_err_o = wbs_err_i & wbm{{p}}_sel;
assign wbm{{p}}_rty_o = wbs_rty_i & wbm{{p}}_sel;
{%- endfor %}
// slave
assign wbs_adr_o = {% for p in ports %}wbm{{p}}_sel ? wbm{{p}}_adr_i :
{% endfor %}{ADDR_WIDTH{1'b0}};
assign wbs_dat_o = {% for p in ports %}wbm{{p}}_sel ? wbm{{p}}_dat_i :
{% endfor %}{DATA_WIDTH{1'b0}};
assign wbs_we_o = {% for p in ports %}wbm{{p}}_sel ? wbm{{p}}_we_i :
{% endfor %}1'b0;
assign wbs_sel_o = {% for p in ports %}wbm{{p}}_sel ? wbm{{p}}_sel_i :
{% endfor %}{SELECT_WIDTH{1'b0}};
assign wbs_stb_o = {% for p in ports %}wbm{{p}}_sel ? wbm{{p}}_stb_i :
{% endfor %}1'b0;
assign wbs_cyc_o = {% for p in ports %}wbm{{p}}_sel ? 1'b1 :
{% endfor %}1'b0;
// arbiter instance
arbiter #(
.PORTS({{n}}),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_BLOCK(1),
.ARB_BLOCK_ACK(0),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
arb_inst (
.clk(clk),
.rst(rst),
.request(request),
.acknowledge(),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded()
);
endmodule
""")
output_file.write(t.render(
n=ports,
w=select_width,
name=name,
ports=range(ports)
))
print("Done")
if __name__ == "__main__":
main()