ucevent CBO.LLC_{DDIO,PCIE}_* events for HSX

[tootoonchian]

Haswell Xeon CBO.LLC_{DDIO,PCIE}_* events are missing. Any plans to add them in the near future?

[andikleen]

You can in theory copy jkt_extra.py to hsx_extra.py to enable those.
Let me know if it works.

[tootoonchian]

I don't think it is working correctly and I couldn't find Haswell uncore manual to verify if anything has changed.

CBO.LLC_DDIO_MEM_READ_BYTES and CBO.LLC_PCIE_MEM_READ_BYTES seem to always report 0 on Haswell but report correctly on Ivy Bridge. I cannot trust the write numbers either (running and comparing the same workload on Ivy Bridge).

On Haswell:

CBO.LLC_DDIO_MEM_WRITE_BYTES
|            CBO.LLC_DDIO_MEM_READ_BYTES
|            |    CBO.LLC_PCIE_MEM_WRITE_BYTES
|            |    |              CBO.LLC_PCIE_MEM_READ_BYTES
1,592,320.00 0.00 410,446,592.00 0.00  
1,593,088.00 0.00 410,517,248.00 0.00  

On Ivy Bridge:

CBO.LLC_DDIO_MEM_WRITE_BYTES
|            CBO.LLC_DDIO_MEM_READ_BYTES
|            |      CBO.LLC_PCIE_MEM_WRITE_BYTES
|            |      |                CBO.LLC_PCIE_MEM_READ_BYTES
17,408.00    0.00   5,046,370,432.00 3,571,441,472.00 
16,896.00    0.00   5,046,201,536.00 3,571,521,088.00 

[andikleen]

The manual is here:

http://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v3-uncore-performance-monitoring.html

[tootoonchian]

Thanks for the link. Just took a quick look at the manual. There doesn't seem to be any changes.

[andikleen]

Unlikely to fix anything for Haswell anymore at this point.