Questions about mmx registers mm0-mm7

[YHZX2013]

I feel confused about reg(mm0-mm7) with index:

'mm0': (72, 8),
'mm1': (73, 8),
…………
'mm7': (79, 8)

Such as disasm:

movq mm0, qword ptr [ebp - 8]

Got Vex IR:

…………
09 | PutI(136:I8x8)[0x00000000,7] = 0x01
10 | t2 = GET:I32(ebp)
11 | t1 = Add32(t2,0xfffffff8)
12 | t3 = LDle:I64(t1)
13 | PUT(mm0) = t3

Will this overwrite mm1's first 7 bytes？
So why not be 'mm0': (72, 8), 'mm1': (80, 8) like xmm0-xmm7?

Thanks a lot!

[rhelmot]

Interesting. This is a bug in the register offset descriptions in archinfo, which are not consulted during the lifting process since that happens purely in libvex.

It looks like this was originally the fault of a bug in the script to autogenerate those offsets. I will fix it shortly.