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libvex_ir.h
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libvex_ir.h
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/*---------------------------------------------------------------*/
/*--- begin libvex_ir.h ---*/
/*---------------------------------------------------------------*/
/*
This file is part of Valgrind, a dynamic binary instrumentation
framework.
Copyright (C) 2004-2015 OpenWorks LLP
info@open-works.net
This program is free software; you can redistribute it and/or
modify it under the terms of the GNU General Public License as
published by the Free Software Foundation; either version 2 of the
License, or (at your option) any later version.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
02110-1301, USA.
The GNU General Public License is contained in the file COPYING.
Neither the names of the U.S. Department of Energy nor the
University of California nor the names of its contributors may be
used to endorse or promote products derived from this software
without prior written permission.
*/
#ifndef __LIBVEX_IR_H
#define __LIBVEX_IR_H
#include "libvex_basictypes.h"
/*---------------------------------------------------------------*/
/*--- High-level IR description ---*/
/*---------------------------------------------------------------*/
/* Vex IR is an architecture-neutral intermediate representation.
Unlike some IRs in systems similar to Vex, it is not like assembly
language (ie. a list of instructions). Rather, it is more like the
IR that might be used in a compiler.
Code blocks
~~~~~~~~~~~
The code is broken into small code blocks ("superblocks", type:
'IRSB'). Each code block typically represents from 1 to perhaps 50
instructions. IRSBs are single-entry, multiple-exit code blocks.
Each IRSB contains three things:
- a type environment, which indicates the type of each temporary
value present in the IRSB
- a list of statements, which represent code
- a jump that exits from the end the IRSB
Because the blocks are multiple-exit, there can be additional
conditional exit statements that cause control to leave the IRSB
before the final exit. Also because of this, IRSBs can cover
multiple non-consecutive sequences of code (up to 3). These are
recorded in the type VexGuestExtents (see libvex.h).
Statements and expressions
~~~~~~~~~~~~~~~~~~~~~~~~~~
Statements (type 'IRStmt') represent operations with side-effects,
eg. guest register writes, stores, and assignments to temporaries.
Expressions (type 'IRExpr') represent operations without
side-effects, eg. arithmetic operations, loads, constants.
Expressions can contain sub-expressions, forming expression trees,
eg. (3 + (4 * load(addr1)).
Storage of guest state
~~~~~~~~~~~~~~~~~~~~~~
The "guest state" contains the guest registers of the guest machine
(ie. the machine that we are simulating). It is stored by default
in a block of memory supplied by the user of the VEX library,
generally referred to as the guest state (area). To operate on
these registers, one must first read ("Get") them from the guest
state into a temporary value. Afterwards, one can write ("Put")
them back into the guest state.
Get and Put are characterised by a byte offset into the guest
state, a small integer which effectively gives the identity of the
referenced guest register, and a type, which indicates the size of
the value to be transferred.
The basic "Get" and "Put" operations are sufficient to model normal
fixed registers on the guest. Selected areas of the guest state
can be treated as a circular array of registers (type:
'IRRegArray'), which can be indexed at run-time. This is done with
the "GetI" and "PutI" primitives. This is necessary to describe
rotating register files, for example the x87 FPU stack, SPARC
register windows, and the Itanium register files.
Examples, and flattened vs. unflattened code
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
For example, consider this x86 instruction:
addl %eax, %ebx
One Vex IR translation for this code would be this:
------ IMark(0x24F275, 7, 0) ------
t3 = GET:I32(0) # get %eax, a 32-bit integer
t2 = GET:I32(12) # get %ebx, a 32-bit integer
t1 = Add32(t3,t2) # addl
PUT(0) = t1 # put %eax
(For simplicity, this ignores the effects on the condition codes, and
the update of the instruction pointer.)
The "IMark" is an IR statement that doesn't represent actual code.
Instead it indicates the address and length of the original
instruction. The numbers 0 and 12 are offsets into the guest state
for %eax and %ebx. The full list of offsets for an architecture
<ARCH> can be found in the type VexGuest<ARCH>State in the file
VEX/pub/libvex_guest_<ARCH>.h.
The five statements in this example are:
- the IMark
- three assignments to temporaries
- one register write (put)
The six expressions in this example are:
- two register reads (gets)
- one arithmetic (add) operation
- three temporaries (two nested within the Add32, one in the PUT)
The above IR is "flattened", ie. all sub-expressions are "atoms",
either constants or temporaries. An equivalent, unflattened version
would be:
PUT(0) = Add32(GET:I32(0), GET:I32(12))
IR is guaranteed to be flattened at instrumentation-time. This makes
instrumentation easier. Equivalent flattened and unflattened IR
typically results in the same generated code.
Another example, this one showing loads and stores:
addl %edx,4(%eax)
This becomes (again ignoring condition code and instruction pointer
updates):
------ IMark(0x4000ABA, 3, 0) ------
t3 = Add32(GET:I32(0),0x4:I32)
t2 = LDle:I32(t3)
t1 = GET:I32(8)
t0 = Add32(t2,t1)
STle(t3) = t0
The "le" in "LDle" and "STle" is short for "little-endian".
No need for deallocations
~~~~~~~~~~~~~~~~~~~~~~~~~
Although there are allocation functions for various data structures
in this file, there are no deallocation functions. This is because
Vex uses a memory allocation scheme that automatically reclaims the
memory used by allocated structures once translation is completed.
This makes things easier for tools that instruments/transforms code
blocks.
SSAness and typing
~~~~~~~~~~~~~~~~~~
The IR is fully typed. For every IRSB (IR block) it is possible to
say unambiguously whether or not it is correctly typed.
Incorrectly typed IR has no meaning and the VEX will refuse to
process it. At various points during processing VEX typechecks the
IR and aborts if any violations are found. This seems overkill but
makes it a great deal easier to build a reliable JIT.
IR also has the SSA property. SSA stands for Static Single
Assignment, and what it means is that each IR temporary may be
assigned to only once. This idea became widely used in compiler
construction in the mid to late 90s. It makes many IR-level
transformations/code improvements easier, simpler and faster.
Whenever it typechecks an IR block, VEX also checks the SSA
property holds, and will abort if not so. So SSAness is
mechanically and rigidly enforced.
*/
/*---------------------------------------------------------------*/
/*--- Type definitions for the IR ---*/
/*---------------------------------------------------------------*/
/* General comments about naming schemes:
All publically visible functions contain the name of the primary
type on which they operate (IRFoo, IRBar, etc). Hence you should
be able to identify these functions by grepping for "IR[A-Z]".
For some type 'IRFoo':
- ppIRFoo is the printing method for IRFoo, printing it to the
output channel specified in the LibVEX_Initialise call.
- eqIRFoo is a structural equality predicate for IRFoos.
- deepCopyIRFoo is a deep copy constructor for IRFoos.
It recursively traverses the entire argument tree and
produces a complete new tree. All types have a deep copy
constructor.
- shallowCopyIRFoo is the shallow copy constructor for IRFoos.
It creates a new top-level copy of the supplied object,
but does not copy any sub-objects. Only some types have a
shallow copy constructor.
*/
/* ------------------ Types ------------------ */
/* A type indicates the size of a value, and whether it's an integer, a
float, or a vector (SIMD) value. */
typedef
enum {
Ity_INVALID=0x1100,
Ity_I1,
Ity_I8,
Ity_I16,
Ity_I32,
Ity_I64,
Ity_I128, /* 128-bit scalar */
Ity_F16, /* 16 bit float */
Ity_F32, /* IEEE 754 float */
Ity_F64, /* IEEE 754 double */
Ity_D32, /* 32-bit Decimal floating point */
Ity_D64, /* 64-bit Decimal floating point */
Ity_D128, /* 128-bit Decimal floating point */
Ity_F128, /* 128-bit floating point; implementation defined */
Ity_V128, /* 128-bit SIMD */
Ity_V256 /* 256-bit SIMD */
}
IRType;
/* Pretty-print an IRType */
extern void ppIRType ( IRType );
/* Get the size (in bytes) of an IRType */
extern Int sizeofIRType ( IRType );
/* Translate 1/2/4/8 into Ity_I{8,16,32,64} respectively. Asserts on
any other input. */
extern IRType integerIRTypeOfSize ( Int szB );
/* ------------------ Endianness ------------------ */
/* IREndness is used in load IRExprs and store IRStmts. */
typedef
enum {
Iend_LE=0x1200, /* little endian */
Iend_BE /* big endian */
}
IREndness;
/* ------------------ Constants ------------------ */
/* IRConsts are used within 'Const' and 'Exit' IRExprs. */
/* The various kinds of constant. */
typedef
enum {
Ico_U1=0x1300,
Ico_U8,
Ico_U16,
Ico_U32,
Ico_U64,
Ico_F32, /* 32-bit IEEE754 floating */
Ico_F32i, /* 32-bit unsigned int to be interpreted literally
as a IEEE754 single value. */
Ico_F64, /* 64-bit IEEE754 floating */
Ico_F64i, /* 64-bit unsigned int to be interpreted literally
as a IEEE754 double value. */
Ico_V128, /* 128-bit restricted vector constant, with 1 bit
(repeated 8 times) for each of the 16 x 1-byte lanes */
Ico_V256 /* 256-bit restricted vector constant, with 1 bit
(repeated 8 times) for each of the 32 x 1-byte lanes */
}
IRConstTag;
/* A constant. Stored as a tagged union. 'tag' indicates what kind of
constant this is. 'Ico' is the union that holds the fields. If an
IRConst 'c' has c.tag equal to Ico_U32, then it's a 32-bit constant,
and its value can be accessed with 'c.Ico.U32'. */
typedef
struct _IRConst {
IRConstTag tag;
union {
Bool U1;
UChar U8;
UShort U16;
UInt U32;
ULong U64;
Float F32;
UInt F32i;
Double F64;
ULong F64i;
UShort V128; /* 16-bit value; see Ico_V128 comment above */
UInt V256; /* 32-bit value; see Ico_V256 comment above */
} Ico;
}
IRConst;
/* IRConst constructors */
extern IRConst* IRConst_U1 ( Bool );
extern IRConst* IRConst_U8 ( UChar );
extern IRConst* IRConst_U16 ( UShort );
extern IRConst* IRConst_U32 ( UInt );
extern IRConst* IRConst_U64 ( ULong );
extern IRConst* IRConst_F32 ( Float );
extern IRConst* IRConst_F32i ( UInt );
extern IRConst* IRConst_F64 ( Double );
extern IRConst* IRConst_F64i ( ULong );
extern IRConst* IRConst_V128 ( UShort );
extern IRConst* IRConst_V256 ( UInt );
/* Deep-copy an IRConst */
extern IRConst* deepCopyIRConst ( const IRConst* );
/* Pretty-print an IRConst */
extern void ppIRConst ( const IRConst* );
/* Compare two IRConsts for equality */
extern Bool eqIRConst ( const IRConst*, const IRConst* );
/* ------------------ Call targets ------------------ */
/* Describes a helper function to call. The name part is purely for
pretty printing and not actually used. regparms=n tells the back
end that the callee has been declared
"__attribute__((regparm(n)))", although indirectly using the
VEX_REGPARM(n) macro. On some targets (x86) the back end will need
to construct a non-standard sequence to call a function declared
like this.
mcx_mask is a sop to Memcheck. It indicates which args should be
considered 'always defined' when lazily computing definedness of
the result. Bit 0 of mcx_mask corresponds to args[0], bit 1 to
args[1], etc. If a bit is set, the corresponding arg is excluded
(hence "x" in "mcx") from definedness checking.
*/
typedef
struct {
Int regparms;
const HChar* name;
void* addr;
UInt mcx_mask;
}
IRCallee;
/* Create an IRCallee. */
extern IRCallee* mkIRCallee ( Int regparms, const HChar* name, void* addr );
/* Deep-copy an IRCallee. */
extern IRCallee* deepCopyIRCallee ( const IRCallee* );
/* Pretty-print an IRCallee. */
extern void ppIRCallee ( const IRCallee* );
/* ------------------ Guest state arrays ------------------ */
/* This describes a section of the guest state that we want to
be able to index at run time, so as to be able to describe
indexed or rotating register files on the guest. */
typedef
struct {
Int base; /* guest state offset of start of indexed area */
IRType elemTy; /* type of each element in the indexed area */
Int nElems; /* number of elements in the indexed area */
}
IRRegArray;
extern IRRegArray* mkIRRegArray ( Int, IRType, Int );
extern IRRegArray* deepCopyIRRegArray ( const IRRegArray* );
extern void ppIRRegArray ( const IRRegArray* );
extern Bool eqIRRegArray ( const IRRegArray*, const IRRegArray* );
/* ------------------ Temporaries ------------------ */
/* This represents a temporary, eg. t1. The IR optimiser relies on the
fact that IRTemps are 32-bit ints. Do not change them to be ints of
any other size. */
typedef UInt IRTemp;
/* Pretty-print an IRTemp. */
extern void ppIRTemp ( IRTemp );
#define IRTemp_INVALID ((IRTemp)0xFFFFFFFF)
/* --------------- Primops (arity 1,2,3 and 4) --------------- */
/* Primitive operations that are used in Unop, Binop, Triop and Qop
IRExprs. Once we take into account integer, floating point and SIMD
operations of all the different sizes, there are quite a lot of them.
Most instructions supported by the architectures that Vex supports
(x86, PPC, etc) are represented. Some more obscure ones (eg. cpuid)
are not; they are instead handled with dirty helpers that emulate
their functionality. Such obscure ones are thus not directly visible
in the IR, but their effects on guest state (memory and registers)
are made visible via the annotations in IRDirty structures.
*/
typedef
enum {
/* -- Do not change this ordering. The IR generators rely on
(eg) Iop_Add64 == IopAdd8 + 3. -- */
Iop_INVALID=0x1400,
Iop_Add8, Iop_Add16, Iop_Add32, Iop_Add64,
Iop_Sub8, Iop_Sub16, Iop_Sub32, Iop_Sub64,
/* Signless mul. MullS/MullU is elsewhere. */
Iop_Mul8, Iop_Mul16, Iop_Mul32, Iop_Mul64,
Iop_Or8, Iop_Or16, Iop_Or32, Iop_Or64,
Iop_And8, Iop_And16, Iop_And32, Iop_And64,
Iop_Xor8, Iop_Xor16, Iop_Xor32, Iop_Xor64,
Iop_Shl8, Iop_Shl16, Iop_Shl32, Iop_Shl64,
Iop_Shr8, Iop_Shr16, Iop_Shr32, Iop_Shr64,
Iop_Sar8, Iop_Sar16, Iop_Sar32, Iop_Sar64,
/* Integer comparisons. */
Iop_CmpEQ8, Iop_CmpEQ16, Iop_CmpEQ32, Iop_CmpEQ64,
Iop_CmpNE8, Iop_CmpNE16, Iop_CmpNE32, Iop_CmpNE64,
/* Tags for unary ops */
Iop_Not8, Iop_Not16, Iop_Not32, Iop_Not64,
/* Exactly like CmpEQ8/16/32/64, but carrying the additional
hint that these compute the success/failure of a CAS
operation, and hence are almost certainly applied to two
copies of the same value, which in turn has implications for
Memcheck's instrumentation. */
Iop_CasCmpEQ8, Iop_CasCmpEQ16, Iop_CasCmpEQ32, Iop_CasCmpEQ64,
Iop_CasCmpNE8, Iop_CasCmpNE16, Iop_CasCmpNE32, Iop_CasCmpNE64,
/* Exactly like CmpNE8/16/32/64, but carrying the additional
hint that these needs expensive definedness tracking. */
Iop_ExpCmpNE8, Iop_ExpCmpNE16, Iop_ExpCmpNE32, Iop_ExpCmpNE64,
/* -- Ordering not important after here. -- */
/* Widening multiplies */
Iop_MullS8, Iop_MullS16, Iop_MullS32, Iop_MullS64,
Iop_MullU8, Iop_MullU16, Iop_MullU32, Iop_MullU64,
/* Wierdo integer stuff */
Iop_Clz64, Iop_Clz32, /* count leading zeroes */
Iop_Ctz64, Iop_Ctz32, /* count trailing zeros */
/* Ctz64/Ctz32/Clz64/Clz32 are UNDEFINED when given arguments of
zero. You must ensure they are never given a zero argument.
*/
/* Standard integer comparisons */
Iop_CmpLT32S, Iop_CmpLT64S,
Iop_CmpLE32S, Iop_CmpLE64S,
Iop_CmpLT32U, Iop_CmpLT64U,
Iop_CmpLE32U, Iop_CmpLE64U,
/* As a sop to Valgrind-Memcheck, the following are useful. */
Iop_CmpNEZ8, Iop_CmpNEZ16, Iop_CmpNEZ32, Iop_CmpNEZ64,
Iop_CmpwNEZ32, Iop_CmpwNEZ64, /* all-0s -> all-Os; other -> all-1s */
Iop_Left8, Iop_Left16, Iop_Left32, Iop_Left64, /* \x -> x | -x */
Iop_Max32U, /* unsigned max */
/* PowerPC-style 3-way integer comparisons. Without them it is
difficult to simulate PPC efficiently.
op(x,y) | x < y = 0x8 else
| x > y = 0x4 else
| x == y = 0x2
*/
Iop_CmpORD32U, Iop_CmpORD64U,
Iop_CmpORD32S, Iop_CmpORD64S,
/* Division */
/* TODO: clarify semantics wrt rounding, negative values, whatever */
Iop_DivU32, // :: I32,I32 -> I32 (simple div, no mod)
Iop_DivS32, // ditto, signed
Iop_DivU64, // :: I64,I64 -> I64 (simple div, no mod)
Iop_DivS64, // ditto, signed
Iop_DivU64E, // :: I64,I64 -> I64 (dividend is 64-bit arg (hi)
// concat with 64 0's (low))
Iop_DivS64E, // ditto, signed
Iop_DivU32E, // :: I32,I32 -> I32 (dividend is 32-bit arg (hi)
// concat with 32 0's (low))
Iop_DivS32E, // ditto, signed
Iop_DivModU64to32, // :: I64,I32 -> I64
// of which lo half is div and hi half is mod
Iop_DivModS64to32, // ditto, signed
Iop_DivModU128to64, // :: V128,I64 -> V128
// of which lo half is div and hi half is mod
Iop_DivModS128to64, // ditto, signed
Iop_DivModS64to64, // :: I64,I64 -> I128
// of which lo half is div and hi half is mod
/* Integer conversions. Some of these are redundant (eg
Iop_64to8 is the same as Iop_64to32 and then Iop_32to8), but
having a complete set reduces the typical dynamic size of IR
and makes the instruction selectors easier to write. */
/* Widening conversions */
Iop_8Uto16, Iop_8Uto32, Iop_8Uto64,
Iop_16Uto32, Iop_16Uto64,
Iop_32Uto64,
Iop_8Sto16, Iop_8Sto32, Iop_8Sto64,
Iop_16Sto32, Iop_16Sto64,
Iop_32Sto64,
/* Narrowing conversions */
Iop_64to8, Iop_32to8, Iop_64to16,
/* 8 <-> 16 bit conversions */
Iop_16to8, // :: I16 -> I8, low half
Iop_16HIto8, // :: I16 -> I8, high half
Iop_8HLto16, // :: (I8,I8) -> I16
/* 16 <-> 32 bit conversions */
Iop_32to16, // :: I32 -> I16, low half
Iop_32HIto16, // :: I32 -> I16, high half
Iop_16HLto32, // :: (I16,I16) -> I32
/* 32 <-> 64 bit conversions */
Iop_64to32, // :: I64 -> I32, low half
Iop_64HIto32, // :: I64 -> I32, high half
Iop_32HLto64, // :: (I32,I32) -> I64
/* 64 <-> 128 bit conversions */
Iop_128to64, // :: I128 -> I64, low half
Iop_128HIto64, // :: I128 -> I64, high half
Iop_64HLto128, // :: (I64,I64) -> I128
/* 1-bit stuff */
Iop_Not1, /* :: Ity_Bit -> Ity_Bit */
Iop_32to1, /* :: Ity_I32 -> Ity_Bit, just select bit[0] */
Iop_64to1, /* :: Ity_I64 -> Ity_Bit, just select bit[0] */
Iop_1Uto8, /* :: Ity_Bit -> Ity_I8, unsigned widen */
Iop_1Uto32, /* :: Ity_Bit -> Ity_I32, unsigned widen */
Iop_1Uto64, /* :: Ity_Bit -> Ity_I64, unsigned widen */
Iop_1Sto8, /* :: Ity_Bit -> Ity_I8, signed widen */
Iop_1Sto16, /* :: Ity_Bit -> Ity_I16, signed widen */
Iop_1Sto32, /* :: Ity_Bit -> Ity_I32, signed widen */
Iop_1Sto64, /* :: Ity_Bit -> Ity_I64, signed widen */
/* ------ Floating point. We try to be IEEE754 compliant. ------ */
/* --- Simple stuff as mandated by 754. --- */
/* Binary operations, with rounding. */
/* :: IRRoundingMode(I32) x F64 x F64 -> F64 */
Iop_AddF64, Iop_SubF64, Iop_MulF64, Iop_DivF64,
/* :: IRRoundingMode(I32) x F32 x F32 -> F32 */
Iop_AddF32, Iop_SubF32, Iop_MulF32, Iop_DivF32,
/* Variants of the above which produce a 64-bit result but which
round their result to a IEEE float range first. */
/* :: IRRoundingMode(I32) x F64 x F64 -> F64 */
Iop_AddF64r32, Iop_SubF64r32, Iop_MulF64r32, Iop_DivF64r32,
/* Unary operations, without rounding. */
/* :: F64 -> F64 */
Iop_NegF64, Iop_AbsF64,
/* :: F32 -> F32 */
Iop_NegF32, Iop_AbsF32,
/* Unary operations, with rounding. */
/* :: IRRoundingMode(I32) x F64 -> F64 */
Iop_SqrtF64,
/* :: IRRoundingMode(I32) x F32 -> F32 */
Iop_SqrtF32,
/* Comparison, yielding GT/LT/EQ/UN(ordered), as per the following:
0x45 Unordered
0x01 LT
0x00 GT
0x40 EQ
This just happens to be the Intel encoding. The values
are recorded in the type IRCmpF64Result.
*/
/* :: F64 x F64 -> IRCmpF64Result(I32) */
Iop_CmpF64,
Iop_CmpF32,
Iop_CmpF128,
/* --- Int to/from FP conversions. --- */
/* For the most part, these take a first argument :: Ity_I32 (as
IRRoundingMode) which is an indication of the rounding mode
to use, as per the following encoding ("the standard
encoding"):
00b to nearest (the default)
01b to -infinity
10b to +infinity
11b to zero
This just happens to be the Intel encoding. For reference only,
the PPC encoding is:
00b to nearest (the default)
01b to zero
10b to +infinity
11b to -infinity
Any PPC -> IR front end will have to translate these PPC
encodings, as encoded in the guest state, to the standard
encodings, to pass to the primops.
For reference only, the ARM VFP encoding is:
00b to nearest
01b to +infinity
10b to -infinity
11b to zero
Again, this will have to be converted to the standard encoding
to pass to primops.
If one of these conversions gets an out-of-range condition,
or a NaN, as an argument, the result is host-defined. On x86
the "integer indefinite" value 0x80..00 is produced. On PPC
it is either 0x80..00 or 0x7F..FF depending on the sign of
the argument.
On ARMvfp, when converting to a signed integer result, the
overflow result is 0x80..00 for negative args and 0x7F..FF
for positive args. For unsigned integer results it is
0x00..00 and 0xFF..FF respectively.
Rounding is required whenever the destination type cannot
represent exactly all values of the source type.
*/
Iop_F64toI16S, /* IRRoundingMode(I32) x F64 -> signed I16 */
Iop_F64toI32S, /* IRRoundingMode(I32) x F64 -> signed I32 */
Iop_F64toI64S, /* IRRoundingMode(I32) x F64 -> signed I64 */
Iop_F64toI64U, /* IRRoundingMode(I32) x F64 -> unsigned I64 */
Iop_F64toI32U, /* IRRoundingMode(I32) x F64 -> unsigned I32 */
Iop_I32StoF64, /* signed I32 -> F64 */
Iop_I64StoF64, /* IRRoundingMode(I32) x signed I64 -> F64 */
Iop_I64UtoF64, /* IRRoundingMode(I32) x unsigned I64 -> F64 */
Iop_I64UtoF32, /* IRRoundingMode(I32) x unsigned I64 -> F32 */
Iop_I32UtoF32, /* IRRoundingMode(I32) x unsigned I32 -> F32 */
Iop_I32UtoF64, /* unsigned I32 -> F64 */
Iop_F32toI32S, /* IRRoundingMode(I32) x F32 -> signed I32 */
Iop_F32toI64S, /* IRRoundingMode(I32) x F32 -> signed I64 */
Iop_F32toI32U, /* IRRoundingMode(I32) x F32 -> unsigned I32 */
Iop_F32toI64U, /* IRRoundingMode(I32) x F32 -> unsigned I64 */
Iop_I32StoF32, /* IRRoundingMode(I32) x signed I32 -> F32 */
Iop_I64StoF32, /* IRRoundingMode(I32) x signed I64 -> F32 */
/* Conversion between floating point formats */
Iop_F32toF64, /* F32 -> F64 */
Iop_F64toF32, /* IRRoundingMode(I32) x F64 -> F32 */
/* Reinterpretation. Take an F64 and produce an I64 with
the same bit pattern, or vice versa. */
Iop_ReinterpF64asI64, Iop_ReinterpI64asF64,
Iop_ReinterpF32asI32, Iop_ReinterpI32asF32,
/* Support for 128-bit floating point */
Iop_F64HLtoF128,/* (high half of F128,low half of F128) -> F128 */
Iop_F128HItoF64,/* F128 -> high half of F128 into a F64 register */
Iop_F128LOtoF64,/* F128 -> low half of F128 into a F64 register */
/* :: IRRoundingMode(I32) x F128 x F128 -> F128 */
Iop_AddF128, Iop_SubF128, Iop_MulF128, Iop_DivF128,
Iop_MAddF128, // (A * B) + C
Iop_MSubF128, // (A * B) - C
Iop_NegMAddF128, // -((A * B) + C)
Iop_NegMSubF128, // -((A * B) - C)
/* :: F128 -> F128 */
Iop_NegF128, Iop_AbsF128,
/* :: IRRoundingMode(I32) x F128 -> F128 */
Iop_SqrtF128,
Iop_I32StoF128, /* signed I32 -> F128 */
Iop_I64StoF128, /* signed I64 -> F128 */
Iop_I32UtoF128, /* unsigned I32 -> F128 */
Iop_I64UtoF128, /* unsigned I64 -> F128 */
Iop_F32toF128, /* F32 -> F128 */
Iop_F64toF128, /* F64 -> F128 */
Iop_F128toI32S, /* IRRoundingMode(I32) x F128 -> signed I32 */
Iop_F128toI64S, /* IRRoundingMode(I32) x F128 -> signed I64 */
Iop_F128toI32U, /* IRRoundingMode(I32) x F128 -> unsigned I32 */
Iop_F128toI64U, /* IRRoundingMode(I32) x F128 -> unsigned I64 */
Iop_F128toI128S,/* IRRoundingMode(I32) x F128 -> signed I128 */
Iop_F128toF64, /* IRRoundingMode(I32) x F128 -> F64 */
Iop_F128toF32, /* IRRoundingMode(I32) x F128 -> F32 */
Iop_RndF128, /* IRRoundingMode(I32) x F128 -> F128 */
/* Truncate to the specified value, source and result
* are stroed in a F128 register.
*/
Iop_TruncF128toI32S, /* truncate F128 -> I32 */
Iop_TruncF128toI32U, /* truncate F128 -> I32 */
Iop_TruncF128toI64U, /* truncate F128 -> I64 */
Iop_TruncF128toI64S, /* truncate F128 -> I64 */
/* --- guest x86/amd64 specifics, not mandated by 754. --- */
/* Binary ops, with rounding. */
/* :: IRRoundingMode(I32) x F64 x F64 -> F64 */
Iop_AtanF64, /* FPATAN, arctan(arg1/arg2) */
Iop_Yl2xF64, /* FYL2X, arg1 * log2(arg2) */
Iop_Yl2xp1F64, /* FYL2XP1, arg1 * log2(arg2+1.0) */
Iop_PRemF64, /* FPREM, non-IEEE remainder(arg1/arg2) */
Iop_PRemC3210F64, /* C3210 flags resulting from FPREM, :: I32 */
Iop_PRem1F64, /* FPREM1, IEEE remainder(arg1/arg2) */
Iop_PRem1C3210F64, /* C3210 flags resulting from FPREM1, :: I32 */
Iop_ScaleF64, /* FSCALE, arg1 * (2^RoundTowardsZero(arg2)) */
/* Note that on x86 guest, PRem1{C3210} has the same behaviour
as the IEEE mandated RemF64, except it is limited in the
range of its operand. Hence the partialness. */
/* Unary ops, with rounding. */
/* :: IRRoundingMode(I32) x F64 -> F64 */
Iop_SinF64, /* FSIN */
Iop_CosF64, /* FCOS */
Iop_TanF64, /* FTAN */
Iop_2xm1F64, /* (2^arg - 1.0) */
Iop_RoundF128toInt, /* F128 value to nearest integral value (still
as F128) */
Iop_RoundF64toInt, /* F64 value to nearest integral value (still
as F64) */
Iop_RoundF32toInt, /* F32 value to nearest integral value (still
as F32) */
/* --- guest s390 specifics, not mandated by 754. --- */
/* Fused multiply-add/sub */
/* :: IRRoundingMode(I32) x F32 x F32 x F32 -> F32
(computes arg2 * arg3 +/- arg4) */
Iop_MAddF32, Iop_MSubF32,
/* --- guest ppc32/64 specifics, not mandated by 754. --- */
/* Ternary operations, with rounding. */
/* Fused multiply-add/sub, with 112-bit intermediate
precision for ppc.
Also used to implement fused multiply-add/sub for s390. */
/* :: IRRoundingMode(I32) x F64 x F64 x F64 -> F64
(computes arg2 * arg3 +/- arg4) */
Iop_MAddF64, Iop_MSubF64,
/* Variants of the above which produce a 64-bit result but which
round their result to a IEEE float range first. */
/* :: IRRoundingMode(I32) x F64 x F64 x F64 -> F64 */
Iop_MAddF64r32, Iop_MSubF64r32,
/* :: F64 -> F64 */
Iop_RSqrtEst5GoodF64, /* reciprocal square root estimate, 5 good bits */
Iop_RoundF64toF64_NEAREST, /* frin */
Iop_RoundF64toF64_NegINF, /* frim */
Iop_RoundF64toF64_PosINF, /* frip */
Iop_RoundF64toF64_ZERO, /* friz */
/* :: F64 -> F32 */
Iop_TruncF64asF32, /* do F64->F32 truncation as per 'fsts' */
/* :: IRRoundingMode(I32) x F64 -> F64 */
Iop_RoundF64toF32, /* round F64 to nearest F32 value (still as F64) */
/* NB: pretty much the same as Iop_F64toF32, except no change
of type. */
/* --- guest arm64 specifics, not mandated by 754. --- */
Iop_RecpExpF64, /* FRECPX d :: IRRoundingMode(I32) x F64 -> F64 */
Iop_RecpExpF32, /* FRECPX s :: IRRoundingMode(I32) x F32 -> F32 */
/* --------- Possibly required by IEEE 754-2008. --------- */
Iop_MaxNumF64, /* max, F64, numerical operand if other is a qNaN */
Iop_MinNumF64, /* min, F64, ditto */
Iop_MaxNumF32, /* max, F32, ditto */
Iop_MinNumF32, /* min, F32, ditto */
/* ------------------ 16-bit scalar FP ------------------ */
Iop_F16toF64, /* F16 -> F64 */
Iop_F64toF16, /* IRRoundingMode(I32) x F64 -> F16 */
Iop_F16toF32, /* F16 -> F32 */
Iop_F32toF16, /* IRRoundingMode(I32) x F32 -> F16 */
/* ------------------ 32-bit SIMD Integer ------------------ */
/* 32x1 saturating add/sub (ok, well, not really SIMD :) */
Iop_QAdd32S,
Iop_QSub32S,
/* 16x2 add/sub, also signed/unsigned saturating variants */
Iop_Add16x2, Iop_Sub16x2,
Iop_QAdd16Sx2, Iop_QAdd16Ux2,
Iop_QSub16Sx2, Iop_QSub16Ux2,
/* 16x2 signed/unsigned halving add/sub. For each lane, these
compute bits 16:1 of (eg) sx(argL) + sx(argR),
or zx(argL) - zx(argR) etc. */
Iop_HAdd16Ux2, Iop_HAdd16Sx2,
Iop_HSub16Ux2, Iop_HSub16Sx2,
/* 8x4 add/sub, also signed/unsigned saturating variants */
Iop_Add8x4, Iop_Sub8x4,
Iop_QAdd8Sx4, Iop_QAdd8Ux4,
Iop_QSub8Sx4, Iop_QSub8Ux4,
/* 8x4 signed/unsigned halving add/sub. For each lane, these
compute bits 8:1 of (eg) sx(argL) + sx(argR),
or zx(argL) - zx(argR) etc. */
Iop_HAdd8Ux4, Iop_HAdd8Sx4,
Iop_HSub8Ux4, Iop_HSub8Sx4,
/* 8x4 sum of absolute unsigned differences. */
Iop_Sad8Ux4,
/* MISC (vector integer cmp != 0) */
Iop_CmpNEZ16x2, Iop_CmpNEZ8x4,
/* ------------------ 64-bit SIMD FP ------------------------ */
/* Convertion to/from int */
Iop_I32UtoFx2, Iop_I32StoFx2, /* I32x4 -> F32x4 */
Iop_FtoI32Ux2_RZ, Iop_FtoI32Sx2_RZ, /* F32x4 -> I32x4 */
/* Fixed32 format is floating-point number with fixed number of fraction
bits. The number of fraction bits is passed as a second argument of
type I8. */
Iop_F32ToFixed32Ux2_RZ, Iop_F32ToFixed32Sx2_RZ, /* fp -> fixed-point */
Iop_Fixed32UToF32x2_RN, Iop_Fixed32SToF32x2_RN, /* fixed-point -> fp */
/* Binary operations */
Iop_Max32Fx2, Iop_Min32Fx2,
/* Pairwise Min and Max. See integer pairwise operations for more
details. */
Iop_PwMax32Fx2, Iop_PwMin32Fx2,
/* Note: For the following compares, the arm front-end assumes a
nan in a lane of either argument returns zero for that lane. */
Iop_CmpEQ32Fx2, Iop_CmpGT32Fx2, Iop_CmpGE32Fx2,
/* Vector Reciprocal Estimate finds an approximate reciprocal of each
element in the operand vector, and places the results in the destination
vector. */
Iop_RecipEst32Fx2,
/* Vector Reciprocal Step computes (2.0 - arg1 * arg2).
Note, that if one of the arguments is zero and another one is infinity
of arbitrary sign the result of the operation is 2.0. */
Iop_RecipStep32Fx2,
/* Vector Reciprocal Square Root Estimate finds an approximate reciprocal
square root of each element in the operand vector. */
Iop_RSqrtEst32Fx2,
/* Vector Reciprocal Square Root Step computes (3.0 - arg1 * arg2) / 2.0.
Note, that of one of the arguments is zero and another one is infiinty
of arbitrary sign the result of the operation is 1.5. */
Iop_RSqrtStep32Fx2,
/* Unary */
Iop_Neg32Fx2, Iop_Abs32Fx2,
/* ------------------ 64-bit SIMD Integer. ------------------ */
/* MISC (vector integer cmp != 0) */
Iop_CmpNEZ8x8, Iop_CmpNEZ16x4, Iop_CmpNEZ32x2,
/* ADDITION (normal / unsigned sat / signed sat) */
Iop_Add8x8, Iop_Add16x4, Iop_Add32x2,
Iop_QAdd8Ux8, Iop_QAdd16Ux4, Iop_QAdd32Ux2, Iop_QAdd64Ux1,
Iop_QAdd8Sx8, Iop_QAdd16Sx4, Iop_QAdd32Sx2, Iop_QAdd64Sx1,
/* PAIRWISE operations */
/* Iop_PwFoo16x4( [a,b,c,d], [e,f,g,h] ) =
[Foo16(a,b), Foo16(c,d), Foo16(e,f), Foo16(g,h)] */
Iop_PwAdd8x8, Iop_PwAdd16x4, Iop_PwAdd32x2,
Iop_PwMax8Sx8, Iop_PwMax16Sx4, Iop_PwMax32Sx2,
Iop_PwMax8Ux8, Iop_PwMax16Ux4, Iop_PwMax32Ux2,
Iop_PwMin8Sx8, Iop_PwMin16Sx4, Iop_PwMin32Sx2,
Iop_PwMin8Ux8, Iop_PwMin16Ux4, Iop_PwMin32Ux2,
/* Longening variant is unary. The resulting vector contains two times
less elements than operand, but they are two times wider.
Example:
Iop_PAddL16Ux4( [a,b,c,d] ) = [a+b,c+d]
where a+b and c+d are unsigned 32-bit values. */
Iop_PwAddL8Ux8, Iop_PwAddL16Ux4, Iop_PwAddL32Ux2,
Iop_PwAddL8Sx8, Iop_PwAddL16Sx4, Iop_PwAddL32Sx2,
/* SUBTRACTION (normal / unsigned sat / signed sat) */
Iop_Sub8x8, Iop_Sub16x4, Iop_Sub32x2,
Iop_QSub8Ux8, Iop_QSub16Ux4, Iop_QSub32Ux2, Iop_QSub64Ux1,
Iop_QSub8Sx8, Iop_QSub16Sx4, Iop_QSub32Sx2, Iop_QSub64Sx1,
/* ABSOLUTE VALUE */
Iop_Abs8x8, Iop_Abs16x4, Iop_Abs32x2,
/* MULTIPLICATION (normal / high half of signed/unsigned / plynomial ) */
Iop_Mul8x8, Iop_Mul16x4, Iop_Mul32x2,
Iop_Mul32Fx2,
Iop_MulHi16Ux4,
Iop_MulHi16Sx4,
/* Plynomial multiplication treats it's arguments as coefficients of
polynoms over {0, 1}. */
Iop_PolynomialMul8x8,
/* Vector Saturating Doubling Multiply Returning High Half and
Vector Saturating Rounding Doubling Multiply Returning High Half */
/* These IROp's multiply corresponding elements in two vectors, double
the results, and place the most significant half of the final results
in the destination vector. The results are truncated or rounded. If
any of the results overflow, they are saturated. */
Iop_QDMulHi16Sx4, Iop_QDMulHi32Sx2,
Iop_QRDMulHi16Sx4, Iop_QRDMulHi32Sx2,
/* AVERAGING: note: (arg1 + arg2 + 1) >>u 1 */
Iop_Avg8Ux8,
Iop_Avg16Ux4,
/* MIN/MAX */
Iop_Max8Sx8, Iop_Max16Sx4, Iop_Max32Sx2,
Iop_Max8Ux8, Iop_Max16Ux4, Iop_Max32Ux2,
Iop_Min8Sx8, Iop_Min16Sx4, Iop_Min32Sx2,
Iop_Min8Ux8, Iop_Min16Ux4, Iop_Min32Ux2,
/* COMPARISON */
Iop_CmpEQ8x8, Iop_CmpEQ16x4, Iop_CmpEQ32x2,
Iop_CmpGT8Ux8, Iop_CmpGT16Ux4, Iop_CmpGT32Ux2,
Iop_CmpGT8Sx8, Iop_CmpGT16Sx4, Iop_CmpGT32Sx2,
/* COUNT ones / leading zeroes / leading sign bits (not including topmost
bit) */
Iop_Cnt8x8,
Iop_Clz8x8, Iop_Clz16x4, Iop_Clz32x2,
Iop_Cls8x8, Iop_Cls16x4, Iop_Cls32x2,
Iop_Clz64x2,
/*Vector COUNT trailing zeros */
Iop_Ctz8x16, Iop_Ctz16x8, Iop_Ctz32x4, Iop_Ctz64x2,
/* VECTOR x VECTOR SHIFT / ROTATE */
Iop_Shl8x8, Iop_Shl16x4, Iop_Shl32x2,
Iop_Shr8x8, Iop_Shr16x4, Iop_Shr32x2,
Iop_Sar8x8, Iop_Sar16x4, Iop_Sar32x2,
Iop_Sal8x8, Iop_Sal16x4, Iop_Sal32x2, Iop_Sal64x1,
/* VECTOR x SCALAR SHIFT (shift amt :: Ity_I8) */
Iop_ShlN8x8, Iop_ShlN16x4, Iop_ShlN32x2,
Iop_ShrN8x8, Iop_ShrN16x4, Iop_ShrN32x2,
Iop_SarN8x8, Iop_SarN16x4, Iop_SarN32x2,
/* VECTOR x VECTOR SATURATING SHIFT */
Iop_QShl8x8, Iop_QShl16x4, Iop_QShl32x2, Iop_QShl64x1,
Iop_QSal8x8, Iop_QSal16x4, Iop_QSal32x2, Iop_QSal64x1,
/* VECTOR x INTEGER SATURATING SHIFT */
Iop_QShlNsatSU8x8, Iop_QShlNsatSU16x4,
Iop_QShlNsatSU32x2, Iop_QShlNsatSU64x1,
Iop_QShlNsatUU8x8, Iop_QShlNsatUU16x4,
Iop_QShlNsatUU32x2, Iop_QShlNsatUU64x1,
Iop_QShlNsatSS8x8, Iop_QShlNsatSS16x4,
Iop_QShlNsatSS32x2, Iop_QShlNsatSS64x1,
/* NARROWING (binary)
-- narrow 2xI64 into 1xI64, hi half from left arg */
/* For saturated narrowing, I believe there are 4 variants of
the basic arithmetic operation, depending on the signedness
of argument and result. Here are examples that exemplify
what I mean:
QNarrow16Uto8U ( UShort x ) if (x >u 255) x = 255;
return x[7:0];
QNarrow16Sto8S ( Short x ) if (x <s -128) x = -128;
if (x >s 127) x = 127;
return x[7:0];
QNarrow16Uto8S ( UShort x ) if (x >u 127) x = 127;
return x[7:0];
QNarrow16Sto8U ( Short x ) if (x <s 0) x = 0;
if (x >s 255) x = 255;
return x[7:0];
*/
Iop_QNarrowBin16Sto8Ux8,
Iop_QNarrowBin16Sto8Sx8, Iop_QNarrowBin32Sto16Sx4,
Iop_NarrowBin16to8x8, Iop_NarrowBin32to16x4,
/* INTERLEAVING */
/* Interleave lanes from low or high halves of
operands. Most-significant result lane is from the left
arg. */
Iop_InterleaveHI8x8, Iop_InterleaveHI16x4, Iop_InterleaveHI32x2,
Iop_InterleaveLO8x8, Iop_InterleaveLO16x4, Iop_InterleaveLO32x2,
/* Interleave odd/even lanes of operands. Most-significant result lane