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s32k1xx_flexcan.c
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s32k1xx_flexcan.c
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/****************************************************************************
* arch/arm/src/s32k1xx/s32k1xx_flexcan.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <inttypes.h>
#include <stdint.h>
#include <stdbool.h>
#include <unistd.h>
#include <time.h>
#include <string.h>
#include <debug.h>
#include <errno.h>
#include <nuttx/can.h>
#include <nuttx/wdog.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/wqueue.h>
#include <nuttx/signal.h>
#include <nuttx/net/netdev.h>
#include <nuttx/net/can.h>
#include "arm_internal.h"
#include "chip.h"
#include "s32k1xx_config.h"
#include "hardware/s32k1xx_flexcan.h"
#include "hardware/s32k1xx_pinmux.h"
#include "s32k1xx_periphclocks.h"
#include "s32k1xx_pin.h"
#include "s32k1xx_flexcan.h"
#include <arch/board/board.h>
#include <sys/time.h>
#ifdef CONFIG_S32K1XX_FLEXCAN
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* If processing is not done at the interrupt level, then work queue support
* is required.
*/
#define CANWORK LPWORK
/* CONFIG_S32K1XX_FLEXCAN_NETHIFS determines the number of physical
* interfaces that will be supported.
*/
#define MASKSTDID 0x000007ff
#define MASKEXTID 0x1fffffff
#define FLAGEFF (1 << 31) /* Extended frame format */
#define FLAGRTR (1 << 30) /* Remote transmission request */
#define RXMBCOUNT 5
#define TXMBCOUNT 2
#define TOTALMBCOUNT RXMBCOUNT + TXMBCOUNT
#define IFLAG1_RX ((1 << RXMBCOUNT)-1)
#define IFLAG1_TX (((1 << TXMBCOUNT)-1) << RXMBCOUNT)
#define CAN_FIFO_NE (1 << 5)
#define CAN_FIFO_OV (1 << 6)
#define CAN_FIFO_WARN (1 << 7)
#define CAN_EFF_FLAG 0x80000000 /* EFF/SFF is set in the MSB */
#define POOL_SIZE 1
#if defined(CONFIG_NET_CAN_RAW_TX_DEADLINE) || defined(CONFIG_NET_TIMESTAMP)
#define MSG_DATA sizeof(struct timeval)
#else
#define MSG_DATA 0
#endif
/* CAN bit timing values */
#define CLK_FREQ 80000000
#define PRESDIV_MAX 256
#define SEG_MAX 8
#define SEG_MIN 1
#define TSEG_MIN 2
#define TSEG1_MAX 17
#define TSEG2_MAX 9
#define NUMTQ_MAX 26
#define SEG_FD_MAX 32
#define SEG_FD_MIN 1
#define TSEG_FD_MIN 2
#define TSEG1_FD_MAX 39
#define TSEG2_FD_MAX 9
#define NUMTQ_FD_MAX 49
#ifdef CONFIG_NET_CAN_RAW_TX_DEADLINE
# if !defined(CONFIG_SCHED_WORKQUEUE)
# error Work queue support is required
# endif
#define TX_TIMEOUT_WQ
#endif
/* Interrupt flags for RX fifo */
#define IFLAG1_RXFIFO (CAN_FIFO_NE | CAN_FIFO_WARN | CAN_FIFO_OV)
static int peak_tx_mailbox_index_ = 0;
/****************************************************************************
* Private Types
****************************************************************************/
union cs_e
{
volatile uint32_t cs;
struct
{
volatile uint32_t time_stamp : 16;
volatile uint32_t dlc : 4;
volatile uint32_t rtr : 1;
volatile uint32_t ide : 1;
volatile uint32_t srr : 1;
volatile uint32_t res : 1;
volatile uint32_t code : 4;
volatile uint32_t res2 : 1;
volatile uint32_t esi : 1;
volatile uint32_t brs : 1;
volatile uint32_t edl : 1;
};
};
union id_e
{
volatile uint32_t w;
struct
{
volatile uint32_t ext : 29;
volatile uint32_t resex : 3;
};
struct
{
volatile uint32_t res : 18;
volatile uint32_t std : 11;
volatile uint32_t resstd : 3;
};
};
union data_e
{
volatile uint32_t w00;
struct
{
volatile uint32_t b03 : 8;
volatile uint32_t b02 : 8;
volatile uint32_t b01 : 8;
volatile uint32_t b00 : 8;
};
};
struct mb_s
{
union cs_e cs;
union id_e id;
#ifdef CONFIG_NET_CAN_CANFD
union data_e data[16];
#else
union data_e data[2];
#endif
};
#ifdef CONFIG_NET_CAN_RAW_TX_DEADLINE
#define TX_ABORT -1
#define TX_FREE 0
#define TX_BUSY 1
struct txmbstats
{
struct timeval deadline;
uint32_t pending; /* -1 = abort, 0 = free, 1 = busy */
};
#endif
/* FlexCAN Device hardware configuration */
struct flexcan_config_s
{
uint32_t tx_pin; /* GPIO configuration for TX */
uint32_t rx_pin; /* GPIO configuration for RX */
uint32_t enable_pin; /* Optional enable pin */
uint32_t enable_high; /* Optional enable high/low */
uint32_t bus_irq; /* BUS IRQ */
uint32_t error_irq; /* ERROR IRQ */
uint32_t lprx_irq; /* LPRX IRQ */
uint32_t mb_irq; /* MB 0-15 IRQ */
};
struct flexcan_timeseg
{
uint32_t bitrate;
int32_t samplep;
uint8_t propseg;
uint8_t pseg1;
uint8_t pseg2;
uint8_t presdiv;
};
/* FlexCAN device structures */
#ifdef CONFIG_S32K1XX_FLEXCAN0
static const struct flexcan_config_s s32k1xx_flexcan0_config =
{
.tx_pin = PIN_CAN0_TX,
.rx_pin = PIN_CAN0_RX,
#ifdef PIN_CAN0_ENABLE
.enable_pin = PIN_CAN0_ENABLE,
.enable_high = CAN0_ENABLE_OUT,
#else
.enable_pin = 0,
.enable_high = 0,
#endif
.bus_irq = S32K1XX_IRQ_CAN0_BUS,
.error_irq = S32K1XX_IRQ_CAN0_ERROR,
.lprx_irq = S32K1XX_IRQ_CAN0_LPRX,
.mb_irq = S32K1XX_IRQ_CAN0_0_15,
};
#endif
#ifdef CONFIG_S32K1XX_FLEXCAN1
static const struct flexcan_config_s s32k1xx_flexcan1_config =
{
.tx_pin = PIN_CAN1_TX,
.rx_pin = PIN_CAN1_RX,
#ifdef PIN_CAN1_ENABLE
.enable_pin = PIN_CAN1_ENABLE,
.enable_high = CAN1_ENABLE_OUT,
#else
.enable_pin = 0,
.enable_high = 0,
#endif
.bus_irq = S32K1XX_IRQ_CAN1_BUS,
.error_irq = S32K1XX_IRQ_CAN1_ERROR,
.lprx_irq = 0,
.mb_irq = S32K1XX_IRQ_CAN1_0_15,
};
#endif
#ifdef CONFIG_S32K1XX_FLEXCAN2
static const struct flexcan_config_s s32k1xx_flexcan2_config =
{
.tx_pin = PIN_CAN2_TX,
.rx_pin = PIN_CAN2_RX,
#ifdef PIN_CAN2_ENABLE
.enable_pin = PIN_CAN2_ENABLE,
.rx_pin = CAN2_ENABLE_HIGH,
#else
.enable_pin = 0,
.rx_pin = 0,
#endif
.bus_irq = S32K1XX_IRQ_CAN2_BUS,
.error_irq = S32K1XX_IRQ_CAN2_ERROR,
.lprx_irq = 0,
.mb_irq = S32K1XX_IRQ_CAN2_0_15,
};
#endif
/* The s32k1xx_driver_s encapsulates all state information for a single
* hardware interface
*/
struct s32k1xx_driver_s
{
uint32_t base; /* FLEXCAN base address */
bool bifup; /* true:ifup false:ifdown */
#ifdef TX_TIMEOUT_WQ
struct wdog_s txtimeout[TXMBCOUNT]; /* TX timeout timer */
#endif
struct work_s irqwork; /* For deferring interrupt work to the wq */
struct work_s pollwork; /* For deferring poll work to the work wq */
#ifdef CONFIG_NET_CAN_CANFD
struct canfd_frame *txdesc; /* A pointer to the list of TX descriptor */
struct canfd_frame *rxdesc; /* A pointer to the list of RX descriptors */
#else
struct can_frame *txdesc; /* A pointer to the list of TX descriptor */
struct can_frame *rxdesc; /* A pointer to the list of RX descriptors */
#endif
/* This holds the information visible to the NuttX network */
struct net_driver_s dev; /* Interface understood by the network */
struct mb_s *rx;
struct mb_s *tx;
struct flexcan_timeseg arbi_timing; /* Timing for arbitration phase */
#ifdef CONFIG_NET_CAN_CANFD
struct flexcan_timeseg data_timing; /* Timing for data phase */
#endif
const struct flexcan_config_s *config;
#ifdef CONFIG_NET_CAN_RAW_TX_DEADLINE
struct txmbstats txmb[TXMBCOUNT];
#endif
};
/****************************************************************************
* Private Data
****************************************************************************/
#ifdef CONFIG_S32K1XX_FLEXCAN0
static struct s32k1xx_driver_s g_flexcan0;
#endif
#ifdef CONFIG_S32K1XX_FLEXCAN1
static struct s32k1xx_driver_s g_flexcan1;
#endif
#ifdef CONFIG_S32K1XX_FLEXCAN2
static struct s32k1xx_driver_s g_flexcan2;
#endif
#ifdef CONFIG_NET_CAN_CANFD
static uint8_t g_tx_pool[(sizeof(struct canfd_frame)+MSG_DATA)*POOL_SIZE];
static uint8_t g_rx_pool[(sizeof(struct canfd_frame)+MSG_DATA)*POOL_SIZE];
#else
static uint8_t g_tx_pool[(sizeof(struct can_frame)+MSG_DATA)*POOL_SIZE];
static uint8_t g_rx_pool[(sizeof(struct can_frame)+MSG_DATA)*POOL_SIZE];
#endif
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: arm_lsb
*
* Description:
* Calculate position of lsb that's equal to 1
*
* Input Parameters:
* value - The value to perform the operation on
*
* Returned Value:
* location of lsb which is equal to 1, returns 32 when value is 0
*
****************************************************************************/
static inline uint32_t arm_lsb(unsigned int value)
{
uint32_t ret;
volatile uint32_t rvalue = value;
__asm__ __volatile__ ("rbit %1,%0" : "=r" (rvalue) : "r" (rvalue));
__asm__ __volatile__ ("clz %0, %1" : "=r"(ret) : "r"(rvalue));
return ret;
}
/****************************************************************************
* Name: s32k1xx_bitratetotimeseg
*
* Description:
* Convert bitrate to timeseg
*
* Input Parameters:
* timeseg - structure to store bit timing
* sp_tolerance - allowed difference in sample point from calculated
* bit timings (recommended value: 1)
* can_fd - if set to calculate CAN FD bit timings, otherwise calculate
* classical can timings
*
* Returned Value:
* return 1 on success, return 0 on failure
*
****************************************************************************/
uint32_t s32k1xx_bitratetotimeseg(struct flexcan_timeseg *timeseg,
int32_t sp_tolerance,
uint32_t can_fd)
{
int32_t tmppresdiv;
int32_t numtq;
int32_t tmpsample;
int32_t tseg1;
int32_t tseg2;
int32_t tmppseg1;
int32_t tmppseg2;
int32_t tmppropseg;
const int32_t TSEG1MAX = (can_fd ? TSEG1_FD_MAX : TSEG1_MAX);
const int32_t TSEG2MAX = (can_fd ? TSEG2_FD_MAX : TSEG2_MAX);
const int32_t SEGMAX = (can_fd ? SEG_FD_MAX : SEG_MAX);
const int32_t NUMTQMAX = (can_fd ? NUMTQ_FD_MAX : NUMTQ_MAX);
for (tmppresdiv = 0; tmppresdiv < PRESDIV_MAX; tmppresdiv++)
{
numtq = (CLK_FREQ / ((tmppresdiv + 1) * timeseg->bitrate));
if (numtq == 0)
{
continue;
}
/* The number of time quanta in 1 bit time must be
* lower than the one supported
*/
if ((CLK_FREQ / ((tmppresdiv + 1) * numtq) == timeseg->bitrate)
&& (numtq >= 8) && (numtq < NUMTQMAX))
{
/* Compute time segments based on the value of the sampling point */
tseg1 = (numtq * timeseg->samplep / 100) - 1;
tseg2 = numtq - 1 - tseg1;
/* Adjust time segment 1 and time segment 2 */
while (tseg1 >= TSEG1MAX || tseg2 < TSEG_MIN)
{
tseg2++;
tseg1--;
}
tmppseg2 = tseg2 - 1;
/* Start from pseg1 = pseg2 and adjust until propseg is valid */
tmppseg1 = tmppseg2;
tmppropseg = tseg1 - tmppseg1 - 2;
while (tmppropseg <= 0)
{
tmppropseg++;
tmppseg1--;
}
while (tmppropseg >= SEGMAX)
{
tmppropseg--;
tmppseg1++;
}
if (((tseg1 >= TSEG1MAX) || (tseg2 >= TSEG2MAX) ||
(tseg2 < TSEG_MIN) || (tseg1 < TSEG_MIN)) ||
((tmppropseg >= SEGMAX) || (tmppseg1 >= SEGMAX) ||
(tmppseg2 < SEG_MIN) || (tmppseg2 >= SEGMAX)))
{
continue;
}
tmpsample = ((tseg1 + 1) * 100) / numtq;
if ((tmpsample - timeseg->samplep) <= sp_tolerance &&
(timeseg->samplep - tmpsample) <= sp_tolerance)
{
if (can_fd == 1)
{
timeseg->propseg = tmppropseg + 1;
}
else
{
timeseg->propseg = tmppropseg;
}
timeseg->pseg1 = tmppseg1;
timeseg->pseg2 = tmppseg2;
timeseg->presdiv = tmppresdiv;
timeseg->samplep = tmpsample;
return 1;
}
}
}
return 0;
}
/* Common TX logic */
static bool s32k1xx_txringfull(struct s32k1xx_driver_s *priv);
static int s32k1xx_transmit(struct s32k1xx_driver_s *priv);
static int s32k1xx_txpoll(struct net_driver_s *dev);
/* Helper functions */
static void s32k1xx_setenable(uint32_t base, uint32_t enable);
static void s32k1xx_setfreeze(uint32_t base, uint32_t freeze);
static uint32_t s32k1xx_waitmcr_change(uint32_t base,
uint32_t mask,
uint32_t target_state);
/* Interrupt handling */
static void s32k1xx_receive(struct s32k1xx_driver_s *priv,
uint32_t flags);
static void s32k1xx_txdone_work(void *arg);
static void s32k1xx_txdone(struct s32k1xx_driver_s *priv);
static int s32k1xx_flexcan_interrupt(int irq, void *context,
void *arg);
/* Watchdog timer expirations */
#ifdef TX_TIMEOUT_WQ
static void s32k1xx_txtimeout_work(void *arg);
static void s32k1xx_txtimeout_expiry(wdparm_t arg);
#endif
/* NuttX callback functions */
static int s32k1xx_ifup(struct net_driver_s *dev);
static int s32k1xx_ifdown(struct net_driver_s *dev);
static void s32k1xx_txavail_work(void *arg);
static int s32k1xx_txavail(struct net_driver_s *dev);
#ifdef CONFIG_NETDEV_IOCTL
static int s32k1xx_ioctl(struct net_driver_s *dev, int cmd,
unsigned long arg);
#endif
/* Initialization */
static int s32k1xx_initialize(struct s32k1xx_driver_s *priv);
static void s32k1xx_reset(struct s32k1xx_driver_s *priv);
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Function: s32k1xx_txringfull
*
* Description:
* Check if all of the TX descriptors are in use.
*
* Input Parameters:
* priv - Reference to the driver state structure
*
* Returned Value:
* true is the TX ring is full; false if there are free slots at the
* head index.
*
****************************************************************************/
static bool s32k1xx_txringfull(struct s32k1xx_driver_s *priv)
{
uint32_t mbi = 0;
while (mbi < TXMBCOUNT)
{
if (priv->tx[mbi].cs.code != CAN_TXMB_DATAORREMOTE)
{
return 0;
}
mbi++;
}
return 1;
}
/****************************************************************************
* Function: s32k1xx_transmit
*
* Description:
* Start hardware transmission. Called either from the txdone interrupt
* handling or from watchdog based polling.
*
* Input Parameters:
* priv - Reference to the driver state structure
*
* Returned Value:
* OK on success; a negated errno on failure
*
* Assumptions:
* May or may not be called from an interrupt handler. In either case,
* global interrupts are disabled, either explicitly or indirectly through
* interrupt handling logic.
*
****************************************************************************/
static int s32k1xx_transmit(struct s32k1xx_driver_s *priv)
{
/* Attempt to write frame */
uint32_t mbi = 0;
uint32_t mb_bit;
uint32_t regval;
#ifdef CONFIG_NET_CAN_CANFD
uint32_t *frame_data_word;
uint32_t i;
#endif
#ifdef CONFIG_NET_CAN_RAW_TX_DEADLINE
int32_t timeout;
#endif
if ((getreg32(priv->base + S32K1XX_CAN_ESR2_OFFSET) &
(CAN_ESR2_IMB | CAN_ESR2_VPS)) ==
(CAN_ESR2_IMB | CAN_ESR2_VPS))
{
mbi = ((getreg32(priv->base + S32K1XX_CAN_ESR2_OFFSET) &
CAN_ESR2_LPTM_MASK) >> CAN_ESR2_LPTM_SHIFT);
mbi -= RXMBCOUNT;
}
mb_bit = 1 << (RXMBCOUNT + mbi);
while (mbi < TXMBCOUNT)
{
if (priv->tx[mbi].cs.code != CAN_TXMB_DATAORREMOTE)
{
putreg32(mb_bit, priv->base + S32K1XX_CAN_IFLAG1_OFFSET);
break;
}
mb_bit <<= 1;
mbi++;
}
if (mbi == TXMBCOUNT)
{
nwarn("No TX MB available mbi %" PRIu32 "\n", mbi);
NETDEV_TXERRORS(&priv->dev);
return 0; /* No transmission for you! */
}
#ifdef CONFIG_NET_CAN_RAW_TX_DEADLINE
struct timespec ts;
clock_systime_timespec(&ts);
if (priv->dev.d_sndlen > priv->dev.d_len)
{
struct timeval *tv =
(struct timeval *)(priv->dev.d_buf + priv->dev.d_len);
priv->txmb[mbi].deadline = *tv;
timeout = (tv->tv_sec - ts.tv_sec)*CLK_TCK
+ ((tv->tv_usec - ts.tv_nsec / 1000)*CLK_TCK) / 1000000;
if (timeout < 0)
{
return 0; /* No transmission for you! */
}
}
else
{
/* Default TX deadline defined in NET_CAN_RAW_DEFAULT_TX_DEADLINE */
if (CONFIG_NET_CAN_RAW_DEFAULT_TX_DEADLINE > 0)
{
timeout = ((CONFIG_NET_CAN_RAW_DEFAULT_TX_DEADLINE / 1000000)
*CLK_TCK);
priv->txmb[mbi].deadline.tv_sec = ts.tv_sec +
CONFIG_NET_CAN_RAW_DEFAULT_TX_DEADLINE / 1000000;
priv->txmb[mbi].deadline.tv_usec = (ts.tv_nsec / 1000) +
CONFIG_NET_CAN_RAW_DEFAULT_TX_DEADLINE % 1000000;
}
else
{
priv->txmb[mbi].deadline.tv_sec = 0;
priv->txmb[mbi].deadline.tv_usec = 0;
timeout = -1;
}
}
#endif
peak_tx_mailbox_index_ =
(peak_tx_mailbox_index_ > mbi ? peak_tx_mailbox_index_ : mbi);
union cs_e cs;
cs.code = CAN_TXMB_DATAORREMOTE;
struct mb_s *mb = &priv->tx[mbi];
mb->cs.code = CAN_TXMB_INACTIVE;
if (priv->dev.d_len <= sizeof(struct can_frame))
{
struct can_frame *frame = (struct can_frame *)priv->dev.d_buf;
if (frame->can_id & CAN_EFF_FLAG)
{
cs.ide = 1;
cs.srr = 1;
mb->id.ext = frame->can_id & MASKEXTID;
}
else
{
mb->id.std = frame->can_id & MASKSTDID;
}
cs.rtr = frame->can_id & FLAGRTR ? 1 : 0;
cs.dlc = frame->can_dlc;
mb->data[0].w00 = __builtin_bswap32(*(uint32_t *)&frame->data[0]);
mb->data[1].w00 = __builtin_bswap32(*(uint32_t *)&frame->data[4]);
}
#ifdef CONFIG_NET_CAN_CANFD
else /* CAN FD frame */
{
struct canfd_frame *frame = (struct canfd_frame *)priv->dev.d_buf;
cs.edl = 1; /* CAN FD Frame */
if (frame->can_id & CAN_EFF_FLAG)
{
cs.ide = 1;
cs.srr = 1;
mb->id.ext = frame->can_id & MASKEXTID;
}
else
{
mb->id.std = frame->can_id & MASKSTDID;
}
cs.rtr = frame->can_id & FLAGRTR ? 1 : 0;
cs.dlc = len_to_can_dlc[frame->len];
frame_data_word = (uint32_t *)&frame->data[0];
for (i = 0; i < (frame->len + 4 - 1) / 4; i++)
{
mb->data[i].w00 = __builtin_bswap32(frame_data_word[i]);
}
}
#endif
mb->cs = cs; /* Go. */
regval = getreg32(priv->base + S32K1XX_CAN_IMASK1_OFFSET);
regval |= mb_bit;
putreg32(regval, priv->base + S32K1XX_CAN_IMASK1_OFFSET);
/* Increment statistics */
NETDEV_TXPACKETS(&priv->dev);
#ifdef TX_TIMEOUT_WQ
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
if (timeout >= 0)
{
wd_start(&priv->txtimeout[mbi], timeout + 1,
s32k1xx_txtimeout_expiry, (wdparm_t)priv);
}
#endif
return OK;
}
/****************************************************************************
* Function: s32k1xx_txpoll
*
* Description:
* The transmitter is available, check if the network has any outgoing
* packets ready to send. This is a callback from devif_poll().
* devif_poll() may be called:
*
* 1. When the preceding TX packet send is complete,
* 2. When the preceding TX packet send timesout and the interface is reset
* 3. During normal TX polling
*
* Input Parameters:
* dev - Reference to the NuttX driver state structure
*
* Returned Value:
* OK on success; a negated errno on failure
*
* Assumptions:
* May or may not be called from an interrupt handler. In either case,
* global interrupts are disabled, either explicitly or indirectly through
* interrupt handling logic.
*
****************************************************************************/
static int s32k1xx_txpoll(struct net_driver_s *dev)
{
struct s32k1xx_driver_s *priv =
(struct s32k1xx_driver_s *)dev->d_private;
/* If the polling resulted in data that should be sent out on the network,
* the field d_len is set to a value > 0.
*/
if (priv->dev.d_len > 0)
{
s32k1xx_txdone(priv);
/* Send the packet */
s32k1xx_transmit(priv);
/* Check if there is room in the device to hold another packet. If
* not, return a non-zero value to terminate the poll.
*/
if ((getreg32(priv->base + S32K1XX_CAN_ESR2_OFFSET) &
(CAN_ESR2_IMB | CAN_ESR2_VPS)) ==
(CAN_ESR2_IMB | CAN_ESR2_VPS))
{
if (s32k1xx_txringfull(priv))
{
return -EBUSY;
}
}
}
/* If zero is returned, the polling will continue until all connections
* have been examined.
*/
return 0;
}
/****************************************************************************
* Function: s32k1xx_receive
*
* Description:
* An interrupt was received indicating the availability of a new RX packet
*
* Input Parameters:
* priv - Reference to the driver state structure
*
* Returned Value:
* None
*
* Assumptions:
* Global interrupts are disabled by interrupt handling logic.
*
****************************************************************************/
static void s32k1xx_receive(struct s32k1xx_driver_s *priv,
uint32_t flags)
{
uint32_t mb_index;
struct mb_s *rf;
#ifdef CONFIG_NET_CAN_CANFD
uint32_t *frame_data_word;
uint32_t i;
#endif
while ((mb_index = arm_lsb(flags)) != 32)
{
rf = &priv->rx[mb_index];
/* Read the frame contents */
#ifdef CONFIG_NET_CAN_CANFD
if (rf->cs.edl) /* CAN FD frame */
{
struct canfd_frame *frame = (struct canfd_frame *)priv->rxdesc;
if (rf->cs.ide)
{
frame->can_id = MASKEXTID & rf->id.ext;
frame->can_id |= FLAGEFF;
}
else
{
frame->can_id = MASKSTDID & rf->id.std;
}
if (rf->cs.rtr)
{
frame->can_id |= FLAGRTR;
}
frame->len = can_dlc_to_len[rf->cs.dlc];
frame_data_word = (uint32_t *)&frame->data[0];
for (i = 0; i < (frame->len + 4 - 1) / 4; i++)
{
frame_data_word[i] = __builtin_bswap32(rf->data[i].w00);
}
/* Clear MB interrupt flag */
putreg32(1 << mb_index,
priv->base + S32K1XX_CAN_IFLAG1_OFFSET);
/* Copy the buffer pointer to priv->dev.. Set amount of data
* in priv->dev.d_len
*/
priv->dev.d_len = sizeof(struct canfd_frame);
priv->dev.d_buf = (uint8_t *)frame;
}
else /* CAN 2.0 Frame */
#endif
{
struct can_frame *frame = (struct can_frame *)priv->rxdesc;
if (rf->cs.ide)
{
frame->can_id = MASKEXTID & rf->id.ext;
frame->can_id |= FLAGEFF;
}
else
{
frame->can_id = MASKSTDID & rf->id.std;
}
if (rf->cs.rtr)
{
frame->can_id |= FLAGRTR;
}
frame->can_dlc = rf->cs.dlc;
*(uint32_t *)&frame->data[0] = __builtin_bswap32(rf->data[0].w00);
*(uint32_t *)&frame->data[4] = __builtin_bswap32(rf->data[1].w00);
/* Clear MB interrupt flag */
putreg32(1 << mb_index,
priv->base + S32K1XX_CAN_IFLAG1_OFFSET);
/* Copy the buffer pointer to priv->dev.. Set amount of data
* in priv->dev.d_len
*/
priv->dev.d_len = sizeof(struct can_frame);
priv->dev.d_buf = (uint8_t *)frame;
}
/* Send to socket interface */
NETDEV_RXPACKETS(&priv->dev);
can_input(&priv->dev);
/* Point the packet buffer back to the next Tx buffer that will be
* used during the next write. If the write queue is full, then
* this will point at an active buffer, which must not be written
* to. This is OK because devif_poll won't be called unless the
* queue is not full.
*/
priv->dev.d_buf = (uint8_t *)priv->txdesc;
flags &= ~(1 << mb_index);
/* Reread interrupt flags and process them in this loop */
if (flags == 0)
{
flags = getreg32(priv->base + S32K1XX_CAN_IFLAG1_OFFSET);
flags &= IFLAG1_RX;
}
}
}
/****************************************************************************
* Function: s32k1xx_txdone
*
* Description:
* Check transmit interrupt flags and clear them
*
* Input Parameters:
* priv - Reference to the driver state structure
*
* Returned Value:
* None
*
* Assumptions:
* None
*
****************************************************************************/
static void s32k1xx_txdone(struct s32k1xx_driver_s *priv)
{
uint32_t flags;
uint32_t mbi;
uint32_t mb_bit;
flags = getreg32(priv->base + S32K1XX_CAN_IFLAG1_OFFSET);
flags &= IFLAG1_TX;
/* TODO First Process Error aborts */
/* Process TX completions */
mb_bit = 1 << RXMBCOUNT;
for (mbi = 0; flags && mbi < TXMBCOUNT; mbi++)