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[Topi, ARM] Disbale Winograd for quantized tensors. #5363

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merged 2 commits into from Apr 21, 2020

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anijain2305
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@anijain2305 anijain2305 commented Apr 17, 2020

Winograd Conv2D on integer tensors lead to bad accuracy. I think this is due to underlying maths that needs floating point multiplication or high precision computation. Enabling it only for FP32 tensors.

@masahi @FrozenGene @zhen-jia @u99127

Without winograd, the TOP 5 labels for few images with class 0 label is

1 [  0 389 391 758 394]
2 [390 394  48 103   0]
3 [  0 389 241 240  28]
4 [133 124 132 131 554]
5 [  0 389 390 939 391]
6 [  0 389  37 997 241]
7 [  0 758 389 391 696]
8 [  0 389 838 930 393]
9 [  0 389   1 395 758]
10 [  0 391 758 389 921]
11 [  0 389   1 391 395]
12 [  0 241 955 944 240]
13 [  0 389   5 393  57]
14 [758 391 346 268 395]
15 [  0 389   1 838 393]
16 [  0 389 241 838  28]
17 [  0 389   1 395  37]

With winograd, the TOP 5 labels for few images with class 0 label is

1 [904 818 828 556 648]
2 [904 632 482 270 556]
3 [904 556 270 632 650]
4 [904 828 650 556 383]
5 [904 632 270 556 482]
6 [904 650 828 556 270]
7 [904 818 650 270 249]
8 [904 632 818  60 482]
9 [904 632 828 556 270]
10 [904 818 556 650 270]
11 [904 632 482 556 270]
12 [904 828 632 482 270]
13 [904 632 818 270 556]
14 [904 828 650 818 556]
15 [904 632 482  60 818]

Essentially, accuracy goes down to 0%

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masahi commented Apr 17, 2020

Do you have concrete data? Say accuracy difference on imagenet with and without winograd.

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Output is all zero. It is not doing the right compute anymore, so it 0% accuracy.

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@masahi
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masahi commented Apr 18, 2020

I will take a look at how MKLDNN does winograd on int8.

I also wonder if weight quantization is working correctly. Since transformed weight shape is not in (OC, OI, KH, KW) format, maybe per channel quantize is broken if winograd is not taken into acount.

UPDATE: Since weight quantization happens before winograd transform, it is not a problem.

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Thanks for sharing the pointers @masahi
That makes sense. It also explains why accuracy is bad in master. We do not cast back to FP32.

Maybe we can handle that in a separate PR.

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masahi commented Apr 18, 2020

If the only missing bits is the cast to fp32, I hope our perf result is still valid...

# check if winograd algorithm is applicable
_, _, kh, kw = get_const_tuple(kernel.shape)
pt, pl, pb, pr = topi.nn.get_pad_tuple(padding, (kh, kw))
if kh == 3 and kw == 3 and stride_h == 1 and stride_w == 1 and \
dilation_h == 1 and dilation_w == 1:
is_dtype_fp32 = data.dtype == "float32" and kernel.dtype == "float32"
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Float16 Too ? (perhaps double aka float64 too)
I get good results with it (e.g yolov3-tiny on mali).
Wouldn't be better to deny int8/int16/int32 ?

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It might be because of this
https://github.com/apache/incubator-tvm/blob/c936a81dab2b4b4b595d02153a6654b9d4e09cd5/topi/python/topi/nn/winograd_util.py#L83-L131

The numbers here need to FP32

degree is an integer (fits in INT8) that requests filter size (usually 3x3), it will also reflect the degree of polynomial.

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cbalint13 commented Apr 18, 2020

Thanks for sharing the pointers @masahi
That makes sense. It also explains why accuracy is bad in master. We do not cast back to FP32.

Maybe we can handle that in a separate PR.

Casting into FP is just a workaround.
Winograd on INT is doable but is tricky.
One wise approach is: https://arxiv.org/abs/2003.08646

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cbalint13 commented Apr 18, 2020

Output is all zero. It is not doing the right compute anymore, so it 0% accuracy.

I think operations overflows badly (untested, its just supposition) leading to lots of 0 MUL ops.
I happens that lot of INT8 ops goes to INT8 (overflowing)

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masahi commented Apr 18, 2020

A related discussion at andravin/wincnn#16

It might be better to do weight transform before weight quantization. But given the order of Relay passes, I don't see how that can be achieved.

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tqchen commented Apr 18, 2020

We might want to do winograd transformation explicitly in relay(as opposed to implicitly in topi), that would enable quantization after the transformation.

But for this particular PR, perhaps we could go ahead and disable i8 winograd for now

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@cbalint13 @masahi PTAL again. I relaxed to have any type of floats. And also added the Top-5 labels for few images in the desciption.

@masahi masahi merged commit b39bd83 into apache:master Apr 21, 2020
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masahi commented Apr 21, 2020

Thanks @anijain2305 @cbalint13 @tqchen

We should follow up to have a proper quantized winograd for ARM and possibly for x86 too. I'm interested in this topic, but I don't have much time recently.

dpankratz pushed a commit to dpankratz/incubator-tvm that referenced this pull request Apr 24, 2020
* [Topi, ARM] Disbale Winograd for quantized tensors.

* Relaxing float
dhruvaray pushed a commit to dhruvaray/incubator-tvm that referenced this pull request Apr 28, 2020
* [Topi, ARM] Disbale Winograd for quantized tensors.

* Relaxing float
dhruvaray added a commit to dhruvaray/incubator-tvm that referenced this pull request Apr 28, 2020
* [Relay][Frontend][TFLite] Add parser support for shape and range

Signed-off-by: Dhruva Ray <dhruvaray@gmail.com>

* [RELAY][PYTORCH]isNan, isinf, isfinite, ceil, clamp, round ops (apache#5316)

* [RELAY][PYTORCH]isNan, isinf, isfinite, ceil, clamp, round ops

* Review comments

* [TIR] Refactor MakePackedAPI to target dependent stage. (apache#5326)

Previously MakePackedAPI was in the target independent stage,
but never the less requires the device_type information that will be
binded at a later target dependent stage.

The previous implementation was due to the limitation of LoweredFunc
which can not carry buffer_map info(so they have to be lowered right away).
This is no longer the case after the unified IR refactor.

This PR migrates MakePackedAPI to a target dependent stage
and removes the un-necessary BindDevice pass.

* [RELAY] Remove re-exports of tvm.transform (apache#5337)

* [LLVM] Use llvm::FunctionCallee in IRBuilder::CreateCall with LLVM 11+ (apache#5338)

The older variants of CreateCall have been deprecated and were recently
removed from LLVM. This caused compilation failures.

* [CI] Fix build.sh to propagate --network=host to the docker build command (apache#5336)

* when passing --net=host to build.sh it needs to be also
   sent as --network=host to "docker build", so that both
   build and run will use the same network configuration

* [Runtime][Relay][Cleanup] Clean up for memory pass to enable heterogenous execution support. (apache#5324)

* Cleanup type pack and unpack for tuples.

* Clean up the memory_pass using common helpers

* Clean up memory.cc

* Refactor pass

* Add doc strings

* Fix CPPlint

* Fix PyLint

* Fix

* Apply suggestions from code review

Co-Authored-By: Zhi <5145158+zhiics@users.noreply.github.com>

* Fix typo

Co-authored-by: Zhi <5145158+zhiics@users.noreply.github.com>

* Windows Support for cpp_rpc (apache#4857)

* Windows Support for cpp_rpc

* Add missing patches that fix crashes under Windows

* On Windows, use python to untar vs wsl

* remove some CMakeLists.txt stuff

* more minor CMakeLists.txt changes

* Remove items from CMakeLists.txt

* Minor CMakeLists.txt changes

* More minor CMakeLists.txt changes

* Even more minor CMakeLists.txt changes

* Modify readme

* [PYTORCH]Take, Topk op support (apache#5332)

* [PYTORCH]take, topk op support

* Ci Failure fix

* [TOPI] Using x86 schedules for ARM conv2d. (apache#5334)

* [TOPI] Improve get_valid_count and nms performance for CUDA (apache#5339)

* get_valid_count updated to have correct results

* speedup nms

* update nms

* revert back nms

* recover one test for get_valid_count

* [PYTHON] Enhance with_attr API, cleanup MakeAPILegacy in testcases (apache#5335)

* [TIR] Remove ProducerConsumer and AllocateNode::new_expr (apache#5333)

* [TIR] Remove ProducerConsumer and AllocateNode::new_expr

This PR removes two legacy IR parts in TIR that are deprecated.

ProducerConsumer node only serves as a hint markup and may no longer be
informative after extensive transformations in the pass.
If necessary, we can add related info via AttrStmt.

The new_expr field in the AllocateNode is deprecated since it can just be
replaced by a LetStmt.

- Remove dependencies of passes on ProducerConsumer.
- Remove ProducerConsumer from the IR.
- Remove the deprecated fields (new_expr, free_function) from AllocateNode.

* Fix additional testcases

* [BYOC] Prevent duplicate outputs in subgraph Tuple (apache#5320)

* Fix duplicate output in partitiongraph

* Add test case

* Fix test_annotated_regions with duplicate compiler_end outputs

* Revert "Fix duplicate output in partitiongraph"

This reverts commit e1f8ef3.

* Prevent duplicate outputs in Tuple in PartitionGraph

* Fix lint

* Add another test case for when regions are merged, and when TupleGetItem was duplicated

* Pull GetFunctionOutput out of branch, improve description of GetFunctionOutput

* Use std::move for GetFunctionOutput. Fix typo with testcase name

* Use tvm.transform.Sequential

* [Tutorial, QNN] Add tutorial for loading quantized PyTorch model (apache#5321)

* add pytorch tutorial code and doc stub

* add more docs

* formatting, more docs

* typo fix

* try make sphinx happy

* add performance section

* type and nit fix

* format fix

* [DOCS] Bring relay docs to the top-level flat view (apache#5343)

- Changes most of the relay docs to use autosummary.
- Bring relay API docs to the top-level flat view for easier discovery
- Removed a few cases of re-exports.

* [TOPI][PYTORCH]Logical & Bitwise operator support (apache#5341)

* [RELAY][BYOC] Register pattern tables from external codegens (apache#5262)

* [RELAY][BYOC] Register pattern tables from external codegens

This adds utility functions to support registering
and retrieving pattern tables used by MergeComposite for
external codegens.

Change-Id: I5be165a321440e48b15ff6aff4970e0c67496aaa

* Updated DNNL tests to use pattern table mechanism

* Removed pattern table standalone test

* Change reg to _op

* [RUNTIME][CRT] support DLTensor whose ndim == 0 (apache#5344)

Signed-off-by: windclarion <windclarion@gmail.com>

* [BYOC][FIX] Fix typo in "default" (apache#5348)

Default annotations were incorrectly being named 'defualt'
which results in them not being removed in PartitionGraph.

* enable tsim and fsim for GPU build (apache#5352)

* [CRT]Compilation warnings fixed for 32bit and 64bit compilation (apache#5349)

* [PYTORCH]Tensor creation ops support (apache#5347)

* [Hexagon] Add hexagon_posix.cc to TVM/RT sources in the right place (apache#5346)

This file was added before the variable with TVM/RT was initialized.
The initialization overwrote the addition.

* [TOPI-ARM] Do not alter layout if layout is NHWC (apache#5350)

* [TOPI-ARM] Do not alter layout if layout is NHWC

* Add test.

* [TIR] Make lower_warp_memory support extent(threadIdx.x) < warp_size (apache#5307)

* support extent(threadIdx.x) < warp_size in lower_warp_memory

* more docs for lower_warp_memory

* [RELAY][PYTORCH]GroupNorm op support added (apache#5358)

* docker: Drop caffe2 download progess bars (apache#5359)

Change-Id: Ia15c3c8f41f75423814e559f6fdb062098f19464

* fix fuse over functions that are handled by external codegen (apache#5365)

* [RUNTIME] FastRPC interface for Hexagon runtime (apache#5353)

* [RUNTIME] FastRPC interface for Hexagon runtime

Co-authored-by: Ravishankar Kolachana <quic_rkolacha@quicinc.com>
Co-authored-by: Krzysztof Parzyszek <kparzysz@quicinc.com>

* Explain store offset in a comment in launcher

Co-authored-by: Abhikrant Sharma <quic_abhikran@quicinc.com>
Co-authored-by: Ravishankar Kolachana <quic_rkolacha@quicinc.com>

* [TIR][REFACTOR] Migrate low-level passes in tvm.lower to the Unified IR pass manager. (apache#5364)

- Migrate BoundCheckers and Simplify
- Migrate RewriteUnsafeSelect and RemoveNoOp
- Migrate UnrollLoop and StorageRewrite
- Migrate InjectDoubleBuffer and InjectVirtualThread
- Migrate LoopPartition and Vectorize
- Migrate CoProcSync, LiftAttrScope, InjectCopyIntrin

We still keep ir_pass registerations for now.
Need a separate PR to refactor the parts before the StorageFlatten.

* [TIR] Fix lower_warp_memory when there are >1 warp buffers (apache#5368)

* fix recursion in lower_warp_memory

* post-order mutation

* Add cuda target check to dense tensorcore schedule. (apache#5376)

* Remove developer facing api from frontend exports. (apache#5375)

* [TIR][REFACTOR] Remove te::Tensor dependencies from TIR passes. (apache#5372)

* [TIR][REFACTOR] Remove te::Tensor dependencies from TIR passes.

te::Tensor is an useful object for tensor expression, but brings
un-necessary reverse dependency in TIR nodes such as Provide and Realize.

This PR is a first step to remove this dependency. We will use Buffer in all the places
where the te::Tensor was used. The rough correspondence are:

- Provide -> BufferStore
- Realize -> BufferRealize
- HalideCall -> BufferLoad.

After this change, we can not use IRModule of PrimFuncs cleanly to represent TIR
at any point of the optimizations. Buffer will serve as the abstraction for the TIR data
models to represent the intermediate storages and their constraints.

We still keep Realize/HalideCall and Provide as TIR nodes for now to make the change minimum.
Right after ScheduleOps, we call SchedulePostProcToPrimFunc to canonicalize the temporary IR
generated by TE(which contains these nodes) to the TIR.

The TIR optimizations are now mostly migrated to to the pass manager.
Followup PRs are needed to migrate the remaining few passes.

* Fix dev tutorial

* [PYTORCH]Unary Ops (apache#5378)

* [TIR][REFACTOR] RewriteForTensorCore -> te/schedule (apache#5379)

* [TIR][REFACTIR] RewriteForTensorCore -> te/schedule

RewriteForTensor depends on the schedule information, which makes it differ
from a typical pass(which should get all the information from the input TIR).

As a result, we refactor it as a SchedulePostProc step for now.
We should revisit it later as we introduce more support for tensor core patterns in the TIR.

* Fix VTA to fit the new IR Pattern

* [Blocksparse] Pipeline for lowering dense model to sparse-dense (apache#5377)

* [REFACTOR][TE] Inline -> te/schedule/operation_inline.h (apache#5386)

Rationale: inline is a transformation used in te to
rewrite its internal expressions. It is not a formal IRModule->IRModule transform pass.

Also removed the python test as the test is covered by stage.compute_inline.

* [ARITH] Remove the legacy Simplify, migrate to Analyzer. (apache#5385)

The legacy Simplify/CanonicalSimplify are now a thin wrapper around the Analyzer.
This PR removes these functions and migrated every place that requires
simplification to enforce Analyzer creation.
The new API would encourage more Analyzer sharing and potentially enable
context-aware analyzer-based simplification.

* [ARITH] Remove legacy const pattern functions (apache#5387)

* Add ability to have multiple copies of same input to onnx_inputs. (apache#5389)

* [Topi, ARM] Disbale Winograd for quantized tensors. (apache#5363)

* [Topi, ARM] Disbale Winograd for quantized tensors.

* Relaxing float

* Fix test_ir_type. (apache#5390)

* The void return type is not None/nullptr, it's VoidType or
   TupleType([]).

* Tf2 test fixups (apache#5391)

* Fix oversight in importing tf.compat.v1 as tf.

* Actually disable test for lstm in TF2.1

Since the testing framework actually uses pytest, the version
check needs to be moved.

* [PTYTHON] Migrate VTA TIR passes to the new pass manager. (apache#5397)

* [LLVM] Use ArrayRef<int> in calls to CreateShuffleVector (apache#5399)

This switch was made in LLVM 11. Previously this function was expecting
mask indices of type uint32_t. This variant is now deprecated.

* [KERAS]Minimum & AlphaDropout op support (apache#5380)

* Factor out import of common tflite.Operator in tflite frontend. (apache#5355)

* Restructure imports in tflite frontend.

These python modules are needed for every tflite file parsed.
Factorize out imports of the common most ones.

Now that the import of operator is common, asserts can be commonized.

Loses 473 lines of duplication.

* Only restrict to tflite.Operator

* [Fix] Remove the duplicate PrintIR pass in Relay (apache#5403)

* Update dmlc-core to latest (apache#5401)

* [TIR] Enhance Substitute, python bindings for Substitute/PostOrderVisit/IRTransform. (apache#5400)

Substitute now takes a std::function to customize more replacing behaviors.

Co-authored-by: Siyuan Feng <hzfengsy@sjtu.edu.cn>

Co-authored-by: Siyuan Feng <hzfengsy@sjtu.edu.cn>

* [Relay] Fix memory leak when accessing NDArray (apache#5413)

* Customize SI prefix in logging (apache#5411)

* Customize SI prefix in logging

* Include unit test

* [LLVM] Replace calls to Type::getVectorNumElements (apache#5398)

This function has recently been removed from LLVM 11. Use alternative
way to obtain vector element count (VectorType::getNumElements) which
works for all LLVM versions.

* Don't remove() TempDirectory in __del__ after atexit hook runs. (apache#5414)

* Use atexit to remove TempDirectory before interpreter shutdown.
 * Can't rely on complex functions from __del__ anyway.
 * Fixes warning message on my box:
       Exception ignored in: <function TempDirectory.__del__ at 0x12be10680>
       Traceback (most recent call last):
        File ".../tvm/python/tvm/contrib/util.py", line 55, in __del__
        File ".../tvm/python/tvm/contrib/util.py", line 51, in remove
        File "/usr/local/opt/python/Frameworks/Python.framework/Versions/3.7/lib/python3.7/shutil.py", line 509, in rmtree
        AttributeError: 'NoneType' object has no attribute 'path'

* [TIR][REFACTOR] Remove ir_pass in favor of analysis/transform. (apache#5415)

This PR removes ir_pass(old style pass functions) in favor
of analysis/transform(new style pass manager).

* [RUNTIME][CONTRIB] CoreML Runtime (apache#5283)

* [RUNTIME][CONTRIB] CoreML Runtime

* fix lint

* fix CI

* use xcrun to compile coreml model

* [DOCS] Migrate HLS documents from md to rst (apache#5419)

* fix [RUNTIME][VULKAN] vkBuffer released before memory copy command send to GPU (apache#5388) (apache#5418)

* [Frontend] Asymmetric padding of convolution support (apache#4803)

* [cuDNN] Add cuDNN grouped convolutions support (apache#5319)

Signed-off-by: Wei Pan <weip@nvidia.com>

* [CI] Migrate Tensorflow and Tensorflow lite in CI to  2.1.0 (apache#5392)

* Migrate Tensorflow and TFLite in the CI up to 1.15.2

The latest stable version of Tensorflow and Tensorflow lite
in the 1.x series is 1.15.2. The tflite frontend is receiving
support for versions of tflite > 1.14 but there is no consistent
testing.

There are 2 failures already in the source base with tf 1.15
and I'm concerned this will just get exacerbated over time
if we don't have CI picking this up and I view this as a stepping
stone towards stepping CI to TF2.x.

The test failures that I have commented will get issues raised
for them as issues to be fixed.

* Comment out run of qnn_mobilenet_v3_net

This is another test that fails with TFlite 1.15.2

* Skip the qnn_mobilenet_v3 test in the pytest fashion.

* Switch docker versions to support Tensorflow 2.1.0

* Fix up pytest imports and usage.

* Skip these tests currently for Tensorflow 2.1.0

* [DOCS] Migrate some markdowns to rst, fix sphinx3 warnings (apache#5416)

* [DOCS] Migrate some markdowns to rst, fix sphinx3 warnings

* Add note block

* [BYOC] Use Non-Recursive Visitor/Mutator (apache#5410)

* Non-Recursive AnnotatedTarget and MergeAnnotation

* Non-Recursive AnnotatedRegionSet and RegionMerger

* [RFC] Pytest environment improvements (apache#5421)

* [RFC] Pass pytest options globally.

In many places having a global pytest flag is useful . For me with the
build and test of tvm , I would like to be able to globally pass in
pytest options as part of development flow or CI flows where one would
like to measure other things regularly that need measurements including
pytest coverage data that I would like to experiment with across the stack.

This has been achieved with an additional setup-pytest-env.sh file in
tests/scripts rather than putting in something in every single task test
script and something I would like to avoid.

This now means the -v option to pytest is superfluous. I did consider
having a pytest.ini file but that doesn't allow me to pass any old
environment variable in and this seems to be the compromise.

* Improve other use case documentation

* Rationalize pytest environment.

* Remove the setting from docker/with_same_user.
* Take the opportunity to migrate common PYTHONPATH and
TVM_PATH into the common environment setting.

* Fixup vta fsim

* Be more explicit with common PYTHONPATH

* Fix python path for task_python_vta_fsim.sh properly

* Fix nit in documentation.

* [MXNET]DepthToSpace & SpaceToDepth Operator (apache#5408)

* Add option to specify flatbuffers location (apache#5425)

* [FRONTEND][MXNET] support elemwise logic ops (apache#5361)

* [PY][FFI] Introduce PyNativeObject, enable runtime.String to subclass str (apache#5426)

To make runtime.String to work as naturally as possible in the python side,
we make it sub-class the python's str object. Note that however, we cannot
sub-class Object at the same time due to python's type layout constraint.

We introduce a PyNativeObject class to handle this kind of object sub-classing
and updated the FFI to handle PyNativeObject classes.

* [PYTORCH]where, addcdiv, addcmul op support (apache#5383)

* [PYTORCH]Where, addcdiv, addcmul op support

* Review comments fixed

* [FRONTEND][TFLITE]Gather, StridedSlice op support added (apache#4788)

* [FRONTEND][TFLITE]Gather, StridedSlice op added

* Review comments fixed

* misc fixes for ROCm (pointer lifetime, runtime::String refactor) (apache#5431)

* Corrected TVM autotuning on GPU (apache#5432)

Added missing "tir" in tvm.tir.analysis.verify_gpu_code(f, kwargs)

* [RUNTIME][OBJECT] Introduce static slots for common objects. (apache#5423)

The _type_child_slots can be used to enable quick type checking optimization
by checking the whether the type index is within the bound.

This PR enables these static slots:

- Introduce a static assert to avoid the scenario when a developer forget to
  _type_child_slots when the field is set for the type's parent.
- Revamp and assign static type index to common runtime objects
- Add a DumpTypeTable call to allow developer monitor the current situation
  of type table and offers suggestions for the slots(ideally the slots equals
  the number of children so there is no overflow.

* [RELAY][PYTORCH]cosh,sinh,log2,log10,log1p op support (apache#5395)

* [RELAY][PYTORCH]cosh,sinh,log2,log10,log1p op support

* Review comment fixed

* Gradient testcase added

* [PYTORCH]Rsub, Embedded, OneHot ops support (apache#5434)

* fix miopen pad (apache#5433)

* [TOPI,RELAY][TFLITE] Sparse to dense operator

Signed-off-by: Dhruva Ray <dhruvaray@gmail.com>

* Add TopK to ONNX Frontend (apache#5441)

* Add TopK to ONNX Frontend

* respond to review comments

* [CodeGen] Cleanup generated code (apache#5424)

- remove unnecessary white spaces from storage kind
- do not start a new scope for vectorization as temporary
  variables are alll uniquely generated.

The above two changes make vectorized code much cleaner.

Signed-off-by: Wei Pan <weip@nvidia.com>

* [RELAY] Move frontend utils (apache#5345)

* [RELAY] Move frontend utils

The util file currently under frontend is used from
outside of frontend (in qnn/op/legalizations). This suggests
that the file should be pushed up to a higher level.

The benefit from this change is that importing qnn no longer
also imports all the frontends.

* Inline get_scalar_from_constant

Change-Id: I1cc64e9ecb0eadb6ac0f7b62e6ea174644af4ad4

* Remove util.py from Relay

Change-Id: If9cd7cf3fc0bd1861a3a9b5604f338e084d8db96

* Shorten functions

Change-Id: Ieb537d82e6ee52421ff05a90cd00a03679ffebf2

* Line length

Change-Id: I1d216b7e73a060c4f118f5da50ce58b18eba907f

* [KERAS]Embedding layer (apache#5444)

* [Docs] VTA install doc migration from md to rst (apache#5442)

* Improve IntervalSet's floormod (apache#5367)

* use param name in documentation

Signed-off-by: Dhruva Ray <dhruvaray@gmail.com>

* [ONNX]GatherNd, Round, IsNaN, IsInf (apache#5445)

* [relay][topi] Add operation relay.nn.dilate() which calls topi.nn.dilate() (apache#5331)

* Add operation relay.nn.dilate() which calls topi.nn.dilate().

* Fix typo

* Set op pattern to injective

* sphinx doc errors fixed

Signed-off-by: Dhruva Ray <dhruvaray@gmail.com>

* [Pytorch] fix translation of transpose when axis argument is as a list (apache#5451)

* incorporated code review comments

Signed-off-by: Dhruva Ray <dhruvaray@gmail.com>

* Fixed indentation

Signed-off-by: Dhruva Ray <dhruvaray@gmail.com>

Co-authored-by: Samuel <siju.samuel@huawei.com>
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trevor-m pushed a commit to trevor-m/tvm that referenced this pull request Jun 9, 2020
* [Topi, ARM] Disbale Winograd for quantized tensors.

* Relaxing float
trevor-m pushed a commit to trevor-m/tvm that referenced this pull request Jun 18, 2020
* [Topi, ARM] Disbale Winograd for quantized tensors.

* Relaxing float
trevor-m pushed a commit to neo-ai/tvm that referenced this pull request Jun 18, 2020
* [Topi, ARM] Disbale Winograd for quantized tensors.

* Relaxing float
@chrschinab
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I currently face the issue that Winograd implementation for quantized int8 operators destroys accuracy (see my topic on discuss.tvm.ai) as described above.

Is the functionality to disable Winograd for quantized operators already implemented? How to do that?

@BUG1989
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BUG1989 commented Oct 18, 2020

@masahi In our project. The int8 winograd F(2,3) has the same accuracy as original int8 conv3x3s1, please refer it.
andravin/wincnn#16 (comment)
ncnn int8 pr
naive c code

@cbalint13
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@BUG1989 ,

Thanks for the share and links ! I was aware of that work, will try to add a schedule to TVM for int8 cases.

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6 participants