-
Notifications
You must be signed in to change notification settings - Fork 1k
/
stm32_serial.c
4077 lines (3396 loc) · 114 KB
/
stm32_serial.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/****************************************************************************
* arch/arm/src/stm32h7/stm32_serial.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <unistd.h>
#include <string.h>
#include <assert.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/fs/ioctl.h>
#include <nuttx/serial/serial.h>
#include <nuttx/semaphore.h>
#include <nuttx/power/pm.h>
#ifdef CONFIG_SERIAL_TERMIOS
# include <termios.h>
#endif
#include "arm_internal.h"
#include "chip.h"
#include "stm32_gpio.h"
#include "hardware/stm32_pinmap.h"
#include "stm32_dma.h"
#include "stm32_rcc.h"
#include "stm32_uart.h"
#include <arch/board/board.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Some sanity checks *******************************************************/
/* Total number of possible serial devices */
#define STM32_NSERIAL (STM32H7_NUSART + STM32H7_NUART)
/* DMA configuration */
/* If DMA is enabled on any USART, then verify that other pre-requisites
* have also been selected.
*/
#ifdef SERIAL_HAVE_RXDMA
/* Verify that RX DMA configuration. */
# if defined(CONFIG_USART1_RXDMA)
# if !defined(DMAMAP_USART1_RX)
# error "USART1 DMA map not defined (DMAMAP_USART1_RX)"
# endif
# if DMAMAP_USART1_RX == DMAMAP_DMA12_USART1RX_0 && !defined(CONFIG_STM32H7_DMA1)
# error STM32 USART1 using DMAMAP_DMA12_USART1RX_0 for receive DMA requires CONFIG_STM32H7_DMA1
# endif
# if DMAMAP_USART1_RX == DMAMAP_DMA12_USART1RX_1 && !defined(CONFIG_STM32H7_DMA2)
# error STM32 USART1 using DMAMAP_DMA12_USART1RX_1 for receive DMA requires CONFIG_STM32H7_DMA2
# endif
# endif
# if defined(CONFIG_USART2_RXDMA)
# if !defined(DMAMAP_USART2_RX)
# error "USART2 DMA map not defined (DMAMAP_USART2_RX)"
# endif
# if DMAMAP_USART2_RX == DMAMAP_DMA12_USART2RX_0 && !defined(CONFIG_STM32H7_DMA1)
# error STM32 USART2 using DMAMAP_DMA12_USART2RX_0 for receive DMA requires CONFIG_STM32H7_DMA1
# endif
# if DMAMAP_USART2_RX == DMAMAP_DMA12_USART2RX_1 && !defined(CONFIG_STM32H7_DMA2)
# error STM32 USART2 using DMAMAP_DMA12_USART2RX_1 for receive DMA requires CONFIG_STM32H7_DMA2
# endif
# endif
# if defined(CONFIG_USART3_RXDMA)
# if !defined(DMAMAP_USART3_RX)
# error "USART3 DMA map not defined (DMAMAP_USART3_RX)"
# endif
# if DMAMAP_USART3_RX == DMAMAP_DMA12_USART3RX_0 && !defined(CONFIG_STM32H7_DMA1)
# error STM32 USART3 using DMAMAP_DMA12_USART3RX_0 for receive DMA requires CONFIG_STM32H7_DMA1
# endif
# if DMAMAP_USART3_RX == DMAMAP_DMA12_USART3RX_1 && !defined(CONFIG_STM32H7_DMA2)
# error STM32 USART3 using DMAMAP_DMA12_USART3RX_1 for receive DMA requires CONFIG_STM32H7_DMA2
# endif
# endif
# if defined(CONFIG_UART4_RXDMA)
# if !defined(DMAMAP_UART4_RX)
# error "UART4 DMA map not defined (DMAMAP_UART4_RX)"
# endif
# if DMAMAP_UART4_RX == DMAMAP_DMA12_UART4RX_0 && !defined(CONFIG_STM32H7_DMA1)
# error STM32 UART4 using DMAMAP_DMA12_UART4RX_0 for receive DMA requires CONFIG_STM32H7_DMA1
# endif
# if DMAMAP_UART4_RX == DMAMAP_DMA12_UART4RX_1 && !defined(CONFIG_STM32H7_DMA2)
# error STM32 UART4 using DMAMAP_DMA12_UART4RX_1 for receive DMA requires CONFIG_STM32H7_DMA2
# endif
# endif
# if defined(CONFIG_UART5_RXDMA)
# if !defined(DMAMAP_UART5_RX)
# error "UART5 DMA map not defined (DMAMAP_UART5_RX)"
# endif
# if DMAMAP_UART5_RX == DMAMAP_DMA12_UART5RX_0 && !defined(CONFIG_STM32H7_DMA1)
# error STM32 UART5 using DMAMAP_DMA12_UART5RX_0 for receive DMA requires CONFIG_STM32H7_DMA1
# endif
# if DMAMAP_UART5_RX == DMAMAP_DMA12_UART5RX_1 && !defined(CONFIG_STM32H7_DMA2)
# error STM32 UART5 using DMAMAP_DMA12_UART5RX_1 for receive DMA requires CONFIG_STM32H7_DMA2
# endif
# endif
# if defined(CONFIG_USART6_RXDMA)
# if !defined(DMAMAP_USART6_RX)
# error "USART6 DMA map not defined (DMAMAP_USART6_RX)"
# endif
# if DMAMAP_USART6_RX == DMAMAP_DMA12_USART6RX_0 && !defined(CONFIG_STM32H7_DMA1)
# error STM32 USART6 using DMAMAP_DMA12_USART6RX_0 for receive DMA requires CONFIG_STM32H7_DMA1
# endif
# if DMAMAP_USART6_RX == DMAMAP_DMA12_USART6RX_1 && !defined(CONFIG_STM32H7_DMA2)
# error STM32 USART6 using DMAMAP_DMA12_USART6RX_1 for receive DMA requires CONFIG_STM32H7_DMA2
# endif
# endif
# if defined(CONFIG_UART7_RXDMA)
# if !defined(DMAMAP_UART7_RX)
# error "UART7 DMA map not defined (DMAMAP_UART7_RX)"
# endif
# if DMAMAP_UART7_RX == DMAMAP_DMA12_UART7RX_0 && !defined(CONFIG_STM32H7_DMA1)
# error STM32 UART7 using DMAMAP_DMA12_UART7RX_0 for receive DMA requires CONFIG_STM32H7_DMA1
# endif
# if DMAMAP_UART7_RX == DMAMAP_DMA12_UART7RX_1 && !defined(CONFIG_STM32H7_DMA2)
# error STM32 UART7 using DMAMAP_DMA12_UART7RX_1 for receive DMA requires CONFIG_STM32H7_DMA2
# endif
# endif
# if defined(CONFIG_UART8_RXDMA)
# if !defined(DMAMAP_UART8_RX)
# error "UART8 DMA map not defined (DMAMAP_UART8_RX)"
# endif
# if DMAMAP_UART8_RX == DMAMAP_DMA12_UART8RX_0 && !defined(CONFIG_STM32H7_DMA1)
# error STM32 UART8 using DMAMAP_DMA12_UART8RX_0 for receive DMA requires CONFIG_STM32H7_DMA1
# endif
# if DMAMAP_UART8_RX == DMAMAP_DMA12_UART8RX_1 && !defined(CONFIG_STM32H7_DMA2)
# error STM32 UART8 using DMAMAP_DMA12_UART8RX_1 for receive DMA requires CONFIG_STM32H7_DMA2
# endif
# endif
/* Currently RS-485 support cannot be enabled when RXDMA is in use due to
* lack of testing - RS-485 support was developed on STM32F1x
*/
# if (defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_RS485)) || \
(defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_RS485)) || \
(defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_RS485)) || \
(defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_RS485)) || \
(defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_RS485)) || \
(defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_RS485)) || \
(defined(CONFIG_UART7_RXDMA) && defined(CONFIG_UART7_RS485)) || \
(defined(CONFIG_UART8_RXDMA) && defined(CONFIG_UART8_RS485))
# error "RXDMA and RS-485 cannot be enabled at the same time for the same U[S]ART"
# endif
/* The DMA buffer size when using RX DMA to emulate a FIFO.
*
* When streaming data, the generic serial layer will be called every time
* the FIFO receives half this number of bytes.
*
* This buffer size should be an even multiple of the Cortex-M7 D-Cache line
* size, ARMV7M_DCACHE_LINESIZE, so that it can be individually invalidated.
*
* Should there be a Cortex-M7 without a D-Cache, ARMV7M_DCACHE_LINESIZE
* would be zero!
*/
# if !defined(ARMV7M_DCACHE_LINESIZE) || ARMV7M_DCACHE_LINESIZE == 0
# undef ARMV7M_DCACHE_LINESIZE
# define ARMV7M_DCACHE_LINESIZE 32
# endif
# if !defined(CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE) || \
(CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE < ARMV7M_DCACHE_LINESIZE)
# undef CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE
# define CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE ARMV7M_DCACHE_LINESIZE
# endif
# define RXDMA_BUFFER_MASK (ARMV7M_DCACHE_LINESIZE - 1)
# define RXDMA_BUFFER_SIZE ((CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE \
+ RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK)
/* DMA priority */
# ifndef CONFIG_USART_RXDMAPRIO
# define CONFIG_USART_RXDMAPRIO DMA_SCR_PRIMED
# endif
# if (CONFIG_USART_RXDMAPRIO & ~DMA_SCR_PL_MASK) != 0
# error "Illegal value for CONFIG_USART_RXDMAPRIO"
# endif
/* DMA control words */
# define SERIAL_RXDMA_CONTROL_WORD \
(DMA_SCR_DIR_P2M | \
DMA_SCR_CIRC | \
DMA_SCR_MINC | \
DMA_SCR_PSIZE_8BITS | \
DMA_SCR_MSIZE_8BITS | \
CONFIG_USART_RXDMAPRIO | \
DMA_SCR_PBURST_SINGLE | \
DMA_SCR_MBURST_SINGLE)
#endif /* SERIAL_HAVE_RXDMA */
#ifdef SERIAL_HAVE_TXDMA
/* Verify that TX DMA configuration. */
# if defined(CONFIG_USART1_TXDMA)
# if !defined(DMAMAP_USART1_TX)
# error "USART1 DMA map not defined (DMAMAP_USART1_TX)"
# endif
# if DMAMAP_USART1_TX == DMAMAP_DMA12_USART1TX_0 && !defined(CONFIG_STM32H7_DMA1)
# error STM32 USART1 using DMAMAP_DMA12_USART1TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1
# endif
# if DMAMAP_USART1_TX == DMAMAP_DMA12_USART1TX_1 && !defined(CONFIG_STM32H7_DMA2)
# error STM32 USART1 using DMAMAP_DMA12_USART1TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2
# endif
# endif
# if defined(CONFIG_USART2_TXDMA)
# if !defined(DMAMAP_USART2_TX)
# error "USART2 DMA map not defined (DMAMAP_USART2_TX)"
# endif
# if DMAMAP_USART2_TX == DMAMAP_DMA12_USART2TX_0 && !defined(CONFIG_STM32H7_DMA1)
# error STM32 USART2 using DMAMAP_DMA12_USART2TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1
# endif
# if DMAMAP_USART2_TX == DMAMAP_DMA12_USART2TX_1 && !defined(CONFIG_STM32H7_DMA2)
# error STM32 USART2 using DMAMAP_DMA12_USART2TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2
# endif
# endif
# if defined(CONFIG_USART3_TXDMA)
# if !defined(DMAMAP_USART3_TX)
# error "USART3 DMA map not defined (DMAMAP_USART3_TX)"
# endif
# if DMAMAP_USART3_TX == DMAMAP_DMA12_USART3TX_0 && !defined(CONFIG_STM32H7_DMA1)
# error STM32 USART3 using DMAMAP_DMA12_USART3TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1
# endif
# if DMAMAP_USART3_TX == DMAMAP_DMA12_USART3TX_1 && !defined(CONFIG_STM32H7_DMA2)
# error STM32 USART3 using DMAMAP_DMA12_USART3TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2
# endif
# endif
# if defined(CONFIG_UART4_TXDMA)
# if !defined(DMAMAP_UART4_TX)
# error "UART4 DMA map not defined (DMAMAP_UART4_TX)"
# endif
# if DMAMAP_UART4_TX == DMAMAP_DMA12_UART4TX_0 && !defined(CONFIG_STM32H7_DMA1)
# error STM32 UART4 using DMAMAP_DMA12_UART4TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1
# endif
# if DMAMAP_UART4_TX == DMAMAP_DMA12_UART4TX_1 && !defined(CONFIG_STM32H7_DMA2)
# error STM32 UART4 using DMAMAP_DMA12_UART4TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2
# endif
# endif
# if defined(CONFIG_UART5_TXDMA)
# if !defined(DMAMAP_UART5_TX)
# error "UART5 DMA map not defined (DMAMAP_UART5_TX)"
# endif
# if DMAMAP_UART5_TX == DMAMAP_DMA12_UART5TX_0 && !defined(CONFIG_STM32H7_DMA1)
# error STM32 UART5 using DMAMAP_DMA12_UART5TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1
# endif
# if DMAMAP_UART5_TX == DMAMAP_DMA12_UART5TX_1 && !defined(CONFIG_STM32H7_DMA2)
# error STM32 UART5 using DMAMAP_DMA12_UART5TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2
# endif
# endif
# if defined(CONFIG_USART6_TXDMA)
# if !defined(DMAMAP_USART6_TX)
# error "USART6 DMA map not defined (DMAMAP_USART6_TX)"
# endif
# if DMAMAP_USART6_TX == DMAMAP_DMA12_USART6TX_0 && !defined(CONFIG_STM32H7_DMA1)
# error STM32 USART6 using DMAMAP_DMA12_USART6TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1
# endif
# if DMAMAP_USART6_TX == DMAMAP_DMA12_USART6TX_1 && !defined(CONFIG_STM32H7_DMA2)
# error STM32 USART6 using DMAMAP_DMA12_USART6TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2
# endif
# endif
# if defined(CONFIG_UART7_TXDMA)
# if !defined(DMAMAP_UART7_TX)
# error "UART7 DMA map not defined (DMAMAP_UART7_TX)"
# endif
# if DMAMAP_UART7_TX == DMAMAP_DMA12_UART7TX_0 && !defined(CONFIG_STM32H7_DMA1)
# error STM32 UART7 using DMAMAP_DMA12_UART7TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1
# endif
# if DMAMAP_UART7_TX == DMAMAP_DMA12_UART7TX_1 && !defined(CONFIG_STM32H7_DMA2)
# error STM32 UART7 using DMAMAP_DMA12_UART7TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2
# endif
# endif
# if defined(CONFIG_UART8_TXDMA)
# if !defined(DMAMAP_UART8_TX)
# error "UART8 DMA map not defined (DMAMAP_UART8_TX)"
# endif
# if DMAMAP_UART8_TX == DMAMAP_DMA12_UART8TX_0 && !defined(CONFIG_STM32H7_DMA1)
# error STM32 UART8 using DMAMAP_DMA12_UART8TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1
# endif
# if DMAMAP_UART8_TX == DMAMAP_DMA12_UART8TX_1 && !defined(CONFIG_STM32H7_DMA2)
# error STM32 UART8 using DMAMAP_DMA12_UART8TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2
# endif
# endif
#endif
/* Currently RS-485 support cannot be enabled when TXDMA is in use due to
* lack of testing - RS-485 support was developed on STM32F1x
*/
#if (defined(CONFIG_USART1_TXDMA) && defined(CONFIG_USART1_RS485)) || \
(defined(CONFIG_USART2_TXDMA) && defined(CONFIG_USART2_RS485)) || \
(defined(CONFIG_USART3_TXDMA) && defined(CONFIG_USART3_RS485)) || \
(defined(CONFIG_UART4_TXDMA) && defined(CONFIG_UART4_RS485)) || \
(defined(CONFIG_UART5_TXDMA) && defined(CONFIG_UART5_RS485)) || \
(defined(CONFIG_USART6_TXDMA) && defined(CONFIG_USART6_RS485)) || \
(defined(CONFIG_UART7_TXDMA) && defined(CONFIG_UART7_RS485)) || \
(defined(CONFIG_UART8_TXDMA) && defined(CONFIG_UART8_RS485))
# error "TXDMA and RS-485 cannot be enabled at the same time for the same U[S]ART"
#endif
/* The DMA buffer size when using TX DMA.
*
* This TX buffer size should be an even multiple of the Cortex-M7 D-Cache
* line size, ARMV7M_DCACHE_LINESIZE, so that it can be individually
* invalidated.
*
* Should there be a Cortex-M7 without a D-Cache, ARMV7M_DCACHE_LINESIZE
* would be zero!
*/
#if !defined(ARMV7M_DCACHE_LINESIZE) || ARMV7M_DCACHE_LINESIZE == 0
# undef ARMV7M_DCACHE_LINESIZE
# define ARMV7M_DCACHE_LINESIZE 32
#endif
#define TXDMA_BUFFER_MASK (ARMV7M_DCACHE_LINESIZE - 1)
#define TXDMA_BUFFER_SIZE ((CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE \
+ RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK)
/* If built with CONFIG_ARMV7M_DCACHE Buffers need to be aligned and
* multiples of ARMV7M_DCACHE_LINESIZE
*/
#if defined(CONFIG_ARMV7M_DCACHE)
# define TXDMA_BUF_SIZE(b) (((b) + TXDMA_BUFFER_MASK) & ~TXDMA_BUFFER_MASK)
# define TXDMA_BUF_ALIGN aligned_data(ARMV7M_DCACHE_LINESIZE)
#else
# define TXDMA_BUF_SIZE(b) (b)
# define TXDMA_BUF_ALIGN
#endif
#if !defined(CONFIG_USART1_TXDMA)
# define USART1_TXBUFSIZE_ADJUSTED CONFIG_USART1_TXBUFSIZE
# define USART1_TXBUFSIZE_ALGN
#else
# define USART1_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_USART1_TXBUFSIZE)
# define USART1_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN
#endif
#if !defined(CONFIG_USART2_TXDMA)
# define USART2_TXBUFSIZE_ADJUSTED CONFIG_USART2_TXBUFSIZE
# define USART2_TXBUFSIZE_ALGN
#else
# define USART2_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_USART2_TXBUFSIZE)
# define USART2_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN
#endif
#if !defined(CONFIG_USART3_TXDMA)
# define USART3_TXBUFSIZE_ADJUSTED CONFIG_USART3_TXBUFSIZE
# define USART3_TXBUFSIZE_ALGN
#else
# define USART3_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_USART3_TXBUFSIZE)
# define USART3_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN
#endif
#if !defined(CONFIG_UART4_TXDMA)
# define UART4_TXBUFSIZE_ADJUSTED CONFIG_UART4_TXBUFSIZE
# define UART4_TXBUFSIZE_ALGN
#else
# define UART4_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_UART4_TXBUFSIZE)
# define UART4_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN
#endif
#if !defined(CONFIG_UART5_TXDMA)
# define UART5_TXBUFSIZE_ADJUSTED CONFIG_UART5_TXBUFSIZE
# define UART5_TXBUFSIZE_ALGN
#else
# define UART5_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_UART5_TXBUFSIZE)
# define UART5_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN
#endif
#if !defined(CONFIG_USART6_TXDMA)
# define USART6_TXBUFSIZE_ADJUSTED CONFIG_USART6_TXBUFSIZE
# define USART6_TXBUFSIZE_ALGN
#else
# define USART6_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_USART6_TXBUFSIZE)
# define USART6_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN
#endif
#if !defined(CONFIG_UART7_TXDMA)
# define UART7_TXBUFSIZE_ADJUSTED CONFIG_UART7_TXBUFSIZE
# define UART7_TXBUFSIZE_ALGN
#else
# define UART7_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_UART7_TXBUFSIZE)
# define UART7_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN
#endif
#if !defined(CONFIG_UART8_TXDMA)
# define UART8_TXBUFSIZE_ADJUSTED CONFIG_UART8_TXBUFSIZE
# define UART8_TXBUFSIZE_ALGN
#else
# define UART8_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_UART8_TXBUFSIZE)
# define UART8_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN
#endif
#ifdef SERIAL_HAVE_TXDMA
/* DMA priority */
# ifndef CONFIG_USART_TXDMAPRIO
# define CONFIG_USART_TXDMAPRIO DMA_SCR_PRIMED
# endif
# if (CONFIG_USART_TXDMAPRIO & ~DMA_SCR_PL_MASK) != 0
# error "Illegal value for CONFIG_USART_TXDMAPRIO"
# endif
# define SERIAL_TXDMA_CONTROL_WORD \
(DMA_SCR_DIR_M2P | \
DMA_SCR_MINC | \
DMA_SCR_PSIZE_8BITS | \
DMA_SCR_MSIZE_8BITS | \
DMA_SCR_PBURST_SINGLE | \
DMA_SCR_MBURST_SINGLE | \
CONFIG_USART_TXDMAPRIO | \
DMA_SCR_TRBUFF)
#endif /* SERIAL_HAVE_TXDMA */
/* Power management definitions */
#if defined(CONFIG_PM) && !defined(CONFIG_STM32H7_PM_SERIAL_ACTIVITY)
# define CONFIG_STM32H7_PM_SERIAL_ACTIVITY 10
#endif
#if defined(CONFIG_PM)
# warning stm32h7 serial power managemnt was taken from stm32f7 and is untested!
#endif
/* Since RX DMA or TX DMA or both may be enabled for a given U[S]ART.
* We need runtime detection in up_dma_setup and up_dma_shutdown
* We use the default struct default init value of 0 which does not map
* to a valid DMA MAPS.
*/
#define INVALID_SERIAL_DMA_CHANNEL 0
/* Keep track if a Break was set
*
* Note:
*
* 1) This value is set in the priv->ie but never written to the control
* register. It must not collide with USART_CR1_USED_INTS or USART_CR3_EIE
* 2) USART_CR3_EIE is also carried in the up_dev_s ie member.
*
* See up_restoreusartint where the masking is done.
*/
#ifdef CONFIG_STM32H7_SERIALBRK_BSDCOMPAT
# define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15
# define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS)
#endif
#ifdef USE_SERIALDRIVER
#ifdef HAVE_UART
/* Warnings for potentially unsafe configuration combinations. */
#if defined(CONFIG_STM32H7_FLOWCONTROL_BROKEN) && \
!defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS)
# error "CONFIG_STM32H7_FLOWCONTROL_BROKEN requires \
CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS to be enabled."
#endif
#ifndef CONFIG_STM32H7_FLOWCONTROL_BROKEN
/* Combination of RXDMA + IFLOWCONTROL does not work as one might expect.
* Since RXDMA uses circular DMA-buffer, DMA will always keep reading new
* data from USART peripheral even if DMA buffer underruns. Thus this
* combination only does following: RTS is asserted on USART setup and
* deasserted on shutdown and does not perform actual RTS flow-control.
*
* With SW flow-control, RTS is asserted before UART receive buffer fully
* fills, thus preventing data loss if application is slow to process data
* from serial device node. However, if RxDMA interrupt is blocked for too
* long, data loss is still possible as SW flow-control would also be
* blocked.
*/
# if defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_IFLOWCONTROL)
# warning "RXDMA and IFLOWCONTROL both enabled for USART1. \
This combination can lead to data loss."
# endif
# if defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_IFLOWCONTROL)
# warning "RXDMA and IFLOWCONTROL both enabled for USART2. \
This combination can lead to data loss."
# endif
# if defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_IFLOWCONTROL)
# warning "RXDMA and IFLOWCONTROL both enabled for USART3. \
This combination can lead to data loss."
# endif
# if defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_IFLOWCONTROL)
# warning "RXDMA and IFLOWCONTROL both enabled for USART6. \
This combination can lead to data loss."
# endif
# if defined(CONFIG_UART7_RXDMA) && defined(CONFIG_UART7_IFLOWCONTROL)
# warning "RXDMA and IFLOWCONTROL both enabled for UART7. \
This combination can lead to data loss."
# endif
# if defined(CONFIG_UART8_RXDMA) && defined(CONFIG_UART8_IFLOWCONTROL)
# warning "RXDMA and IFLOWCONTROL both enabled for UART8. \
This combination can lead to data loss."
# endif
#endif /* CONFIG_STM32H7_FLOWCONTROL_BROKEN */
/****************************************************************************
* Private Types
****************************************************************************/
struct up_dev_s
{
struct uart_dev_s dev; /* Generic UART device */
uint16_t ie; /* Saved interrupt mask bits value */
uint16_t sr; /* Saved status bits */
/* Has been initialized and HW is setup. */
bool initialized;
#ifdef CONFIG_PM
bool suspended; /* UART device has been suspended. */
/* Interrupt mask value stored before suspending for stop mode. */
uint16_t suspended_ie;
#endif
/* If termios are supported, then the following fields may vary at
* runtime.
*/
#ifdef CONFIG_SERIAL_TERMIOS
uint8_t rxftcfg; /* Rx FIFO threshold level */
uint8_t parity; /* 0=none, 1=odd, 2=even */
uint8_t bits; /* Number of bits (7 or 8) */
bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */
#ifdef CONFIG_SERIAL_IFLOWCONTROL
bool iflow; /* input flow control (RTS) enabled */
#endif
#ifdef CONFIG_SERIAL_OFLOWCONTROL
bool oflow; /* output flow control (CTS) enabled */
#endif
uint32_t baud; /* Configured baud */
#else
const uint8_t rxftcfg; /* Rx FIFO threshold level */
const uint8_t parity; /* 0=none, 1=odd, 2=even */
const uint8_t bits; /* Number of bits (7 or 8) */
const bool stopbits2; /* True: Configure with 2 stop bits instead of 1 */
#ifdef CONFIG_SERIAL_IFLOWCONTROL
const bool iflow; /* input flow control (RTS) enabled */
#endif
#ifdef CONFIG_SERIAL_OFLOWCONTROL
const bool oflow; /* output flow control (CTS) enabled */
#endif
const uint32_t baud; /* Configured baud */
#endif
const uint8_t irq; /* IRQ associated with this USART */
const uint32_t apbclock; /* PCLK 1 or 2 frequency */
const uint32_t usartbase; /* Base address of USART registers */
const uint32_t tx_gpio; /* U[S]ART TX GPIO pin configuration */
const uint32_t rx_gpio; /* U[S]ART RX GPIO pin configuration */
#ifdef CONFIG_SERIAL_IFLOWCONTROL
const uint32_t rts_gpio; /* U[S]ART RTS GPIO pin configuration */
#endif
#ifdef CONFIG_SERIAL_OFLOWCONTROL
const uint32_t cts_gpio; /* U[S]ART CTS GPIO pin configuration */
#endif
/* TX DMA state */
#ifdef SERIAL_HAVE_TXDMA
const unsigned int txdma_channel; /* DMA channel assigned */
DMA_HANDLE txdma; /* currently-open trasnmit DMA stream */
sem_t txdmasem; /* Indicate TX DMA completion */
#endif
/* RX DMA state */
#ifdef SERIAL_HAVE_RXDMA
const unsigned int rxdma_channel; /* DMA channel assigned */
DMA_HANDLE rxdma; /* currently-open receive DMA stream */
bool rxenable; /* DMA-based reception en/disable */
#ifdef CONFIG_PM
bool rxdmasusp; /* Rx DMA suspended */
#endif
uint32_t rxdmanext; /* Next byte in the DMA buffer to be read */
#ifdef CONFIG_ARMV7M_DCACHE
uint32_t rxdmaavail; /* Number of bytes available without need to
* to invalidate the data cache */
#endif
char *const rxfifo; /* Receive DMA buffer */
#endif
#ifdef HAVE_RS485
const uint32_t rs485_dir_gpio; /* U[S]ART RS-485 DIR GPIO pin configuration */
const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for TX enabled */
#endif
};
#ifdef CONFIG_PM
struct pm_config_s
{
struct pm_callback_s pm_cb;
bool serial_suspended;
};
#endif
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static void up_set_format(struct uart_dev_s *dev);
static int up_setup(struct uart_dev_s *dev);
static void up_shutdown(struct uart_dev_s *dev);
static int up_attach(struct uart_dev_s *dev);
static void up_detach(struct uart_dev_s *dev);
static int up_interrupt(int irq, void *context, void *arg);
static int up_ioctl(struct file *filep, int cmd, unsigned long arg);
#if defined(SERIAL_HAVE_TXDMA_OPS) || defined(SERIAL_HAVE_NODMA_OPS)
static int up_receive(struct uart_dev_s *dev, unsigned int *status);
static void up_rxint(struct uart_dev_s *dev, bool enable);
static bool up_rxavailable(struct uart_dev_s *dev);
#endif
#ifdef CONFIG_SERIAL_IFLOWCONTROL
static bool up_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered,
bool upper);
#endif
static void up_send(struct uart_dev_s *dev, int ch);
#ifndef SERIAL_HAVE_ONLY_TXDMA
static void up_txint(struct uart_dev_s *dev, bool enable);
#endif
static bool up_txready(struct uart_dev_s *dev);
#ifdef SERIAL_HAVE_TXDMA
static void up_dma_send(struct uart_dev_s *dev);
static void up_dma_txint(struct uart_dev_s *dev, bool enable);
static void up_dma_txavailable(struct uart_dev_s *dev);
static void up_dma_txcallback(DMA_HANDLE handle, uint8_t status, void *arg);
#endif
#if defined(SERIAL_HAVE_RXDMA) || defined(SERIAL_HAVE_TXDMA)
static int up_dma_setup(struct uart_dev_s *dev);
static void up_dma_shutdown(struct uart_dev_s *dev);
#endif
#ifdef SERIAL_HAVE_RXDMA
static int up_dma_receive(struct uart_dev_s *dev, unsigned int *status);
#ifdef CONFIG_PM
static void up_dma_reenable(struct up_dev_s *priv);
#endif
static void up_dma_rxint(struct uart_dev_s *dev, bool enable);
static bool up_dma_rxavailable(struct uart_dev_s *dev);
static void up_dma_rxcallback(DMA_HANDLE handle, uint8_t status, void *arg);
#endif
#ifdef CONFIG_PM
static void up_setsuspend(struct uart_dev_s *dev, bool suspend);
static void up_pm_setsuspend(bool suspend);
static void up_pm_notify(struct pm_callback_s *cb, int domain,
enum pm_state_e pmstate);
static int up_pm_prepare(struct pm_callback_s *cb, int domain,
enum pm_state_e pmstate);
#endif
/****************************************************************************
* Private Data
****************************************************************************/
#ifdef SERIAL_HAVE_NODMA_OPS
static const struct uart_ops_s g_uart_ops =
{
.setup = up_setup,
.shutdown = up_shutdown,
.attach = up_attach,
.detach = up_detach,
.ioctl = up_ioctl,
.receive = up_receive,
.rxint = up_rxint,
.rxavailable = up_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = up_rxflowcontrol,
#endif
.send = up_send,
.txint = up_txint,
.txready = up_txready,
.txempty = up_txready,
};
#endif
#ifdef SERIAL_HAVE_RXTXDMA_OPS
static const struct uart_ops_s g_uart_rxtxdma_ops =
{
.setup = up_dma_setup,
.shutdown = up_dma_shutdown,
.attach = up_attach,
.detach = up_detach,
.ioctl = up_ioctl,
.receive = up_dma_receive,
.rxint = up_dma_rxint,
.rxavailable = up_dma_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = up_rxflowcontrol,
#endif
.send = up_send,
.txint = up_dma_txint,
.txready = up_txready,
.txempty = up_txready,
.dmatxavail = up_dma_txavailable,
.dmasend = up_dma_send,
};
#endif
#ifdef SERIAL_HAVE_RXDMA_OPS
static const struct uart_ops_s g_uart_rxdma_ops =
{
.setup = up_dma_setup,
.shutdown = up_dma_shutdown,
.attach = up_attach,
.detach = up_detach,
.ioctl = up_ioctl,
.receive = up_dma_receive,
.rxint = up_dma_rxint,
.rxavailable = up_dma_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = up_rxflowcontrol,
#endif
.send = up_send,
.txint = up_txint,
.txready = up_txready,
.txempty = up_txready,
};
#endif
#ifdef SERIAL_HAVE_TXDMA_OPS
static const struct uart_ops_s g_uart_txdma_ops =
{
.setup = up_dma_setup,
.shutdown = up_dma_shutdown,
.attach = up_attach,
.detach = up_detach,
.ioctl = up_ioctl,
.receive = up_receive,
.rxint = up_rxint,
.rxavailable = up_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = up_rxflowcontrol,
#endif
.send = up_send,
.txint = up_dma_txint,
.txready = up_txready,
.txempty = up_txready,
.dmatxavail = up_dma_txavailable,
.dmasend = up_dma_send,
};
#endif
/* DMA buffers. RX DMA buffers must:
*
* 1. Be a multiple of the D-Cache line size. This requirement is assured
* by the definition of RXDMA buffer size above.
* 2. Be aligned a D-Cache line boundaries, and
* 3. Be positioned in DMA-able memory.
*
* These DMA buffers are defined sequentially here to best assure optimal
* packing of the buffers.
*/
#ifdef CONFIG_USART1_RXDMA
static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]
aligned_data(ARMV7M_DCACHE_LINESIZE);
#endif
# ifdef CONFIG_USART2_RXDMA
static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]
aligned_data(ARMV7M_DCACHE_LINESIZE);
#endif
#ifdef CONFIG_USART3_RXDMA
static char g_usart3rxfifo[RXDMA_BUFFER_SIZE]
aligned_data(ARMV7M_DCACHE_LINESIZE);
#endif
#ifdef CONFIG_UART4_RXDMA
static char g_uart4rxfifo[RXDMA_BUFFER_SIZE]
aligned_data(ARMV7M_DCACHE_LINESIZE);
#endif
#ifdef CONFIG_UART5_RXDMA
static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]
aligned_data(ARMV7M_DCACHE_LINESIZE);
#endif
#ifdef CONFIG_USART6_RXDMA
static char g_usart6rxfifo[RXDMA_BUFFER_SIZE]
aligned_data(ARMV7M_DCACHE_LINESIZE);
#endif
#ifdef CONFIG_UART7_RXDMA
static char g_uart7rxfifo[RXDMA_BUFFER_SIZE]
aligned_data(ARMV7M_DCACHE_LINESIZE);
#endif
#ifdef CONFIG_UART8_RXDMA
static char g_uart8rxfifo[RXDMA_BUFFER_SIZE]
aligned_data(ARMV7M_DCACHE_LINESIZE);
#endif
/* Receive/Transmit buffers */
#ifdef CONFIG_STM32H7_USART1
static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE];
static char g_usart1txbuffer[USART1_TXBUFSIZE_ADJUSTED] \
USART1_TXBUFSIZE_ALGN;
#endif
#ifdef CONFIG_STM32H7_USART2
static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE];
static char g_usart2txbuffer[USART2_TXBUFSIZE_ADJUSTED] \
USART2_TXBUFSIZE_ALGN;
#endif
#ifdef CONFIG_STM32H7_USART3
static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE];
static char g_usart3txbuffer[USART3_TXBUFSIZE_ADJUSTED] \
USART3_TXBUFSIZE_ALGN;
#endif
#ifdef CONFIG_STM32H7_UART4
static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE];
static char g_uart4txbuffer[UART4_TXBUFSIZE_ADJUSTED] \
UART4_TXBUFSIZE_ALGN;
#endif
#ifdef CONFIG_STM32H7_UART5
static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE];
static char g_uart5txbuffer[UART5_TXBUFSIZE_ADJUSTED] \
UART5_TXBUFSIZE_ALGN;
#endif
#ifdef CONFIG_STM32H7_USART6
static char g_usart6rxbuffer[CONFIG_USART6_RXBUFSIZE];
static char g_usart6txbuffer[USART6_TXBUFSIZE_ADJUSTED] \
USART6_TXBUFSIZE_ALGN;
#endif
#ifdef CONFIG_STM32H7_UART7
static char g_uart7rxbuffer[CONFIG_UART7_RXBUFSIZE];
static char g_uart7txbuffer[UART7_TXBUFSIZE_ADJUSTED] \
UART7_TXBUFSIZE_ALGN;
#endif
#ifdef CONFIG_STM32H7_UART8
static char g_uart8rxbuffer[CONFIG_UART8_RXBUFSIZE];
static char g_uart8txbuffer[UART8_TXBUFSIZE_ADJUSTED] \
UART8_TXBUFSIZE_ALGN;
#endif
/* This describes the state of the STM32 USART1 ports. */
#ifdef CONFIG_STM32H7_USART1
static struct up_dev_s g_usart1priv =
{
.dev =
{
#if CONSOLE_UART == 1
.isconsole = true,
#endif
.recv =
{
.size = sizeof(g_usart1rxbuffer),
.buffer = g_usart1rxbuffer,
},
.xmit =
{
.size = sizeof(g_usart1txbuffer),
.buffer = g_usart1txbuffer,
},
#if defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_TXDMA)
.ops = &g_uart_rxtxdma_ops,
#elif defined(CONFIG_USART1_RXDMA) && !defined(CONFIG_USART1_TXDMA)
.ops = &g_uart_rxdma_ops,
#elif !defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_TXDMA)
.ops = &g_uart_txdma_ops,
#else
.ops = &g_uart_ops,
#endif
.priv = &g_usart1priv,
},
.irq = STM32_IRQ_USART1,
.rxftcfg = CONFIG_USART1_RXFIFO_THRES,
.parity = CONFIG_USART1_PARITY,
.bits = CONFIG_USART1_BITS,
.stopbits2 = CONFIG_USART1_2STOP,
.baud = CONFIG_USART1_BAUD,
.apbclock = STM32_PCLK2_FREQUENCY,
.usartbase = STM32_USART1_BASE,
.tx_gpio = GPIO_USART1_TX,
.rx_gpio = GPIO_USART1_RX,
#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL)
.oflow = true,
.cts_gpio = GPIO_USART1_CTS,
#endif
#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL)
.iflow = true,
.rts_gpio = GPIO_USART1_RTS,
#endif
#ifdef CONFIG_USART1_TXDMA
.txdma_channel = DMAMAP_USART1_TX,
.txdmasem = SEM_INITIALIZER(1),
#endif
#ifdef CONFIG_USART1_RXDMA
.rxdma_channel = DMAMAP_USART1_RX,
.rxfifo = g_usart1rxfifo,
#endif
#ifdef CONFIG_USART1_RS485
.rs485_dir_gpio = GPIO_USART1_RS485_DIR,
# if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
.rs485_dir_polarity = false,
# else
.rs485_dir_polarity = true,
# endif
#endif
};
#endif
/* This describes the state of the STM32 USART2 port. */
#ifdef CONFIG_STM32H7_USART2
static struct up_dev_s g_usart2priv =
{
.dev =
{
#if CONSOLE_UART == 2
.isconsole = true,
#endif
.recv =
{
.size = sizeof(g_usart2rxbuffer),
.buffer = g_usart2rxbuffer,
},