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imxrt_serial.c
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imxrt_serial.c
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/****************************************************************************
* arch/arm/src/imxrt/imxrt_serial.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <unistd.h>
#include <string.h>
#include <assert.h>
#include <errno.h>
#include <debug.h>
#ifdef CONFIG_SERIAL_TERMIOS
# include <termios.h>
#endif
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/spinlock.h>
#include <nuttx/init.h>
#include <nuttx/power/pm.h>
#include <nuttx/fs/ioctl.h>
#include <nuttx/serial/serial.h>
#include <arch/board/board.h>
#include "chip.h"
#include "arm_internal.h"
#include "hardware/imxrt_lpuart.h"
#include "imxrt_gpio.h"
#include "imxrt_edma.h"
#include "hardware/imxrt_dmamux.h"
#include "hardware/imxrt_pinmux.h"
#include "imxrt_config.h"
#include "imxrt_lowputc.h"
#include "imxrt_serial.h"
#ifdef USE_SERIALDRIVER
/* Alias IOMUX_PULL_{UP|DOWN} to IOMUX V1 */
#if defined(IOMUX_PULL_UP_47K)
#define IOMUX_PULL_UP IOMUX_PULL_UP_47K
#endif
#if defined(IOMUX_PULL_DOWN_100K)
#define IOMUX_PULL_DOWN IOMUX_PULL_DOWN_100K
#endif
/* The DMA buffer size when using RX DMA to emulate a FIFO.
*
* When streaming data, the generic serial layer will be called every time
* the FIFO receives half this number of bytes.
*
* This buffer size should be an even multiple of the Cortex-M7 D-Cache line
* size, ARMV7M_DCACHE_LINESIZE, so that it can be individually invalidated.
*
* Should there be a Cortex-M7 without a D-Cache, ARMV7M_DCACHE_LINESIZE
* would be zero!
*/
# if !defined(ARMV7M_DCACHE_LINESIZE) || ARMV7M_DCACHE_LINESIZE == 0
# undef ARMV7M_DCACHE_LINESIZE
# define ARMV7M_DCACHE_LINESIZE 32
# endif
# if !defined(CONFIG_IMXRT_SERIAL_RXDMA_BUFFER_SIZE) || \
(CONFIG_IMXRT_SERIAL_RXDMA_BUFFER_SIZE < ARMV7M_DCACHE_LINESIZE)
# undef CONFIG_IMXRT_SERIAL_RXDMA_BUFFER_SIZE
# define CONFIG_IMXRT_SERIAL_RXDMA_BUFFER_SIZE ARMV7M_DCACHE_LINESIZE
# endif
# define RXDMA_BUFFER_MASK (ARMV7M_DCACHE_LINESIZE - 1)
# define RXDMA_BUFFER_SIZE ((CONFIG_IMXRT_SERIAL_RXDMA_BUFFER_SIZE \
+ RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK)
/* The DMA buffer size when using TX DMA.
*
* This TX buffer size should be an even multiple of the Cortex-M7 D-Cache
* line size, ARMV7M_DCACHE_LINESIZE, so that it can be individually
* invalidated.
*
* Should there be a Cortex-M7 without a D-Cache, ARMV7M_DCACHE_LINESIZE
* would be zero!
*/
#if !defined(ARMV7M_DCACHE_LINESIZE) || ARMV7M_DCACHE_LINESIZE == 0
# undef ARMV7M_DCACHE_LINESIZE
# define ARMV7M_DCACHE_LINESIZE 32
#endif
#define TXDMA_BUFFER_MASK (ARMV7M_DCACHE_LINESIZE - 1)
#define TXDMA_BUFFER_SIZE ((CONFIG_IMXRT_SERIAL_RXDMA_BUFFER_SIZE \
+ RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK)
/* If built with CONFIG_ARMV7M_DCACHE Buffers need to be aligned and
* multiples of ARMV7M_DCACHE_LINESIZE
*/
#if defined(CONFIG_ARMV7M_DCACHE)
# define TXDMA_BUF_SIZE(b) (((b) + TXDMA_BUFFER_MASK) & ~TXDMA_BUFFER_MASK)
# define TXDMA_BUF_ALIGN aligned_data(ARMV7M_DCACHE_LINESIZE);
#else
# define TXDMA_BUF_SIZE(b) (b)
# define TXDMA_BUF_ALIGN
#endif
#if !defined(CONFIG_LPUART1_TXDMA)
# define LPUART1_TXBUFSIZE_ADJUSTED CONFIG_LPUART1_TXBUFSIZE
# define LPUART1_TXBUFSIZE_ALGN
#else
# define LPUART1_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART1_TXBUFSIZE)
# define LPUART1_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN
#endif
#if !defined(CONFIG_LPUART2_TXDMA)
# define LPUART2_TXBUFSIZE_ADJUSTED CONFIG_LPUART2_TXBUFSIZE
# define LPUART2_TXBUFSIZE_ALGN
#else
# define LPUART2_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART2_TXBUFSIZE)
# define LPUART2_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN
#endif
#if !defined(CONFIG_LPUART3_TXDMA)
# define LPUART3_TXBUFSIZE_ADJUSTED CONFIG_LPUART3_TXBUFSIZE
# define LPUART3_TXBUFSIZE_ALGN
#else
# define LPUART3_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART3_TXBUFSIZE)
# define LPUART3_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN
#endif
#if !defined(CONFIG_LPUART4_TXDMA)
# define LPUART4_TXBUFSIZE_ADJUSTED CONFIG_LPUART4_TXBUFSIZE
# define LPUART4_TXBUFSIZE_ALGN
#else
# define LPUART4_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART4_TXBUFSIZE)
# define LPUART4_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN
#endif
#if !defined(CONFIG_LPUART5_TXDMA)
# define LPUART5_TXBUFSIZE_ADJUSTED CONFIG_LPUART5_TXBUFSIZE
# define LPUART5_TXBUFSIZE_ALGN
#else
# define LPUART5_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART5_TXBUFSIZE)
# define LPUART5_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN
#endif
#if !defined(CONFIG_LPUART6_TXDMA)
# define LPUART6_TXBUFSIZE_ADJUSTED CONFIG_LPUART6_TXBUFSIZE
# define LPUART6_TXBUFSIZE_ALGN
#else
# define LPUART6_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART6_TXBUFSIZE)
# define LPUART6_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN
#endif
#if !defined(CONFIG_LPUART7_TXDMA)
# define LPUART7_TXBUFSIZE_ADJUSTED CONFIG_LPUART7_TXBUFSIZE
# define LPUART7_TXBUFSIZE_ALGN
#else
# define LPUART7_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART7_TXBUFSIZE)
# define LPUART7_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN
#endif
#if !defined(CONFIG_LPUART8_TXDMA)
# define LPUART8_TXBUFSIZE_ADJUSTED CONFIG_LPUART8_TXBUFSIZE
# define LPUART8_TXBUFSIZE_ALGN
#else
# define LPUART8_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART8_TXBUFSIZE)
# define LPUART8_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN
#endif
#if !defined(CONFIG_LPUART9_TXDMA)
# define LPUART9_TXBUFSIZE_ADJUSTED CONFIG_LPUART9_TXBUFSIZE
# define LPUART9_TXBUFSIZE_ALGN
#else
# define LPUART9_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART9_TXBUFSIZE)
# define LPUART9_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN
#endif
#if !defined(CONFIG_LPUART10_TXDMA)
# define LPUART10_TXBUFSIZE_ADJUSTED CONFIG_LPUART10_TXBUFSIZE
# define LPUART10_TXBUFSIZE_ALGN
#else
# define LPUART10_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART10_TXBUFSIZE)
# define LPUART10_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN
#endif
#if !defined(CONFIG_LPUART11_TXDMA)
# define LPUART11_TXBUFSIZE_ADJUSTED CONFIG_LPUART11_TXBUFSIZE
# define LPUART11_TXBUFSIZE_ALGN
#else
# define LPUART11_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART11_TXBUFSIZE)
# define LPUART11_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN
#endif
#if !defined(CONFIG_LPUART12_TXDMA)
# define LPUART12_TXBUFSIZE_ADJUSTED CONFIG_LPUART12_TXBUFSIZE
# define LPUART12_TXBUFSIZE_ALGN
#else
# define LPUART12_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART12_TXBUFSIZE)
# define LPUART12_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN
#endif
/* Which LPUART with be tty0/console and which tty1-7? The console will
* always be ttyS0. If there is no console then will use the lowest
* numbered UART.
*/
/* First pick the console and ttys0. This could be any of LPUART1-8 */
#if defined(CONFIG_LPUART1_SERIAL_CONSOLE)
# define CONSOLE_DEV g_lpuart1priv /* LPUART1 is console */
# define TTYS0_DEV g_lpuart1priv /* LPUART1 is ttyS0 */
# define LPUART1_ASSIGNED 1
# if defined(CONFIG_LPUART1_RXDMA)
# define SERIAL_HAVE_CONSOLE_RXDMA 1
# endif
# if defined(CONFIG_LPUART1_TXDMA)
# define SERIAL_HAVE_CONSOLE_TXDMA 1
# endif
#elif defined(CONFIG_LPUART2_SERIAL_CONSOLE)
# define CONSOLE_DEV g_lpuart2priv /* LPUART2 is console */
# define TTYS0_DEV g_lpuart2priv /* LPUART2 is ttyS0 */
# define LPUART2_ASSIGNED 1
# if defined(CONFIG_LPUART2_RXDMA)
# define SERIAL_HAVE_CONSOLE_RXDMA 1
# endif
# if defined(CONFIG_LPUART2_TXDMA)
# define SERIAL_HAVE_CONSOLE_TXDMA 1
# endif
#elif defined(CONFIG_LPUART3_SERIAL_CONSOLE)
# define CONSOLE_DEV g_lpuart3priv /* LPUART3 is console */
# define TTYS0_DEV g_lpuart3priv /* LPUART3 is ttyS0 */
# define LPUART3_ASSIGNED 1
# if defined(CONFIG_LPUART3_RXDMA)
# define SERIAL_HAVE_CONSOLE_RXDMA 1
# endif
# if defined(CONFIG_LPUART3_TXDMA)
# define SERIAL_HAVE_CONSOLE_TXDMA 1
# endif
#elif defined(CONFIG_LPUART4_SERIAL_CONSOLE)
# define CONSOLE_DEV g_lpuart4priv /* LPUART4 is console */
# define TTYS0_DEV g_lpuart4priv /* LPUART4 is ttyS0 */
# define LPUART4_ASSIGNED 1
# if defined(CONFIG_LPUART4_RXDMA)
# define SERIAL_HAVE_CONSOLE_RXDMA 1
# endif
# if defined(CONFIG_LPUART4_TXDMA)
# define SERIAL_HAVE_CONSOLE_TXDMA 1
# endif
#elif defined(CONFIG_LPUART5_SERIAL_CONSOLE)
# define CONSOLE_DEV g_lpuart5priv /* LPUART5 is console */
# define TTYS0_DEV g_lpuart5priv /* LPUART5 is ttyS0 */
# define LPUART5_ASSIGNED 1
# if defined(CONFIG_LPUART5_RXDMA)
# define SERIAL_HAVE_CONSOLE_RXDMA 1
# endif
# if defined(CONFIG_LPUART5_TXDMA)
# define SERIAL_HAVE_CONSOLE_TXDMA 1
# endif
#elif defined(CONFIG_LPUART6_SERIAL_CONSOLE)
# define CONSOLE_DEV g_lpuart6priv /* LPUART6 is console */
# define TTYS0_DEV g_lpuart6priv /* LPUART6 is ttyS0 */
# define LPUART6_ASSIGNED 1
# if defined(CONFIG_LPUART6_RXDMA)
# define SERIAL_HAVE_CONSOLE_RXDMA 1
# endif
# if defined(CONFIG_LPUART6_TXDMA)
# define SERIAL_HAVE_CONSOLE_TXDMA 1
# endif
#elif defined(CONFIG_LPUART7_SERIAL_CONSOLE)
# define CONSOLE_DEV g_lpuart7priv /* LPUART7 is console */
# define TTYS0_DEV g_lpuart7priv /* LPUART7 is ttyS0 */
# define LPUART7_ASSIGNED 1
# if defined(CONFIG_LPUART7_RXDMA)
# define SERIAL_HAVE_CONSOLE_RXDMA 1
# endif
# if defined(CONFIG_LPUART7_TXDMA)
# define SERIAL_HAVE_CONSOLE_TXDMA 1
# endif
#elif defined(CONFIG_LPUART8_SERIAL_CONSOLE)
# define CONSOLE_DEV g_lpuart8priv /* LPUART8 is console */
# define TTYS0_DEV g_lpuart8priv /* LPUART8 is ttyS0 */
# define LPUART8_ASSIGNED 1
# if defined(CONFIG_LPUART8_RXDMA)
# define SERIAL_HAVE_CONSOLE_RXDMA 1
# endif
# if defined(CONFIG_LPUART9_TXDMA)
# define SERIAL_HAVE_CONSOLE_TXDMA 1
# endif
#elif defined(CONFIG_LPUART9_SERIAL_CONSOLE)
# define CONSOLE_DEV g_lpuart9priv /* LPUART9 is console */
# define TTYS0_DEV g_lpuart9priv /* LPUART9 is ttyS0 */
# define LPUART9_ASSIGNED 1
# if defined(CONFIG_LPUART9_RXDMA)
# define SERIAL_HAVE_CONSOLE_RXDMA 1
# endif
# if defined(CONFIG_LPUART9_TXDMA)
# define SERIAL_HAVE_CONSOLE_TXDMA 1
# endif
#elif defined(CONFIG_LPUART10_SERIAL_CONSOLE)
# define CONSOLE_DEV g_lpuart10priv /* LPUART10 is console */
# define TTYS0_DEV g_lpuart10priv /* LPUART10 is ttyS0 */
# define LPUART10_ASSIGNED 1
# if defined(CONFIG_LPUART10_RXDMA)
# define SERIAL_HAVE_CONSOLE_RXDMA 1
# endif
# if defined(CONFIG_LPUART10_TXDMA)
# define SERIAL_HAVE_CONSOLE_TXDMA 1
# endif
#elif defined(CONFIG_LPUART11_SERIAL_CONSOLE)
# define CONSOLE_DEV g_lpuart11priv /* LPUART11 is console */
# define TTYS0_DEV g_lpuart11priv /* LPUART11 is ttyS0 */
# define LPUART11_ASSIGNED 1
# if defined(CONFIG_LPUART11_RXDMA)
# define SERIAL_HAVE_CONSOLE_RXDMA 1
# endif
# if defined(CONFIG_LPUART11_TXDMA)
# define SERIAL_HAVE_CONSOLE_TXDMA 1
# endif
#elif defined(CONFIG_LPUART12_SERIAL_CONSOLE)
# define CONSOLE_DEV g_lpuart12priv /* LPUART12 is console */
# define TTYS0_DEV g_lpuart12priv /* LPUART12 is ttyS0 */
# define LPUART12_ASSIGNED 1
# if defined(CONFIG_LPUART12_RXDMA)
# define SERIAL_HAVE_CONSOLE_RXDMA 1
# endif
# if defined(CONFIG_LPUART12_TXDMA)
# define SERIAL_HAVE_CONSOLE_TXDMA 1
# endif
#else
# undef CONSOLE_DEV /* No console */
# if defined(CONFIG_IMXRT_LPUART1)
# define TTYS0_DEV g_lpuart1priv /* LPUART1 is ttyS0 */
# define UART1_ASSIGNED 1
# elif defined(CONFIG_IMXRT_LPUART2)
# define TTYS0_DEV g_lpuart2priv /* LPUART2 is ttyS0 */
# define UART2_ASSIGNED 1
# elif defined(CONFIG_IMXRT_LPUART3)
# define TTYS0_DEV g_lpuart3priv /* LPUART3 is ttyS0 */
# define UART3_ASSIGNED 1
# elif defined(CONFIG_IMXRT_LPUART4)
# define TTYS0_DEV g_lpuart4priv /* LPUART4 is ttyS0 */
# define UART4_ASSIGNED 1
# elif defined(CONFIG_IMXRT_LPUART5)
# define TTYS0_DEV g_lpuart5priv /* LPUART5 is ttyS0 */
# define UART5_ASSIGNED 1
# elif defined(CONFIG_IMXRT_LPUART6)
# define TTYS0_DEV g_lpuart6priv /* LPUART6 is ttyS0 */
# define UART6_ASSIGNED 1
# elif defined(CONFIG_IMXRT_LPUART7)
# define TTYS0_DEV g_lpuart7priv /* LPUART7 is ttyS0 */
# define UART7_ASSIGNED 1
# elif defined(CONFIG_IMXRT_LPUART8)
# define TTYS0_DEV g_lpuart8priv /* LPUART8 is ttyS0 */
# define UART8_ASSIGNED 1
# elif defined(CONFIG_IMXRT_LPUART9)
# define TTYS0_DEV g_lpuart9priv /* LPUART9 is ttyS0 */
# define LPUART9_ASSIGNED 1
# elif defined(CONFIG_IMXRT_LPUART10)
# define TTYS0_DEV g_lpuart10priv /* LPUART10 is ttyS0 */
# define LPUART10_ASSIGNED 1
# elif defined(CONFIG_IMXRT_LPUART11)
# define TTYS0_DEV g_lpuart11priv /* LPUART11 is ttyS0 */
# define LPUART11_ASSIGNED 1
# elif defined(CONFIG_IMXRT_LPUART12)
# define TTYS0_DEV g_lpuart12priv /* LPUART12 is ttyS0 */
# define LPUART12_ASSIGNED 1
# endif
#endif
#if defined(SERIAL_HAVE_CONSOLE_RXDMA) || defined(SERIAL_HAVE_CONSOLE_TXDMA)
# define SERIAL_HAVE_CONSOLE_DMA
#endif
/* Pick ttys1. This could be any of UART1-12 excluding the console UART.
* One of UART1-12 could be the console; one of UART1-12 has already been
* assigned to ttys0.
*/
#if defined(CONFIG_IMXRT_LPUART1) && !defined(LPUART1_ASSIGNED)
# define TTYS1_DEV g_lpuart1priv /* LPUART1 is ttyS1 */
# define LPUART1_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART2) && !defined(LPUART2_ASSIGNED)
# define TTYS1_DEV g_lpuart2priv /* LPUART2 is ttyS1 */
# define LPUART2_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART3) && !defined(LPUART3_ASSIGNED)
# define TTYS1_DEV g_lpuart3priv /* LPUART3 is ttyS1 */
# define LPUART3_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART4) && !defined(LPUART4_ASSIGNED)
# define TTYS1_DEV g_lpuart4priv /* LPUART4 is ttyS1 */
# define LPUART4_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART5) && !defined(LPUART5_ASSIGNED)
# define TTYS1_DEV g_lpuart5priv /* LPUART5 is ttyS1 */
# define LPUART5_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART6) && !defined(LPUART6_ASSIGNED)
# define TTYS1_DEV g_lpuart6priv /* LPUART6 is ttyS1 */
# define LPUART6_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART7) && !defined(LPUART7_ASSIGNED)
# define TTYS1_DEV g_lpuart7priv /* LPUART7 is ttyS1 */
# define LPUART7_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART8) && !defined(LPUART8_ASSIGNED)
# define TTYS1_DEV g_lpuart8priv /* LPUART8 is ttyS1 */
# define LPUART8_ASSIGNED 11
#elif defined(CONFIG_IMXRT_LPUART9) && !defined(LPUART9_ASSIGNED)
# define TTYS1_DEV g_lpuart9priv /* LPUART9 is ttyS1 */
# define LPUART9_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART10) && !defined(LPUART10_ASSIGNED)
# define TTYS1_DEV g_lpuart10priv /* LPUART10 is ttyS1 */
# define LPUART10_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART11) && !defined(LPUART11_ASSIGNED)
# define TTYS1_DEV g_lpuart11priv /* LPUART11 is ttyS1 */
# define LPUART11_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART12) && !defined(LPUART12_ASSIGNED)
# define TTYS1_DEV g_lpuart12priv /* LPUART12 is ttyS1 */
# define LPUART12_ASSIGNED 1
#endif
/* Pick ttys2. This could be one of UART2-12. It can't be UART1 because that
* was either assigned as ttyS0 or ttys1. One of UART 1-12 could be the
* console. One of UART2-12 has already been assigned to ttys0 or ttyS1.
*/
#if defined(CONFIG_IMXRT_LPUART2) && !defined(LPUART2_ASSIGNED)
# define TTYS2_DEV g_lpuart2priv /* LPUART2 is ttyS2 */
# define LPUART2_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART3) && !defined(LPUART3_ASSIGNED)
# define TTYS2_DEV g_lpuart3priv /* LPUART3 is ttyS2 */
# define LPUART3_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART4) && !defined(LPUART4_ASSIGNED)
# define TTYS2_DEV g_lpuart4priv /* LPUART4 is ttyS2 */
# define LPUART4_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART5) && !defined(LPUART5_ASSIGNED)
# define TTYS2_DEV g_lpuart5priv /* LPUART5 is ttyS2 */
# define LPUART5_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART6) && !defined(LPUART6_ASSIGNED)
# define TTYS2_DEV g_lpuart6priv /* LPUART6 is ttyS2 */
# define LPUART6_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART7) && !defined(LPUART7_ASSIGNED)
# define TTYS2_DEV g_lpuart7priv /* LPUART7 is ttyS2 */
# define LPUART7_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART8) && !defined(LPUART8_ASSIGNED)
# define TTYS2_DEV g_lpuart8priv /* LPUART8 is ttyS2 */
# define LPUART8_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART9) && !defined(LPUART9_ASSIGNED)
# define TTYS2_DEV g_lpuart9priv /* LPUART9 is ttyS2 */
# define LPUART9_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART10) && !defined(LPUART10_ASSIGNED)
# define TTYS2_DEV g_lpuart10priv /* LPUART10 is ttyS2 */
# define LPUART10_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART11) && !defined(LPUART11_ASSIGNED)
# define TTYS2_DEV g_lpuart11priv /* LPUART11 is ttyS2 */
# define LPUART11_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART12) && !defined(LPUART12_ASSIGNED)
# define TTYS2_DEV g_lpuart12priv /* LPUART12 is ttyS2 */
# define LPUART12_ASSIGNED 1
#endif
/* Pick ttys3. This could be one of UART3-12. It can't be UART1-2 because
* those have already been assigned to ttsyS0, 1, or 2. One of
* UART3-12 could also be the console. One of UART3-12 has already
* been assigned to ttys0, 1, or 3.
*/
#if defined(CONFIG_IMXRT_LPUART3) && !defined(LPUART3_ASSIGNED)
# define TTYS3_DEV g_lpuart3priv /* LPUART3 is ttyS3 */
# define LPUART3_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART4) && !defined(LPUART4_ASSIGNED)
# define TTYS3_DEV g_lpuart4priv /* LPUART4 is ttyS3 */
# define LPUART4_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART5) && !defined(LPUART5_ASSIGNED)
# define TTYS3_DEV g_lpuart5priv /* LPUART5 is ttyS3 */
# define LPUART5_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART6) && !defined(LPUART6_ASSIGNED)
# define TTYS3_DEV g_lpuart6priv /* LPUART6 is ttyS3 */
# define LPUART6_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART7) && !defined(LPUART7_ASSIGNED)
# define TTYS3_DEV g_lpuart7priv /* LPUART7 is ttyS3 */
# define LPUART7_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART8) && !defined(LPUART8_ASSIGNED)
# define TTYS3_DEV g_lpuart8priv /* LPUART8 is ttyS3 */
# define LPUART8_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART9) && !defined(LPUART9_ASSIGNED)
# define TTYS3_DEV g_lpuart9priv /* LPUART9 is ttyS3 */
# define LPUART9_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART10) && !defined(LPUART10_ASSIGNED)
# define TTYS3_DEV g_lpuart10priv /* LPUART10 is ttyS3 */
# define LPUART10_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART11) && !defined(LPUART11_ASSIGNED)
# define TTYS3_DEV g_lpuart11priv /* LPUART11 is ttyS3 */
# define LPUART11_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART12) && !defined(LPUART12_ASSIGNED)
# define TTYS3_DEV g_lpuart12priv /* LPUART12 is ttyS3 */
# define LPUART12_ASSIGNED 1
#endif
/* Pick ttys4. This could be one of UART4-8. It can't be UART1-3 because
* those have already been assigned to ttsyS0, 1, 2 or 3. One of
* UART 4-12 could be the console. One of UART4-12 has already been
* assigned to ttys0, 1, 3, or 4.
*/
#if defined(CONFIG_IMXRT_LPUART4) && !defined(LPUART4_ASSIGNED)
# define TTYS4_DEV g_lpuart4priv /* LPUART4 is ttyS4 */
# define LPUART4_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART5) && !defined(LPUART5_ASSIGNED)
# define TTYS4_DEV g_lpuart5priv /* LPUART5 is ttyS4 */
# define LPUART5_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART6) && !defined(LPUART6_ASSIGNED)
# define TTYS4_DEV g_lpuart6priv /* LPUART6 is ttyS4 */
# define LPUART6_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART7) && !defined(LPUART7_ASSIGNED)
# define TTYS4_DEV g_lpuart7priv /* LPUART7 is ttyS4 */
# define LPUART7_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART8) && !defined(LPUART8_ASSIGNED)
# define TTYS4_DEV g_lpuart8priv /* LPUART8 is ttyS4 */
# define LPUART8_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART9) && !defined(LPUART9_ASSIGNED)
# define TTYS4_DEV g_lpuart9priv /* LPUART9 is ttyS4 */
# define LPUART9_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART10) && !defined(LPUART10_ASSIGNED)
# define TTYS4_DEV g_lpuart10priv /* LPUART10 is ttyS4 */
# define LPUART10_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART11) && !defined(LPUART11_ASSIGNED)
# define TTYS4_DEV g_lpuart11priv /* LPUART11 is ttyS4 */
# define LPUART11_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART12) && !defined(LPUART12_ASSIGNED)
# define TTYS4_DEV g_lpuart12priv /* LPUART12 is ttyS4 */
# define LPUART12_ASSIGNED 1
#endif
/* Pick ttys5. This could be one of UART5-12. It can't be UART1-4 because
* those have already been assigned to ttsyS0, 1, 2, 3 or 4. One of
* UART 5-12 could be the console. One of UART5-12 has already been
* assigned to ttys0, 1, 2, 3, or 4.
*/
#if defined(CONFIG_IMXRT_LPUART5) && !defined(LPUART5_ASSIGNED)
# define TTYS5_DEV g_lpuart5priv /* LPUART5 is ttyS5 */
# define LPUART5_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART6) && !defined(LPUART6_ASSIGNED)
# define TTYS5_DEV g_lpuart6priv /* LPUART6 is ttyS5 */
# define LPUART6_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART7) && !defined(LPUART7_ASSIGNED)
# define TTYS5_DEV g_lpuart7priv /* LPUART7 is ttyS5 */
# define LPUART7_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART8) && !defined(LPUART8_ASSIGNED)
# define TTYS5_DEV g_lpuart8priv /* LPUART8 is ttyS5 */
# define LPUART8_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART9) && !defined(LPUART9_ASSIGNED)
# define TTYS5_DEV g_lpuart9priv /* LPUART9 is ttyS5 */
# define LPUART9_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART10) && !defined(LPUART10_ASSIGNED)
# define TTYS5_DEV g_lpuart10priv /* LPUART10 is ttyS5 */
# define LPUART10_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART11) && !defined(LPUART11_ASSIGNED)
# define TTYS5_DEV g_lpuart11priv /* LPUART11 is ttyS5 */
# define LPUART11_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART12) && !defined(LPUART12_ASSIGNED)
# define TTYS5_DEV g_lpuart12priv /* LPUART12 is ttyS5 */
# define LPUART12_ASSIGNED 1
#endif
/* Pick ttys6. This could be one of UART6-12. It can't be UART1-5 because
* those have already been assigned to ttsyS0, 1, 2, 3, 4 or 5. One of
* UART 6-12 could be the console. One of UART6-12 has already been
* assigned to ttys0, 1, 2, 3, 4 or 5.
*/
#if defined(CONFIG_IMXRT_LPUART6) && !defined(LPUART6_ASSIGNED)
# define TTYS6_DEV g_lpuart6priv /* LPUART6 is ttyS6 */
# define LPUART6_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART7) && !defined(LPUART7_ASSIGNED)
# define TTYS6_DEV g_lpuart7priv /* LPUART7 is ttyS6 */
# define LPUART7_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART8) && !defined(LPUART8_ASSIGNED)
# define TTYS6_DEV g_lpuart8priv /* LPUART8 is ttyS6 */
# define LPUART8_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART9) && !defined(LPUART9_ASSIGNED)
# define TTYS6_DEV g_lpuart9priv /* LPUART9 is ttyS6 */
# define LPUART9_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART10) && !defined(LPUART10_ASSIGNED)
# define TTYS6_DEV g_lpuart10priv /* LPUART10 is ttyS6 */
# define LPUART10_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART11) && !defined(LPUART11_ASSIGNED)
# define TTYS6_DEV g_lpuart11priv /* LPUART11 is ttyS6 */
# define LPUART11_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART12) && !defined(LPUART12_ASSIGNED)
# define TTYS6_DEV g_lpuart12priv /* LPUART12 is ttyS6 */
# define LPUART12_ASSIGNED 1
#endif
/* Pick ttys7. This could be one of UART7-12. It can't be UART1-6 because
* those have already been assigned to ttsyS0, 1, 2, 3, 4, 5 or 6. One of
* UART 7-12 could be the console. One of UART7-12 has already been
* assigned to ttys0, 1, 2, 3, 4, 5 or 6.
*/
#if defined(CONFIG_IMXRT_LPUART7) && !defined(LPUART7_ASSIGNED)
# define TTYS7_DEV g_lpuart7priv /* LPUART7 is ttyS7 */
# define LPUART7_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART8) && !defined(LPUART8_ASSIGNED)
# define TTYS7_DEV g_lpuart8port /* LPUART8 is ttyS7 */
# define LPUART8_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART9) && !defined(LPUART9_ASSIGNED)
# define TTYS7_DEV g_lpuart9priv /* LPUART9 is ttyS7 */
# define LPUART9_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART10) && !defined(LPUART10_ASSIGNED)
# define TTYS7_DEV g_lpuart10priv /* LPUART10 is ttyS7 */
# define LPUART10_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART11) && !defined(LPUART11_ASSIGNED)
# define TTYS7_DEV g_lpuart11priv /* LPUART11 is ttyS7 */
# define LPUART11_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART12) && !defined(LPUART12_ASSIGNED)
# define TTYS7_DEV g_lpuart12priv /* LPUART12 is ttyS7 */
# define LPUART12_ASSIGNED 1
#endif
/* Pick ttys8. This could be one of UART8-12. It can't be UART1-9 because
* those have already been assigned to ttsyS0, 1, 2, 3, 4, 5 or 6. One of
* UART 8-12 could be the console. One of UART8-12 has already been
* assigned to ttys0, 1, 2, 3, 4, 5, 6 or 7.
*/
#if defined(CONFIG_IMXRT_LPUART8) && !defined(LPUART8_ASSIGNED)
# define TTYS8_DEV g_lpuart8port /* LPUART8 is ttyS8 */
# define LPUART8_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART9) && !defined(LPUART9_ASSIGNED)
# define TTYS8_DEV g_lpuart9priv /* LPUART9 is ttyS8 */
# define LPUART9_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART10) && !defined(LPUART10_ASSIGNED)
# define TTYS8_DEV g_lpuart10priv /* LPUART10 is ttyS8 */
# define LPUART10_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART11) && !defined(LPUART11_ASSIGNED)
# define TTYS8_DEV g_lpuart11priv /* LPUART11 is ttyS8 */
# define LPUART11_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART12) && !defined(LPUART12_ASSIGNED)
# define TTYS8_DEV g_lpuart12priv /* LPUART12 is ttyS8 */
# define LPUART12_ASSIGNED 1
#endif
/* Pick ttys9. This could be one of UART9-12. It can't be UART1-10 because
* those have already been assigned to ttsyS0, 1, 2, 3, 4, 5, 6 or 7. One of
* UART 9-12 could be the console. One of UART9-12 has already been
* assigned to ttys0, 1, 2, 3, 4, 5, 6, 7 or 8.
*/
#if defined(CONFIG_IMXRT_LPUART9) && !defined(LPUART9_ASSIGNED)
# define TTYS9_DEV g_lpuart9priv /* LPUART9 is ttyS9 */
# define LPUART9_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART10) && !defined(LPUART10_ASSIGNED)
# define TTYS9_DEV g_lpuart10priv /* LPUART10 is ttyS9 */
# define LPUART10_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART11) && !defined(LPUART11_ASSIGNED)
# define TTYS9_DEV g_lpuart11priv /* LPUART11 is ttyS9 */
# define LPUART11_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART12) && !defined(LPUART12_ASSIGNED)
# define TTYS9_DEV g_lpuart12priv /* LPUART12 is ttyS9 */
# define LPUART12_ASSIGNED 1
#endif
/* Pick ttys10. This could be one of UART10-12. It can't be UART1-10 because
* those have already been assigned to ttsyS0, 1, 2, 3, 4, 5, 6, 7 or 8.
* One of UART 10-12 could be the console. One of UART10-12 has already been
* assigned to ttys0, 1, 2, 3, 4, 5, 6, 7, 8 or 9.
*/
#if defined(CONFIG_IMXRT_LPUART10) && !defined(LPUART10_ASSIGNED)
# define TTYS10_DEV g_lpuart10priv /* LPUART10 is ttyS10 */
# define LPUART10_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART11) && !defined(LPUART11_ASSIGNED)
# define TTYS10_DEV g_lpuart11priv /* LPUART11 is ttyS10 */
# define LPUART11_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART12) && !defined(LPUART12_ASSIGNED)
# define TTYS10_DEV g_lpuart12priv /* LPUART12 is ttyS10 */
# define LPUART12_ASSIGNED 1
#endif
/* Pick ttys11. This could be one of UART11-12. It can't be UART1-11 because
* those have already been assigned to ttsyS0, 1, 2, 3, 4, 5, 6, 7, 8 or 9.
* One of UART 11-12 could be the console. One of UART11-12 has already been
* assigned to ttys0, 1, 2, 3, 4, 5, 6, 7, 8, 9 or 10.
*/
#if defined(CONFIG_IMXRT_LPUART11) && !defined(LPUART11_ASSIGNED)
# define TTYS11_DEV g_lpuart11priv /* LPUART11 is ttyS11 */
# define LPUART11_ASSIGNED 1
#elif defined(CONFIG_IMXRT_LPUART12) && !defined(LPUART12_ASSIGNED)
# define TTYS11_DEV g_lpuart12priv /* LPUART12 is ttyS11 */
# define LPUART12_ASSIGNED 1
#endif
/* UART, if available, should have been assigned to ttyS0-7. */
/* Power management definitions */
#if defined(CONFIG_PM) && !defined(CONFIG_IMXRT_PM_SERIAL_ACTIVITY)
# define CONFIG_IMXRT_PM_SERIAL_ACTIVITY 10
#endif
/****************************************************************************
* Private Types
****************************************************************************/
struct imxrt_uart_s
{
struct uart_dev_s dev; /* Generic UART device */
uint32_t uartbase; /* Base address of UART registers */
uint32_t baud; /* Configured baud */
uint32_t ie; /* Saved enabled interrupts */
uint8_t irq; /* IRQ associated with this UART */
uint8_t parity; /* 0=none, 1=odd, 2=even */
uint8_t bits; /* Number of bits (7 or 8) */
#if defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)
uint8_t inviflow:1; /* Invert RTS sense */
const uint32_t rts_gpio; /* LPUART RTS GPIO pin configuration */
#endif
#ifdef CONFIG_SERIAL_OFLOWCONTROL
const uint32_t cts_gpio; /* LPUART CTS GPIO pin configuration */
#endif
#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
const uint32_t tx_gpio; /* TX GPIO pin configuration */
const struct uart_ops_s *prev_ops;
#endif
uint8_t stopbits2:1; /* 1: Configure with 2 stop bits vs 1 */
#ifdef CONFIG_SERIAL_IFLOWCONTROL
uint8_t iflow:1; /* input flow control (RTS) enabled */
#endif
#ifdef CONFIG_SERIAL_OFLOWCONTROL
uint8_t oflow:1; /* output flow control (CTS) enabled */
#endif
#ifdef CONFIG_SERIAL_RS485CONTROL
uint8_t rs485mode:1; /* We are in RS485 (RTS on TX) mode */
#endif
/* TX DMA state */
#ifdef SERIAL_HAVE_TXDMA
const unsigned int dma_txreqsrc; /* DMAMUX source of TX DMA request */
DMACH_HANDLE txdma; /* currently-open trasnmit DMA stream */
#endif
/* RX DMA state */
#ifdef SERIAL_HAVE_RXDMA
const unsigned int dma_rxreqsrc; /* DMAMUX source of RX DMA request */
DMACH_HANDLE rxdma; /* currently-open receive DMA stream */
bool rxenable; /* DMA-based reception en/disable */
uint32_t rxdmanext; /* Next byte in the DMA buffer to be read */
#ifdef CONFIG_ARMV7M_DCACHE
uint32_t rxdmaavail; /* Number of bytes available without need to
* to invalidate the data cache */
#endif
char *const rxfifo; /* Receive DMA buffer */
#endif
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static inline uint32_t imxrt_serialin(struct imxrt_uart_s *priv,
uint32_t offset);
static inline void imxrt_serialout(struct imxrt_uart_s *priv,
uint32_t offset, uint32_t value);
#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONSOLE_DEV)
static inline void imxrt_disableuartint(struct imxrt_uart_s *priv,
uint32_t *ie);
static inline void imxrt_restoreuartint(struct imxrt_uart_s *priv,
uint32_t ie);
#endif
static int imxrt_setup(struct uart_dev_s *dev);
static void imxrt_shutdown(struct uart_dev_s *dev);
static int imxrt_attach(struct uart_dev_s *dev);
static void imxrt_detach(struct uart_dev_s *dev);
static int imxrt_interrupt(int irq, void *context, void *arg);
static int imxrt_ioctl(struct file *filep, int cmd, unsigned long arg);
#if !defined(SERIAL_HAVE_ONLY_RXDMA)
static int imxrt_receive(struct uart_dev_s *dev, unsigned int *status);
static void imxrt_rxint(struct uart_dev_s *dev, bool enable);
static bool imxrt_rxavailable(struct uart_dev_s *dev);
#endif
#if !defined(SERIAL_HAVE_ONLY_TXDMA)
static void imxrt_txint(struct uart_dev_s *dev, bool enable);
#endif
#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
static void imxrt_singlewire_txint(struct uart_dev_s *dev, bool enable);
#endif
#ifdef CONFIG_SERIAL_IFLOWCONTROL
static bool imxrt_rxflowcontrol(struct uart_dev_s *dev,
unsigned int nbuffered, bool upper);
#endif
#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
static void imxrt_singlewire_send(struct uart_dev_s *dev, int ch);
#endif
static void imxrt_send(struct uart_dev_s *dev, int ch);
static bool imxrt_txready(struct uart_dev_s *dev);
#ifdef SERIAL_HAVE_TXDMA
static void imxrt_dma_send(struct uart_dev_s *dev);
static void imxrt_dma_txint(struct uart_dev_s *dev, bool enable);
static void imxrt_dma_txavailable(struct uart_dev_s *dev);
static void imxrt_dma_txcallback(DMACH_HANDLE handle, void *arg, bool done,
int result);
#endif
#if defined(SERIAL_HAVE_RXDMA) || defined(SERIAL_HAVE_TXDMA)
static int imxrt_dma_setup(struct uart_dev_s *dev);
static void imxrt_dma_shutdown(struct uart_dev_s *dev);
#endif
#ifdef SERIAL_HAVE_RXDMA
static int imxrt_dma_receive(struct uart_dev_s *dev, unsigned int *status);
#ifdef CONFIG_PM
static void imxrt_dma_reenable(struct imxrt_uart_s *priv);
#endif
static void imxrt_dma_rxint(struct uart_dev_s *dev, bool enable);
static bool imxrt_dma_rxavailable(struct uart_dev_s *dev);
static void imxrt_dma_rxcallback(DMACH_HANDLE handle, void *arg, bool done,
int result);
#endif
static bool imxrt_txempty(struct uart_dev_s *dev);
#ifdef CONFIG_PM
static void up_pm_notify(struct pm_callback_s *cb, int dowmin,
enum pm_state_e pmstate);
static int up_pm_prepare(struct pm_callback_s *cb, int domain,
enum pm_state_e pmstate);
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/* Serial driver UART operations */
#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE
static const struct uart_ops_s g_lpuart_singlewire_ops =
{
.setup = imxrt_setup,
.shutdown = imxrt_shutdown,
.attach = imxrt_attach,
.detach = imxrt_detach,
.ioctl = imxrt_ioctl,
.receive = imxrt_receive,
.rxint = imxrt_rxint,
.rxavailable = imxrt_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = imxrt_rxflowcontrol,
#endif
.send = imxrt_singlewire_send,
.txint = imxrt_singlewire_txint,
.txready = imxrt_txready,
.txempty = imxrt_txempty,
};
#endif
#if !defined(SERIAL_HAVE_ONLY_TXDMA) && !defined(SERIAL_HAVE_ONLY_RXDMA)
static const struct uart_ops_s g_lpuart_ops =
{
.setup = imxrt_setup,
.shutdown = imxrt_shutdown,
.attach = imxrt_attach,
.detach = imxrt_detach,
.ioctl = imxrt_ioctl,
.receive = imxrt_receive,
.rxint = imxrt_rxint,
.rxavailable = imxrt_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = imxrt_rxflowcontrol,
#endif
.send = imxrt_send,
.txint = imxrt_txint,
.txready = imxrt_txready,
.txempty = imxrt_txempty,
};
#endif
#if defined(SERIAL_HAVE_RXDMA) && defined(SERIAL_HAVE_TXDMA)
static const struct uart_ops_s g_lpuart_rxtxdma_ops =
{
.setup = imxrt_dma_setup,
.shutdown = imxrt_dma_shutdown,
.attach = imxrt_attach,
.detach = imxrt_detach,
.ioctl = imxrt_ioctl,
.receive = imxrt_dma_receive,
.rxint = imxrt_dma_rxint,
.rxavailable = imxrt_dma_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = imxrt_rxflowcontrol,
#endif
.send = imxrt_send,
.txint = imxrt_dma_txint,
.txready = imxrt_txready,
.txempty = imxrt_txempty,
.dmatxavail = imxrt_dma_txavailable,
.dmasend = imxrt_dma_send,
};
#endif
#if !defined(SERIAL_HAVE_ONLY_DMA) && defined(SERIAL_HAVE_RXDMA)
static const struct uart_ops_s g_lpuart_rxdma_ops =
{
.setup = imxrt_dma_setup,
.shutdown = imxrt_dma_shutdown,
.attach = imxrt_attach,
.detach = imxrt_detach,
.ioctl = imxrt_ioctl,
.receive = imxrt_dma_receive,
.rxint = imxrt_dma_rxint,
.rxavailable = imxrt_dma_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = imxrt_rxflowcontrol,
#endif
.send = imxrt_send,
.txint = imxrt_txint,
.txready = imxrt_txready,
.txempty = imxrt_txempty,
};
#endif
#if !defined(SERIAL_HAVE_ONLY_DMA) && defined(SERIAL_HAVE_TXDMA)
static const struct uart_ops_s g_lpuart_txdma_ops =
{
.setup = imxrt_dma_setup,
.shutdown = imxrt_dma_shutdown,
.attach = imxrt_attach,
.detach = imxrt_detach,
.ioctl = imxrt_ioctl,
.receive = imxrt_receive,
.rxint = imxrt_rxint,
.rxavailable = imxrt_rxavailable,
#ifdef CONFIG_SERIAL_IFLOWCONTROL
.rxflowcontrol = imxrt_rxflowcontrol,
#endif
.send = imxrt_send,
.txint = imxrt_dma_txint,
.txready = imxrt_txready,
.txempty = imxrt_txempty,
.dmatxavail = imxrt_dma_txavailable,
.dmasend = imxrt_dma_send,
};
#endif
/* Avoid unused warning */
#if !defined(SERIAL_HAVE_ONLY_DMA) && defined(SERIAL_HAVE_RXDMA)
const struct uart_ops_s *g_o0 = &g_lpuart_rxdma_ops;
#endif
#if !defined(SERIAL_HAVE_ONLY_DMA) && defined(SERIAL_HAVE_TXDMA)
const struct uart_ops_s *g_o1 = &g_lpuart_txdma_ops;
#endif
/* I/O buffers */
#ifdef CONFIG_LPUART1_RXDMA
static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE]
aligned_data(ARMV7M_DCACHE_LINESIZE);
#endif
# ifdef CONFIG_LPUART2_RXDMA
static char g_lpuart2rxfifo[RXDMA_BUFFER_SIZE]
aligned_data(ARMV7M_DCACHE_LINESIZE);
#endif
#ifdef CONFIG_LPUART3_RXDMA
static char g_lpuart3rxfifo[RXDMA_BUFFER_SIZE]
aligned_data(ARMV7M_DCACHE_LINESIZE);
#endif
#ifdef CONFIG_LPUART4_RXDMA
static char g_lpuart4rxfifo[RXDMA_BUFFER_SIZE]
aligned_data(ARMV7M_DCACHE_LINESIZE);