This repository has been archived by the owner on May 22, 2023. It is now read-only.
/
Diagnostics.c
423 lines (366 loc) · 12.6 KB
/
Diagnostics.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
/*
* Copyright (c) 2005-2008 Apple Inc. All rights reserved.
*
* @APPLE_OSREFERENCE_LICENSE_HEADER_START@
*
* This file contains Original Code and/or Modifications of Original Code
* as defined in and that are subject to the Apple Public Source License
* Version 2.0 (the 'License'). You may not use this file except in
* compliance with the License. The rights granted to you under the License
* may not be used to create, or enable the creation or redistribution of,
* unlawful or unlicensed copies of an Apple operating system, or to
* circumvent, violate, or enable the circumvention or violation of, any
* terms of an Apple operating system software license agreement.
*
* Please obtain a copy of the License at
* http://www.opensource.apple.com/apsl/ and read it before using this file.
*
* The Original Code and all software distributed under the License are
* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
* Please see the License for the specific language governing rights and
* limitations under the License.
*
* @APPLE_OSREFERENCE_LICENSE_HEADER_END@
*/
/*
* @OSF_FREE_COPYRIGHT@
*/
/*
* @APPLE_FREE_COPYRIGHT@
*/
/*
* Author: Bill Angell, Apple
* Date: 10/auht-five
*
* Random diagnostics, augmented Derek Kumar 2011
*
*
*/
#include <kern/machine.h>
#include <kern/processor.h>
#include <mach/machine.h>
#include <mach/processor_info.h>
#include <mach/mach_types.h>
#include <mach/boolean.h>
#include <kern/thread.h>
#include <kern/task.h>
#include <kern/ipc_kobject.h>
#include <mach/vm_param.h>
#include <ipc/port.h>
#include <ipc/ipc_entry.h>
#include <ipc/ipc_space.h>
#include <ipc/ipc_object.h>
#include <ipc/ipc_port.h>
#include <vm/vm_kern.h>
#include <vm/vm_map.h>
#include <vm/vm_page.h>
#include <vm/pmap.h>
#include <pexpert/pexpert.h>
#include <console/video_console.h>
#include <i386/cpu_data.h>
#include <i386/Diagnostics.h>
#include <i386/mp.h>
#include <i386/pmCPU.h>
#include <i386/tsc.h>
#include <mach/i386/syscall_sw.h>
#include <kern/kalloc.h>
#include <sys/kdebug.h>
#include <i386/machine_cpu.h>
#include <i386/misc_protos.h>
#include <i386/cpuid.h>
#if MONOTONIC
#include <kern/monotonic.h>
#endif /* MONOTONIC */
#define PERMIT_PERMCHECK (0)
diagWork dgWork;
uint64_t lastRuptClear = 0ULL;
boolean_t diag_pmc_enabled = FALSE;
void cpu_powerstats(void *);
typedef struct {
uint64_t caperf;
uint64_t cmperf;
uint64_t ccres[6];
uint64_t crtimes[CPU_RTIME_BINS];
uint64_t citimes[CPU_ITIME_BINS];
uint64_t crtime_total;
uint64_t citime_total;
uint64_t cpu_idle_exits;
uint64_t cpu_insns;
uint64_t cpu_ucc;
uint64_t cpu_urc;
#if DIAG_ALL_PMCS
uint64_t gpmcs[4];
#endif /* DIAG_ALL_PMCS */
} core_energy_stat_t;
typedef struct {
uint64_t pkes_version;
uint64_t pkg_cres[2][7];
uint64_t pkg_power_unit;
uint64_t pkg_energy;
uint64_t pp0_energy;
uint64_t pp1_energy;
uint64_t ddr_energy;
uint64_t llc_flushed_cycles;
uint64_t ring_ratio_instantaneous;
uint64_t IA_frequency_clipping_cause;
uint64_t GT_frequency_clipping_cause;
uint64_t pkg_idle_exits;
uint64_t pkg_rtimes[CPU_RTIME_BINS];
uint64_t pkg_itimes[CPU_ITIME_BINS];
uint64_t mbus_delay_time;
uint64_t mint_delay_time;
uint32_t ncpus;
core_energy_stat_t cest[];
} pkg_energy_statistics_t;
int
diagCall64(x86_saved_state_t * state)
{
uint64_t curpos, i, j;
uint64_t selector, data;
uint64_t currNap, durNap;
x86_saved_state64_t *regs;
boolean_t diagflag;
uint32_t rval = 0;
assert(is_saved_state64(state));
regs = saved_state64(state);
diagflag = ((dgWork.dgFlags & enaDiagSCs) != 0);
selector = regs->rdi;
switch (selector) { /* Select the routine */
case dgRuptStat: /* Suck Interruption statistics */
(void) ml_set_interrupts_enabled(TRUE);
data = regs->rsi; /* Get the number of processors */
if (data == 0) { /* If no location is specified for data, clear all
* counts
*/
for (i = 0; i < real_ncpus; i++) { /* Cycle through
* processors */
for (j = 0; j < 256; j++) {
cpu_data_ptr[i]->cpu_hwIntCnt[j] = 0;
}
}
lastRuptClear = mach_absolute_time(); /* Get the time of clear */
rval = 1; /* Normal return */
(void) ml_set_interrupts_enabled(FALSE);
break;
}
(void) copyout((char *) &real_ncpus, data, sizeof(real_ncpus)); /* Copy out number of
* processors */
currNap = mach_absolute_time(); /* Get the time now */
durNap = currNap - lastRuptClear; /* Get the last interval
* duration */
if (durNap == 0) {
durNap = 1; /* This is a very short time, make it
* bigger */
}
curpos = data + sizeof(real_ncpus); /* Point to the next
* available spot */
for (i = 0; i < real_ncpus; i++) { /* Move 'em all out */
(void) copyout((char *) &durNap, curpos, 8); /* Copy out the time
* since last clear */
(void) copyout((char *) &cpu_data_ptr[i]->cpu_hwIntCnt, curpos + 8, 256 * sizeof(uint32_t)); /* Copy out interrupt
* data for this
* processor */
curpos = curpos + (256 * sizeof(uint32_t) + 8); /* Point to next out put
* slot */
}
rval = 1;
(void) ml_set_interrupts_enabled(FALSE);
break;
case dgPowerStat:
{
uint32_t c2l = 0, c2h = 0, c3l = 0, c3h = 0, c6l = 0, c6h = 0, c7l = 0, c7h = 0;
uint32_t pkg_unit_l = 0, pkg_unit_h = 0, pkg_ecl = 0, pkg_ech = 0;
pkg_energy_statistics_t pkes;
core_energy_stat_t cest;
bzero(&pkes, sizeof(pkes));
bzero(&cest, sizeof(cest));
pkes.pkes_version = 1ULL;
rdmsr_carefully(MSR_IA32_PKG_C2_RESIDENCY, &c2l, &c2h);
rdmsr_carefully(MSR_IA32_PKG_C3_RESIDENCY, &c3l, &c3h);
rdmsr_carefully(MSR_IA32_PKG_C6_RESIDENCY, &c6l, &c6h);
rdmsr_carefully(MSR_IA32_PKG_C7_RESIDENCY, &c7l, &c7h);
pkes.pkg_cres[0][0] = ((uint64_t)c2h << 32) | c2l;
pkes.pkg_cres[0][1] = ((uint64_t)c3h << 32) | c3l;
pkes.pkg_cres[0][2] = ((uint64_t)c6h << 32) | c6l;
pkes.pkg_cres[0][3] = ((uint64_t)c7h << 32) | c7l;
uint64_t c8r = ~0ULL, c9r = ~0ULL, c10r = ~0ULL;
rdmsr64_carefully(MSR_IA32_PKG_C8_RESIDENCY, &c8r);
rdmsr64_carefully(MSR_IA32_PKG_C9_RESIDENCY, &c9r);
rdmsr64_carefully(MSR_IA32_PKG_C10_RESIDENCY, &c10r);
pkes.pkg_cres[0][4] = c8r;
pkes.pkg_cres[0][5] = c9r;
pkes.pkg_cres[0][6] = c10r;
pkes.ddr_energy = ~0ULL;
rdmsr64_carefully(MSR_IA32_DDR_ENERGY_STATUS, &pkes.ddr_energy);
pkes.llc_flushed_cycles = ~0ULL;
rdmsr64_carefully(MSR_IA32_LLC_FLUSHED_RESIDENCY_TIMER, &pkes.llc_flushed_cycles);
pkes.ring_ratio_instantaneous = ~0ULL;
rdmsr64_carefully(MSR_IA32_RING_PERF_STATUS, &pkes.ring_ratio_instantaneous);
pkes.IA_frequency_clipping_cause = ~0ULL;
uint32_t ia_perf_limits = MSR_IA32_IA_PERF_LIMIT_REASONS;
/* Should perhaps be a generic register map module for these
* registers with identical functionality that were renumbered.
*/
switch (cpuid_cpufamily()) {
case CPUFAMILY_INTEL_SKYLAKE:
case CPUFAMILY_INTEL_KABYLAKE:
case CPUFAMILY_INTEL_ICELAKE:
ia_perf_limits = MSR_IA32_IA_PERF_LIMIT_REASONS_SKL;
break;
default:
break;
}
rdmsr64_carefully(ia_perf_limits, &pkes.IA_frequency_clipping_cause);
pkes.GT_frequency_clipping_cause = ~0ULL;
rdmsr64_carefully(MSR_IA32_GT_PERF_LIMIT_REASONS, &pkes.GT_frequency_clipping_cause);
rdmsr_carefully(MSR_IA32_PKG_POWER_SKU_UNIT, &pkg_unit_l, &pkg_unit_h);
rdmsr_carefully(MSR_IA32_PKG_ENERGY_STATUS, &pkg_ecl, &pkg_ech);
pkes.pkg_power_unit = ((uint64_t)pkg_unit_h << 32) | pkg_unit_l;
pkes.pkg_energy = ((uint64_t)pkg_ech << 32) | pkg_ecl;
rdmsr_carefully(MSR_IA32_PP0_ENERGY_STATUS, &pkg_ecl, &pkg_ech);
pkes.pp0_energy = ((uint64_t)pkg_ech << 32) | pkg_ecl;
rdmsr_carefully(MSR_IA32_PP1_ENERGY_STATUS, &pkg_ecl, &pkg_ech);
pkes.pp1_energy = ((uint64_t)pkg_ech << 32) | pkg_ecl;
pkes.pkg_idle_exits = current_cpu_datap()->lcpu.package->package_idle_exits;
pkes.ncpus = real_ncpus;
(void) ml_set_interrupts_enabled(TRUE);
copyout(&pkes, regs->rsi, sizeof(pkes));
curpos = regs->rsi + sizeof(pkes);
mp_cpus_call(CPUMASK_ALL, ASYNC, cpu_powerstats, NULL);
for (i = 0; i < real_ncpus; i++) {
(void) ml_set_interrupts_enabled(FALSE);
cest.caperf = cpu_data_ptr[i]->cpu_aperf;
cest.cmperf = cpu_data_ptr[i]->cpu_mperf;
cest.ccres[0] = cpu_data_ptr[i]->cpu_c3res;
cest.ccres[1] = cpu_data_ptr[i]->cpu_c6res;
cest.ccres[2] = cpu_data_ptr[i]->cpu_c7res;
bcopy(&cpu_data_ptr[i]->cpu_rtimes[0], &cest.crtimes[0], sizeof(cest.crtimes));
bcopy(&cpu_data_ptr[i]->cpu_itimes[0], &cest.citimes[0], sizeof(cest.citimes));
cest.citime_total = cpu_data_ptr[i]->cpu_itime_total;
cest.crtime_total = cpu_data_ptr[i]->cpu_rtime_total;
cest.cpu_idle_exits = cpu_data_ptr[i]->cpu_idle_exits;
#if MONOTONIC
cest.cpu_insns = cpu_data_ptr[i]->cpu_monotonic.mtc_counts[MT_CORE_INSTRS];
cest.cpu_ucc = cpu_data_ptr[i]->cpu_monotonic.mtc_counts[MT_CORE_CYCLES];
cest.cpu_urc = cpu_data_ptr[i]->cpu_monotonic.mtc_counts[MT_CORE_REFCYCLES];
#endif /* MONOTONIC */
#if DIAG_ALL_PMCS
bcopy(&cpu_data_ptr[i]->cpu_gpmcs[0], &cest.gpmcs[0], sizeof(cest.gpmcs));
#endif /* DIAG_ALL_PMCS */
(void) ml_set_interrupts_enabled(TRUE);
copyout(&cest, curpos, sizeof(cest));
curpos += sizeof(cest);
}
rval = 1;
(void) ml_set_interrupts_enabled(FALSE);
}
break;
case dgEnaPMC:
{
boolean_t enable = TRUE;
uint32_t cpuinfo[4];
/* Require architectural PMC v2 or higher, corresponding to
* Merom+, or equivalent virtualised facility.
*/
do_cpuid(0xA, &cpuinfo[0]);
if ((cpuinfo[0] & 0xFF) >= 2) {
mp_cpus_call(CPUMASK_ALL, ASYNC, cpu_pmc_control, &enable);
diag_pmc_enabled = TRUE;
}
rval = 1;
}
break;
#if DEVELOPMENT || DEBUG
case dgGzallocTest:
{
(void) ml_set_interrupts_enabled(TRUE);
if (diagflag) {
unsigned *ptr = (unsigned *)kalloc(1024);
kfree(ptr, 1024);
*ptr = 0x42;
}
(void) ml_set_interrupts_enabled(FALSE);
}
break;
#endif
#if DEVELOPMENT || DEBUG
case dgPermCheck:
{
(void) ml_set_interrupts_enabled(TRUE);
if (diagflag) {
rval = pmap_permissions_verify(kernel_pmap, kernel_map, 0, ~0ULL);
}
(void) ml_set_interrupts_enabled(FALSE);
}
break;
#endif /* DEVELOPMENT || DEBUG */
default: /* Handle invalid ones */
rval = 0; /* Return an exception */
}
regs->rax = rval;
assert(ml_get_interrupts_enabled() == FALSE);
return rval;
}
void
cpu_powerstats(__unused void *arg)
{
cpu_data_t *cdp = current_cpu_datap();
__unused int cnum = cdp->cpu_number;
uint32_t cl = 0, ch = 0, mpl = 0, mph = 0, apl = 0, aph = 0;
rdmsr_carefully(MSR_IA32_MPERF, &mpl, &mph);
rdmsr_carefully(MSR_IA32_APERF, &apl, &aph);
cdp->cpu_mperf = ((uint64_t)mph << 32) | mpl;
cdp->cpu_aperf = ((uint64_t)aph << 32) | apl;
uint64_t ctime = mach_absolute_time();
cdp->cpu_rtime_total += ctime - cdp->cpu_ixtime;
cdp->cpu_ixtime = ctime;
rdmsr_carefully(MSR_IA32_CORE_C3_RESIDENCY, &cl, &ch);
cdp->cpu_c3res = ((uint64_t)ch << 32) | cl;
rdmsr_carefully(MSR_IA32_CORE_C6_RESIDENCY, &cl, &ch);
cdp->cpu_c6res = ((uint64_t)ch << 32) | cl;
rdmsr_carefully(MSR_IA32_CORE_C7_RESIDENCY, &cl, &ch);
cdp->cpu_c7res = ((uint64_t)ch << 32) | cl;
if (diag_pmc_enabled) {
#if MONOTONIC
mt_update_fixed_counts();
#else /* MONOTONIC */
uint64_t insns = read_pmc(FIXED_PMC0);
uint64_t ucc = read_pmc(FIXED_PMC1);
uint64_t urc = read_pmc(FIXED_PMC2);
#endif /* !MONOTONIC */
#if DIAG_ALL_PMCS
int i;
for (i = 0; i < 4; i++) {
cdp->cpu_gpmcs[i] = read_pmc(i);
}
#endif /* DIAG_ALL_PMCS */
#if !MONOTONIC
cdp->cpu_cur_insns = insns;
cdp->cpu_cur_ucc = ucc;
cdp->cpu_cur_urc = urc;
#endif /* !MONOTONIC */
}
}
void
cpu_pmc_control(void *enablep)
{
#if !MONOTONIC
boolean_t enable = *(boolean_t *)enablep;
cpu_data_t *cdp = current_cpu_datap();
if (enable) {
wrmsr64(0x38F, 0x70000000FULL);
wrmsr64(0x38D, 0x333);
set_cr4(get_cr4() | CR4_PCE);
} else {
wrmsr64(0x38F, 0);
wrmsr64(0x38D, 0);
set_cr4((get_cr4() & ~CR4_PCE));
}
cdp->cpu_fixed_pmcs_enabled = enable;
#else /* !MONOTONIC */
#pragma unused(enablep)
#endif /* MONOTONIC */
}