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mp.c
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mp.c
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/*
* Copyright (c) 2000-2020 Apple Inc. All rights reserved.
*
* @APPLE_OSREFERENCE_LICENSE_HEADER_START@
*
* This file contains Original Code and/or Modifications of Original Code
* as defined in and that are subject to the Apple Public Source License
* Version 2.0 (the 'License'). You may not use this file except in
* compliance with the License. The rights granted to you under the License
* may not be used to create, or enable the creation or redistribution of,
* unlawful or unlicensed copies of an Apple operating system, or to
* circumvent, violate, or enable the circumvention or violation of, any
* terms of an Apple operating system software license agreement.
*
* Please obtain a copy of the License at
* http://www.opensource.apple.com/apsl/ and read it before using this file.
*
* The Original Code and all software distributed under the License are
* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
* Please see the License for the specific language governing rights and
* limitations under the License.
*
* @APPLE_OSREFERENCE_LICENSE_HEADER_END@
*/
/*
* @OSF_COPYRIGHT@
*/
#include <mach_kdp.h>
#include <kdp/kdp_internal.h>
#include <mach_ldebug.h>
#include <mach/mach_types.h>
#include <mach/kern_return.h>
#include <kern/kern_types.h>
#include <kern/startup.h>
#include <kern/timer_queue.h>
#include <kern/processor.h>
#include <kern/cpu_number.h>
#include <kern/cpu_data.h>
#include <kern/assert.h>
#include <kern/lock_group.h>
#include <kern/machine.h>
#include <kern/pms.h>
#include <kern/misc_protos.h>
#include <kern/timer_call.h>
#include <kern/zalloc.h>
#include <kern/queue.h>
#include <prng/random.h>
#include <vm/vm_map.h>
#include <vm/vm_kern.h>
#include <i386/bit_routines.h>
#include <i386/proc_reg.h>
#include <i386/cpu_threads.h>
#include <i386/mp_desc.h>
#include <i386/misc_protos.h>
#include <i386/trap.h>
#include <i386/postcode.h>
#include <i386/machine_routines.h>
#include <i386/mp.h>
#include <i386/mp_events.h>
#include <i386/lapic.h>
#include <i386/cpuid.h>
#include <i386/fpu.h>
#include <i386/machine_cpu.h>
#include <i386/pmCPU.h>
#if CONFIG_MCA
#include <i386/machine_check.h>
#endif
#include <i386/acpi.h>
#include <sys/kdebug.h>
#include <console/serial_protos.h>
#if MONOTONIC
#include <kern/monotonic.h>
#endif /* MONOTONIC */
#if MP_DEBUG
#define PAUSE delay(1000000)
#define DBG(x...) kprintf(x)
#else
#define DBG(x...)
#define PAUSE
#endif /* MP_DEBUG */
/* Debugging/test trace events: */
#define TRACE_MP_TLB_FLUSH MACHDBG_CODE(DBG_MACH_MP, 0)
#define TRACE_MP_CPUS_CALL MACHDBG_CODE(DBG_MACH_MP, 1)
#define TRACE_MP_CPUS_CALL_LOCAL MACHDBG_CODE(DBG_MACH_MP, 2)
#define TRACE_MP_CPUS_CALL_ACTION MACHDBG_CODE(DBG_MACH_MP, 3)
#define TRACE_MP_CPUS_CALL_NOBUF MACHDBG_CODE(DBG_MACH_MP, 4)
#define TRACE_MP_CPU_FAST_START MACHDBG_CODE(DBG_MACH_MP, 5)
#define TRACE_MP_CPU_START MACHDBG_CODE(DBG_MACH_MP, 6)
#define TRACE_MP_CPU_DEACTIVATE MACHDBG_CODE(DBG_MACH_MP, 7)
#define ABS(v) (((v) > 0)?(v):-(v))
void slave_boot_init(void);
void i386_cpu_IPI(int cpu);
#if MACH_KDP
static void mp_kdp_wait(boolean_t flush, boolean_t isNMI);
#endif /* MACH_KDP */
#if MACH_KDP
static boolean_t cpu_signal_pending(int cpu, mp_event_t event);
#endif /* MACH_KDP */
static int NMIInterruptHandler(x86_saved_state_t *regs);
boolean_t smp_initialized = FALSE;
uint32_t TSC_sync_margin = 0xFFF;
volatile boolean_t force_immediate_debugger_NMI = FALSE;
volatile boolean_t pmap_tlb_flush_timeout = FALSE;
#if DEBUG || DEVELOPMENT
boolean_t mp_interrupt_watchdog_enabled = TRUE;
uint32_t mp_interrupt_watchdog_events = 0;
#endif
SIMPLE_LOCK_DECLARE(debugger_callback_lock, 0);
struct debugger_callback *debugger_callback = NULL;
static LCK_GRP_DECLARE(smp_lck_grp, "i386_smp");
static LCK_MTX_EARLY_DECLARE(mp_cpu_boot_lock, &smp_lck_grp);
/* Variables needed for MP rendezvous. */
SIMPLE_LOCK_DECLARE(mp_rv_lock, 0);
static void (*mp_rv_setup_func)(void *arg);
static void (*mp_rv_action_func)(void *arg);
static void (*mp_rv_teardown_func)(void *arg);
static void *mp_rv_func_arg;
static volatile int mp_rv_ncpus;
/* Cache-aligned barriers: */
static volatile long mp_rv_entry __attribute__((aligned(64)));
static volatile long mp_rv_exit __attribute__((aligned(64)));
static volatile long mp_rv_complete __attribute__((aligned(64)));
volatile uint64_t debugger_entry_time;
volatile uint64_t debugger_exit_time;
#if MACH_KDP
#include <kdp/kdp.h>
extern int kdp_snapshot;
static struct _kdp_xcpu_call_func {
kdp_x86_xcpu_func_t func;
void *arg0, *arg1;
volatile long ret;
volatile uint16_t cpu;
} kdp_xcpu_call_func = {
.cpu = KDP_XCPU_NONE
};
#endif
/* Variables needed for MP broadcast. */
static void (*mp_bc_action_func)(void *arg);
static void *mp_bc_func_arg;
static int mp_bc_ncpus;
static volatile long mp_bc_count;
static LCK_MTX_EARLY_DECLARE(mp_bc_lock, &smp_lck_grp);
static volatile int debugger_cpu = -1;
volatile long NMIPI_acks = 0;
volatile long NMI_count = 0;
static NMI_reason_t NMI_panic_reason = NONE;
static int vector_timed_out;
extern void NMI_cpus(void);
static void mp_cpus_call_init(void);
static void mp_cpus_call_action(void);
static void mp_call_PM(void);
char mp_slave_stack[PAGE_SIZE] __attribute__((aligned(PAGE_SIZE))); // Temp stack for slave init
/* PAL-related routines */
boolean_t i386_smp_init(int nmi_vector, i386_intr_func_t nmi_handler,
int ipi_vector, i386_intr_func_t ipi_handler);
void i386_start_cpu(int lapic_id, int cpu_num);
void i386_send_NMI(int cpu);
void NMIPI_enable(boolean_t);
#define NUM_CPU_WARM_CALLS 20
struct timer_call cpu_warm_call_arr[NUM_CPU_WARM_CALLS];
queue_head_t cpu_warm_call_list;
decl_simple_lock_data(static, cpu_warm_lock);
typedef struct cpu_warm_data {
timer_call_t cwd_call;
uint64_t cwd_deadline;
int cwd_result;
} *cpu_warm_data_t;
static void cpu_prewarm_init(void);
static void cpu_warm_timer_call_func(timer_call_param_t p0, timer_call_param_t p1);
static void _cpu_warm_setup(void *arg);
static timer_call_t grab_warm_timer_call(void);
static void free_warm_timer_call(timer_call_t call);
void
smp_init(void)
{
console_init();
if (!i386_smp_init(LAPIC_NMI_INTERRUPT, NMIInterruptHandler,
LAPIC_VECTOR(INTERPROCESSOR), cpu_signal_handler)) {
return;
}
cpu_thread_init();
DBGLOG_CPU_INIT(master_cpu);
mp_cpus_call_init();
mp_cpus_call_cpu_init(master_cpu);
#if DEBUG || DEVELOPMENT
if (PE_parse_boot_argn("interrupt_watchdog",
&mp_interrupt_watchdog_enabled,
sizeof(mp_interrupt_watchdog_enabled))) {
kprintf("Interrupt watchdog %sabled\n",
mp_interrupt_watchdog_enabled ? "en" : "dis");
}
#endif
if (PE_parse_boot_argn("TSC_sync_margin",
&TSC_sync_margin, sizeof(TSC_sync_margin))) {
kprintf("TSC sync Margin 0x%x\n", TSC_sync_margin);
} else if (cpuid_vmm_present()) {
kprintf("TSC sync margin disabled\n");
TSC_sync_margin = 0;
}
smp_initialized = TRUE;
cpu_prewarm_init();
return;
}
typedef struct {
int target_cpu;
int target_lapic;
int starter_cpu;
} processor_start_info_t;
static processor_start_info_t start_info __attribute__((aligned(64)));
/*
* Cache-alignment is to avoid cross-cpu false-sharing interference.
*/
static volatile long tsc_entry_barrier __attribute__((aligned(64)));
static volatile long tsc_exit_barrier __attribute__((aligned(64)));
static volatile uint64_t tsc_target __attribute__((aligned(64)));
/*
* Poll a CPU to see when it has marked itself as running.
*/
static void
mp_wait_for_cpu_up(int slot_num, unsigned int iters, unsigned int usecdelay)
{
while (iters-- > 0) {
if (cpu_datap(slot_num)->cpu_running) {
break;
}
delay(usecdelay);
}
}
/*
* Quickly bring a CPU back online which has been halted.
*/
kern_return_t
intel_startCPU_fast(int slot_num)
{
kern_return_t rc;
/*
* Try to perform a fast restart
*/
rc = pmCPUExitHalt(slot_num);
if (rc != KERN_SUCCESS) {
/*
* The CPU was not eligible for a fast restart.
*/
return rc;
}
KERNEL_DEBUG_CONSTANT(
TRACE_MP_CPU_FAST_START | DBG_FUNC_START,
slot_num, 0, 0, 0, 0);
/*
* Wait until the CPU is back online.
*/
mp_disable_preemption();
/*
* We use short pauses (1us) for low latency. 30,000 iterations is
* longer than a full restart would require so it should be more
* than long enough.
*/
mp_wait_for_cpu_up(slot_num, 30000, 1);
mp_enable_preemption();
KERNEL_DEBUG_CONSTANT(
TRACE_MP_CPU_FAST_START | DBG_FUNC_END,
slot_num, cpu_datap(slot_num)->cpu_running, 0, 0, 0);
/*
* Check to make sure that the CPU is really running. If not,
* go through the slow path.
*/
if (cpu_datap(slot_num)->cpu_running) {
return KERN_SUCCESS;
} else {
return KERN_FAILURE;
}
}
static void
started_cpu(void)
{
/* Here on the started cpu with cpu_running set TRUE */
if (TSC_sync_margin &&
start_info.target_cpu == cpu_number()) {
/*
* I've just started-up, synchronize again with the starter cpu
* and then snap my TSC.
*/
tsc_target = 0;
atomic_decl(&tsc_entry_barrier, 1);
while (tsc_entry_barrier != 0) {
; /* spin for starter and target at barrier */
}
tsc_target = rdtsc64();
atomic_decl(&tsc_exit_barrier, 1);
}
}
static void
start_cpu(void *arg)
{
int i = 1000;
processor_start_info_t *psip = (processor_start_info_t *) arg;
/* Ignore this if the current processor is not the starter */
if (cpu_number() != psip->starter_cpu) {
return;
}
DBG("start_cpu(%p) about to start cpu %d, lapic %d\n",
arg, psip->target_cpu, psip->target_lapic);
KERNEL_DEBUG_CONSTANT(
TRACE_MP_CPU_START | DBG_FUNC_START,
psip->target_cpu,
psip->target_lapic, 0, 0, 0);
i386_start_cpu(psip->target_lapic, psip->target_cpu);
#ifdef POSTCODE_DELAY
/* Wait much longer if postcodes are displayed for a delay period. */
i *= 10000;
#endif
DBG("start_cpu(%p) about to wait for cpu %d\n",
arg, psip->target_cpu);
mp_wait_for_cpu_up(psip->target_cpu, i * 100, 100);
KERNEL_DEBUG_CONSTANT(
TRACE_MP_CPU_START | DBG_FUNC_END,
psip->target_cpu,
cpu_datap(psip->target_cpu)->cpu_running, 0, 0, 0);
if (TSC_sync_margin &&
cpu_datap(psip->target_cpu)->cpu_running) {
/*
* Compare the TSC from the started processor with ours.
* Report and log/panic if it diverges by more than
* TSC_sync_margin (TSC_SYNC_MARGIN) ticks. This margin
* can be overriden by boot-arg (with 0 meaning no checking).
*/
uint64_t tsc_starter;
int64_t tsc_delta;
atomic_decl(&tsc_entry_barrier, 1);
while (tsc_entry_barrier != 0) {
; /* spin for both processors at barrier */
}
tsc_starter = rdtsc64();
atomic_decl(&tsc_exit_barrier, 1);
while (tsc_exit_barrier != 0) {
; /* spin for target to store its TSC */
}
tsc_delta = tsc_target - tsc_starter;
kprintf("TSC sync for cpu %d: 0x%016llx delta 0x%llx (%lld)\n",
psip->target_cpu, tsc_target, tsc_delta, tsc_delta);
#if DEBUG || DEVELOPMENT
/*
* Stash the delta for inspection later, since we can no
* longer print/log it with interrupts disabled.
*/
cpu_datap(psip->target_cpu)->tsc_sync_delta = tsc_delta;
#endif
if (ABS(tsc_delta) > (int64_t) TSC_sync_margin) {
#if DEBUG
panic(
#else
kprintf(
#endif
"Unsynchronized TSC for cpu %d: "
"0x%016llx, delta 0x%llx\n",
psip->target_cpu, tsc_target, tsc_delta);
}
}
}
kern_return_t
intel_startCPU(
int slot_num)
{
int lapic = cpu_to_lapic[slot_num];
boolean_t istate;
assert(lapic != -1);
DBGLOG_CPU_INIT(slot_num);
DBG("intel_startCPU(%d) lapic_id=%d\n", slot_num, lapic);
DBG("IdlePTD(%p): 0x%x\n", &IdlePTD, (int) (uintptr_t)IdlePTD);
/*
* Initialize (or re-initialize) the descriptor tables for this cpu.
* Propagate processor mode to slave.
*/
cpu_desc_init(cpu_datap(slot_num));
/* Serialize use of the slave boot stack, etc. */
lck_mtx_lock(&mp_cpu_boot_lock);
istate = ml_set_interrupts_enabled(FALSE);
if (slot_num == get_cpu_number()) {
ml_set_interrupts_enabled(istate);
lck_mtx_unlock(&mp_cpu_boot_lock);
return KERN_SUCCESS;
}
start_info.starter_cpu = cpu_number();
start_info.target_cpu = slot_num;
start_info.target_lapic = lapic;
tsc_entry_barrier = 2;
tsc_exit_barrier = 2;
/*
* Perform the processor startup sequence with all running
* processors rendezvous'ed. This is required during periods when
* the cache-disable bit is set for MTRR/PAT initialization.
*/
mp_rendezvous_no_intrs(start_cpu, (void *) &start_info);
start_info.target_cpu = 0;
ml_set_interrupts_enabled(istate);
lck_mtx_unlock(&mp_cpu_boot_lock);
if (!cpu_datap(slot_num)->cpu_running) {
kprintf("Failed to start CPU %02d\n", slot_num);
printf("Failed to start CPU %02d, rebooting...\n", slot_num);
delay(1000000);
halt_cpu();
return KERN_SUCCESS;
} else {
kprintf("Started cpu %d (lapic id %08x)\n", slot_num, lapic);
return KERN_SUCCESS;
}
}
#if MP_DEBUG
cpu_signal_event_log_t *cpu_signal[MAX_CPUS];
cpu_signal_event_log_t *cpu_handle[MAX_CPUS];
MP_EVENT_NAME_DECL();
#endif /* MP_DEBUG */
/*
* Note: called with NULL state when polling for TLB flush and cross-calls.
*/
int
cpu_signal_handler(x86_saved_state_t *regs)
{
#if !MACH_KDP
#pragma unused (regs)
#endif /* !MACH_KDP */
int my_cpu;
volatile int *my_word;
SCHED_STATS_INC(ipi_count);
my_cpu = cpu_number();
my_word = &cpu_data_ptr[my_cpu]->cpu_signals;
/* Store the initial set of signals for diagnostics. New
* signals could arrive while these are being processed
* so it's no more than a hint.
*/
cpu_data_ptr[my_cpu]->cpu_prior_signals = *my_word;
do {
#if MACH_KDP
if (i_bit(MP_KDP, my_word)) {
DBGLOG(cpu_handle, my_cpu, MP_KDP);
i_bit_clear(MP_KDP, my_word);
/* Ensure that the i386_kernel_state at the base of the
* current thread's stack (if any) is synchronized with the
* context at the moment of the interrupt, to facilitate
* access through the debugger.
*/
sync_iss_to_iks(regs);
if (pmsafe_debug && !kdp_snapshot) {
pmSafeMode(¤t_cpu_datap()->lcpu, PM_SAFE_FL_SAFE);
}
mp_kdp_wait(TRUE, FALSE);
if (pmsafe_debug && !kdp_snapshot) {
pmSafeMode(¤t_cpu_datap()->lcpu, PM_SAFE_FL_NORMAL);
}
} else
#endif /* MACH_KDP */
if (i_bit(MP_TLB_FLUSH, my_word)) {
DBGLOG(cpu_handle, my_cpu, MP_TLB_FLUSH);
i_bit_clear(MP_TLB_FLUSH, my_word);
pmap_update_interrupt();
} else if (i_bit(MP_CALL, my_word)) {
DBGLOG(cpu_handle, my_cpu, MP_CALL);
i_bit_clear(MP_CALL, my_word);
mp_cpus_call_action();
} else if (i_bit(MP_CALL_PM, my_word)) {
DBGLOG(cpu_handle, my_cpu, MP_CALL_PM);
i_bit_clear(MP_CALL_PM, my_word);
mp_call_PM();
}
if (regs == NULL) {
/* Called to poll only for cross-calls and TLB flush */
break;
} else if (i_bit(MP_AST, my_word)) {
DBGLOG(cpu_handle, my_cpu, MP_AST);
i_bit_clear(MP_AST, my_word);
ast_check(cpu_to_processor(my_cpu));
}
} while (*my_word);
return 0;
}
extern void kprintf_break_lock(void);
int
NMIInterruptHandler(x86_saved_state_t *regs)
{
void *stackptr;
char pstr[256];
uint64_t now = mach_absolute_time();
if (panic_active() && !panicDebugging) {
if (pmsafe_debug) {
pmSafeMode(¤t_cpu_datap()->lcpu, PM_SAFE_FL_SAFE);
}
for (;;) {
cpu_pause();
}
}
atomic_incl(&NMIPI_acks, 1);
atomic_incl(&NMI_count, 1);
sync_iss_to_iks_unconditionally(regs);
__asm__ volatile ("movq %%rbp, %0" : "=m" (stackptr));
if (cpu_number() == debugger_cpu) {
goto NMExit;
}
if (NMI_panic_reason == SPINLOCK_TIMEOUT) {
snprintf(&pstr[0], sizeof(pstr),
"Panic(CPU %d, time %llu): NMIPI for spinlock acquisition timeout, spinlock: %p, spinlock owner: %p, current_thread: %p, spinlock_owner_cpu: 0x%x\n",
cpu_number(), now, spinlock_timed_out, (void *) spinlock_timed_out->interlock.lock_data, current_thread(), spinlock_owner_cpu);
panic_i386_backtrace(stackptr, 64, &pstr[0], TRUE, regs);
} else if (NMI_panic_reason == TLB_FLUSH_TIMEOUT) {
snprintf(&pstr[0], sizeof(pstr),
"Panic(CPU %d, time %llu): NMIPI for unresponsive processor: TLB flush timeout, TLB state:0x%x\n",
cpu_number(), now, current_cpu_datap()->cpu_tlb_invalid);
panic_i386_backtrace(stackptr, 48, &pstr[0], TRUE, regs);
} else if (NMI_panic_reason == CROSSCALL_TIMEOUT) {
snprintf(&pstr[0], sizeof(pstr),
"Panic(CPU %d, time %llu): NMIPI for unresponsive processor: cross-call timeout\n",
cpu_number(), now);
panic_i386_backtrace(stackptr, 64, &pstr[0], TRUE, regs);
} else if (NMI_panic_reason == INTERRUPT_WATCHDOG) {
snprintf(&pstr[0], sizeof(pstr),
"Panic(CPU %d, time %llu): NMIPI for unresponsive processor: interrupt watchdog for vector 0x%x\n",
cpu_number(), now, vector_timed_out);
panic_i386_backtrace(stackptr, 64, &pstr[0], TRUE, regs);
}
#if MACH_KDP
if (pmsafe_debug && !kdp_snapshot) {
pmSafeMode(¤t_cpu_datap()->lcpu, PM_SAFE_FL_SAFE);
}
current_cpu_datap()->cpu_NMI_acknowledged = TRUE;
i_bit_clear(MP_KDP, ¤t_cpu_datap()->cpu_signals);
if (panic_active() || NMI_panic_reason != NONE) {
mp_kdp_wait(FALSE, TRUE);
} else if (!mp_kdp_trap &&
!mp_kdp_is_NMI &&
virtualized && (debug_boot_arg & DB_NMI)) {
/*
* Under a VMM with the debug boot-arg set, drop into kdp.
* Since an NMI is involved, there's a risk of contending with
* a panic. And side-effects of NMIs may result in entry into,
* and continuing from, the debugger being unreliable.
*/
if (__sync_bool_compare_and_swap(&mp_kdp_is_NMI, FALSE, TRUE)) {
kprintf_break_lock();
kprintf("Debugger entry requested by NMI\n");
kdp_i386_trap(T_DEBUG, saved_state64(regs), 0, 0);
printf("Debugger entry requested by NMI\n");
mp_kdp_is_NMI = FALSE;
} else {
mp_kdp_wait(FALSE, FALSE);
}
} else {
mp_kdp_wait(FALSE, FALSE);
}
if (pmsafe_debug && !kdp_snapshot) {
pmSafeMode(¤t_cpu_datap()->lcpu, PM_SAFE_FL_NORMAL);
}
#endif
NMExit:
return 1;
}
/*
* cpu_interrupt is really just to be used by the scheduler to
* get a CPU's attention it may not always issue an IPI. If an
* IPI is always needed then use i386_cpu_IPI.
*/
void
cpu_interrupt(int cpu)
{
boolean_t did_IPI = FALSE;
if (smp_initialized
&& pmCPUExitIdle(cpu_datap(cpu))) {
i386_cpu_IPI(cpu);
did_IPI = TRUE;
}
KERNEL_DEBUG_CONSTANT(MACHDBG_CODE(DBG_MACH_SCHED, MACH_REMOTE_AST), cpu, did_IPI, 0, 0, 0);
}
/*
* Send a true NMI via the local APIC to the specified CPU.
*/
void
cpu_NMI_interrupt(int cpu)
{
if (smp_initialized) {
i386_send_NMI(cpu);
}
}
void
NMI_cpus(void)
{
unsigned int cpu;
boolean_t intrs_enabled;
uint64_t tsc_timeout;
intrs_enabled = ml_set_interrupts_enabled(FALSE);
NMIPI_enable(TRUE);
for (cpu = 0; cpu < real_ncpus; cpu++) {
if (!cpu_is_running(cpu)) {
continue;
}
cpu_datap(cpu)->cpu_NMI_acknowledged = FALSE;
cpu_NMI_interrupt(cpu);
tsc_timeout = !machine_timeout_suspended() ?
rdtsc64() + (1000 * 1000 * 1000 * 10ULL) :
~0ULL;
while (!cpu_datap(cpu)->cpu_NMI_acknowledged) {
handle_pending_TLB_flushes();
cpu_pause();
if (rdtsc64() > tsc_timeout) {
panic("NMI_cpus() timeout cpu %d", cpu);
}
}
cpu_datap(cpu)->cpu_NMI_acknowledged = FALSE;
}
NMIPI_enable(FALSE);
ml_set_interrupts_enabled(intrs_enabled);
}
static void(*volatile mp_PM_func)(void) = NULL;
static void
mp_call_PM(void)
{
assert(!ml_get_interrupts_enabled());
if (mp_PM_func != NULL) {
mp_PM_func();
}
}
void
cpu_PM_interrupt(int cpu)
{
assert(!ml_get_interrupts_enabled());
if (mp_PM_func != NULL) {
if (cpu == cpu_number()) {
mp_PM_func();
} else {
i386_signal_cpu(cpu, MP_CALL_PM, ASYNC);
}
}
}
void
PM_interrupt_register(void (*fn)(void))
{
mp_PM_func = fn;
}
void
i386_signal_cpu(int cpu, mp_event_t event, mp_sync_t mode)
{
volatile int *signals = &cpu_datap(cpu)->cpu_signals;
uint64_t tsc_timeout;
if (!cpu_datap(cpu)->cpu_running) {
return;
}
if (event == MP_TLB_FLUSH) {
KERNEL_DEBUG(TRACE_MP_TLB_FLUSH | DBG_FUNC_START, cpu, 0, 0, 0, 0);
}
DBGLOG(cpu_signal, cpu, event);
i_bit_set(event, signals);
i386_cpu_IPI(cpu);
if (mode == SYNC) {
again:
tsc_timeout = !machine_timeout_suspended() ?
rdtsc64() + (1000 * 1000 * 1000) :
~0ULL;
while (i_bit(event, signals) && rdtsc64() < tsc_timeout) {
cpu_pause();
}
if (i_bit(event, signals)) {
DBG("i386_signal_cpu(%d, 0x%x, SYNC) timed out\n",
cpu, event);
goto again;
}
}
if (event == MP_TLB_FLUSH) {
KERNEL_DEBUG(TRACE_MP_TLB_FLUSH | DBG_FUNC_END, cpu, 0, 0, 0, 0);
}
}
/*
* Helper function called when busy-waiting: panic if too long
* a TSC-based time has elapsed since the start of the spin.
*/
static boolean_t
mp_spin_timeout(uint64_t tsc_start)
{
uint64_t tsc_timeout;
cpu_pause();
if (machine_timeout_suspended()) {
return FALSE;
}
/*
* The timeout is 4 * the spinlock timeout period
* unless we have serial console printing (kprintf) enabled
* in which case we allow an even greater margin.
*/
tsc_timeout = disable_serial_output ? LockTimeOutTSC << 2
: LockTimeOutTSC << 4;
return rdtsc64() > tsc_start + tsc_timeout;
}
/*
* Helper function to take a spinlock while ensuring that incoming IPIs
* are still serviced if interrupts are masked while we spin.
* Returns current interrupt state.
*/
boolean_t
mp_safe_spin_lock(usimple_lock_t lock)
{
if (ml_get_interrupts_enabled()) {
simple_lock(lock, LCK_GRP_NULL);
return TRUE;
} else {
uint64_t tsc_spin_start = rdtsc64();
while (!simple_lock_try(lock, LCK_GRP_NULL)) {
cpu_signal_handler(NULL);
if (mp_spin_timeout(tsc_spin_start)) {
uint32_t lock_cpu;
uintptr_t lowner = (uintptr_t)
lock->interlock.lock_data;
spinlock_timed_out = lock;
lock_cpu = spinlock_timeout_NMI(lowner);
NMIPI_panic(cpu_to_cpumask(lock_cpu), SPINLOCK_TIMEOUT);
panic("mp_safe_spin_lock() timed out, lock: %p, owner thread: 0x%lx, current_thread: %p, owner on CPU 0x%x, time: %llu",
lock, lowner, current_thread(), lock_cpu, mach_absolute_time());
}
}
return FALSE;
}
}
/*
* All-CPU rendezvous:
* - CPUs are signalled,
* - all execute the setup function (if specified),
* - rendezvous (i.e. all cpus reach a barrier),
* - all execute the action function (if specified),
* - rendezvous again,
* - execute the teardown function (if specified), and then
* - resume.
*
* Note that the supplied external functions _must_ be reentrant and aware
* that they are running in parallel and in an unknown lock context.
*/
static void
mp_rendezvous_action(__unused void *null)
{
boolean_t intrs_enabled;
uint64_t tsc_spin_start;
/*
* Note that mp_rv_lock was acquired by the thread that initiated the
* rendezvous and must have been acquired before we enter
* mp_rendezvous_action().
*/
current_cpu_datap()->cpu_rendezvous_in_progress = TRUE;
/* setup function */
if (mp_rv_setup_func != NULL) {
mp_rv_setup_func(mp_rv_func_arg);
}
intrs_enabled = ml_get_interrupts_enabled();
/* spin on entry rendezvous */
atomic_incl(&mp_rv_entry, 1);
tsc_spin_start = rdtsc64();
while (mp_rv_entry < mp_rv_ncpus) {
/* poll for pesky tlb flushes if interrupts disabled */
if (!intrs_enabled) {
handle_pending_TLB_flushes();
}
if (mp_spin_timeout(tsc_spin_start)) {
panic("mp_rv_action() entry: %ld of %d responses, start: 0x%llx, cur: 0x%llx", mp_rv_entry, mp_rv_ncpus, tsc_spin_start, rdtsc64());
}
}
/* action function */
if (mp_rv_action_func != NULL) {
mp_rv_action_func(mp_rv_func_arg);
}
/* spin on exit rendezvous */
atomic_incl(&mp_rv_exit, 1);
tsc_spin_start = rdtsc64();
while (mp_rv_exit < mp_rv_ncpus) {
if (!intrs_enabled) {
handle_pending_TLB_flushes();
}
if (mp_spin_timeout(tsc_spin_start)) {
panic("mp_rv_action() exit: %ld of %d responses, start: 0x%llx, cur: 0x%llx", mp_rv_exit, mp_rv_ncpus, tsc_spin_start, rdtsc64());
}
}
/* teardown function */
if (mp_rv_teardown_func != NULL) {
mp_rv_teardown_func(mp_rv_func_arg);
}
current_cpu_datap()->cpu_rendezvous_in_progress = FALSE;
/* Bump completion count */
atomic_incl(&mp_rv_complete, 1);
}
void
mp_rendezvous(void (*setup_func)(void *),
void (*action_func)(void *),
void (*teardown_func)(void *),
void *arg)
{
uint64_t tsc_spin_start;
if (!smp_initialized) {
if (setup_func != NULL) {
setup_func(arg);
}
if (action_func != NULL) {
action_func(arg);
}
if (teardown_func != NULL) {
teardown_func(arg);
}
return;
}
/* obtain rendezvous lock */
mp_rendezvous_lock();
/* set static function pointers */
mp_rv_setup_func = setup_func;
mp_rv_action_func = action_func;
mp_rv_teardown_func = teardown_func;
mp_rv_func_arg = arg;
mp_rv_entry = 0;
mp_rv_exit = 0;
mp_rv_complete = 0;
/*
* signal other processors, which will call mp_rendezvous_action()
* with interrupts disabled
*/
mp_rv_ncpus = mp_cpus_call(CPUMASK_OTHERS, NOSYNC, &mp_rendezvous_action, NULL) + 1;
/* call executor function on this cpu */
mp_rendezvous_action(NULL);
/*
* Spin for everyone to complete.
* This is necessary to ensure that all processors have proceeded
* from the exit barrier before we release the rendezvous structure.
*/
tsc_spin_start = rdtsc64();
while (mp_rv_complete < mp_rv_ncpus) {
if (mp_spin_timeout(tsc_spin_start)) {
panic("mp_rendezvous() timeout: %ld of %d responses, start: 0x%llx, cur: 0x%llx", mp_rv_complete, mp_rv_ncpus, tsc_spin_start, rdtsc64());
}
}
/* Tidy up */
mp_rv_setup_func = NULL;
mp_rv_action_func = NULL;
mp_rv_teardown_func = NULL;
mp_rv_func_arg = NULL;
/* release lock */
mp_rendezvous_unlock();
}
void
mp_rendezvous_lock(void)
{
(void) mp_safe_spin_lock(&mp_rv_lock);
}
void
mp_rendezvous_unlock(void)
{
simple_unlock(&mp_rv_lock);
}
void
mp_rendezvous_break_lock(void)
{
simple_lock_init(&mp_rv_lock, 0);
}
static void
setup_disable_intrs(__unused void * param_not_used)
{
/* disable interrupts before the first barrier */
boolean_t intr = ml_set_interrupts_enabled(FALSE);
current_cpu_datap()->cpu_iflag = intr;
DBG("CPU%d: %s\n", get_cpu_number(), __FUNCTION__);
}