GeneratorTB.vhd.bak

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
 
ENTITY GeneratorTB IS
END GeneratorTB;
 
ARCHITECTURE behavior OF GeneratorTB IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Generator
    PORT(
         CLK_100MHz : IN  std_logic;
         dout : OUT  std_logic_vector(13 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal CLK_100MHz : std_logic := '0';

 	--Outputs
   signal dout : std_logic_vector(13 downto 0);

   -- Clock period definitions
   constant CLK_100MHz_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: Generator PORT MAP (
          CLK_100MHz => CLK_100MHz,
          dout => dout
        );

   -- Clock process definitions
   CLK_100MHzP_process :process
   begin
		CLK_100MHz <= '0';
		wait for CLK_100MHz_period/2;
		CLK_100MHz <= '1';
		wait for CLK_100MHz_period/2;
   end process; 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      --wait for 100 ns;	

      --wait for CLK_100MHzP_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;