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12.a64.regs
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12.a64.regs
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A64 Hacking Guide. Part 5: Registers
====================================
(c) Groupoid Infinity
A64: R0-R30 -- general purpose registers (63..0: Xn, 31..0: Wn)
R31 -- zero register (63..0)
SP -- stack pointer (63..0)
PC -- program counter (63..0)
NEON: V0-V31 -- FPU/SIMD registers (127..0: Qn, 63..0: Dn, 31..0: Sn, 15..0: Hn, 7..0: Bn)
FPCR,FPSR -- FPU/SIMD status registers (63..0)
SVE: Z0-Z31 -- SVE registers (2047..0, ..., 127..0: Qn, 63..0: Dn, 31..0: Sn, 15..0: Hn, 7..0: Bn)
P0-P15 -- SVE predicate registers (255..0, ..., 15..0)
FFR -- SVE first fault register (63..0)
Extensions:
NEON, PMULL, FP, FP16, SVE, CRC, LSE, LSE2, RDM, RCPC, RCPC2, DOTPROD, TME, FHM, DIT, FLAGM, FLAGM2, SPE, LOR, XS,
SSBS, SB, PACA, PACG, DPB, DPB2, SVE2, SVE2-AES, SVE2-SM4, SVE2-SHA3, SVE2-BITPERM, FRINTTS, I8MM, F32MM, F64MM,
BF16, RAND, BTI, MTE, JSCVT, FCMA, AES, SHA2, SHA3, SM4, SME, ASM, BRBE, SPECRES, RAS, LS64, LRCPC, LRCPC2, TRF,
DPB, DPB2, FPAC, EPAC, HBC
A32 Registers:
31...28 27...24 23...20 19...16 15...12 11...08 07...05 04...00
+---------+---------+---------+---------+---------+---------+---------+---------+
A32 PFR #0 | RAS | DIT | AMU | CSV2 | STATE3 | STATE2 | STATE1 | STATE0 |
+---------+---------+---------+---------+---------+---------+---------+---------+
A32 PFR #1 | GIC | VIRT | SEC | GenTimer| VIRT | MProgMod| SEC | ProgMod |
+---------+---------+---------+---------+---------+---------+---------+---------+
A32 PFR #2 | | RAS | SSBS | CSV3 |
+---------+---------+---------+---------+---------+---------+---------+---------+
A32 MIDR | Implementer | Variant | Arch | Primary Part Number | Revision|
+---------+---------+---------+---------+---------+---------+---------+---------+
A32 MVFR #0 | FPround | FPshVec | FPsqrt | FPdiv | FPtrap | FPDP | FPSP | SIMDreg |
+---------+---------+---------+---------+---------+---------+---------+---------+
A32 MVFR #1 | SIMDmac | FPHP | SIMDHP | SIMDHP | SIMDint | SIMDLS | FPDNaN | FPFtZ |
+---------+---------+---------+---------+---------+---------+---------+---------+
A32 MVFR #2 | | FPmisc | SIMDmisc|
+---------+---------+---------+---------+---------+---------+---------+---------+
A32 ISAR #0 | | Divide | Debug | Coproc | CmpBr | BitField| BitCount| Swap |
+---------+---------+---------+---------+---------+---------+---------+---------+
A32 ISAR #1 | Jazelle |Interwork|Immediate| IfThen | Extend | ExceptAR| Except | Endian |
+---------+---------+---------+---------+---------+---------+---------+---------+
A32 ISAR #2 | Reversal| PSR_AR | MultU | MultS | Mult | MAI | MemHint |LoadStore|
+---------+---------+---------+---------+---------+---------+---------+---------+
A32 ISAR #3 | T32EE | TrueNOP | T32Copy | TabBr | SynPrim | SVC | SIMD | Saturate|
+---------+---------+---------+---------+---------+---------+---------+---------+
A32 ISAR #4 | SWP | PSR_M | SynPrim | Barrier | SMC | WB | WS | Unpriv |
+---------+---------+---------+---------+---------+---------+---------+---------+
A32 ISAR #5 | VCMA | RDM | | CRC32 | SHA2 | SHA1 | AES | SEVL |
+---------+---------+---------+---------+---------+---------+---------+---------+
A32 ISAR #6 | | I8MM | BF16 | SPECRES | SB | FHM | DP | JSCVT |
+---------+---------+---------+---------+---------+---------+---------+---------+
A32 MMFR #0 | InnerShr| FCSE | AuxReg | TCM | ShareLvl| OuterShr| PMSA | VMSA |
+---------+---------+---------+---------+---------+---------+---------+---------+
A32 MMFR #1 | BPred | L1TstCln| L1Uni | L1Hvd | L1UniSW | L1HvdSW | L1UniVA | L1HvdVA |
+---------+---------+---------+---------+---------+---------+---------+---------+
A32 MMFR #2 | HWAccFlg| WFIStall| MemBarr | UniTLB | HvdTLB | L1HvdRng| L1HvdBG | L1HvdFG |
+---------+---------+---------+---------+---------+---------+---------+---------+
A64 Registers:
63...60 59...56 55...52 51...48 47...44 43...40 39...36 35...32 31...28 27...24 23...20 19...16 15...12 11...08 07...05 04...00
+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+
| CSV3 | CSV2 | RME | DIT | AMU | MPAM | SEL2 | SVE | RAS | GIC | AdvSIMD | FP | EL3 | EL2 | EL1 | EL0 | A64 PFR #0
+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+
| | NMI | CSV2 | RNDRtrap| SME | | MPAM | RAS | MTE | SSBS | BT | A64 PFR #1
+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+
| RNDR | TLB | TS | FHM | DP | SM4 | SM3 | SHA3 | RDM | TME | ATOMIC | CRC32 | SHA2 | SHA1 | AES | RES0 | A64 ISAR #0
+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+
| LS64 | XS | I8MM | DGH | BF16 | SPECRES | SB | FRINTTS | GPI | GPA | LRCPC | FCMA | JCVT | API | APA | DPB | A64 ISAR #1
+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+
| | RES0 | PAC | HBC | MOPS | APA3 | GPA3 | RPRES | WFxT | A64 ISAR #2
+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+
A32 ISAR #3 SVC:
0000 Not implemented.
0001 Adds the SVC instruction.
A32 ISAR #3 SIMD:
0b0000 None implemented.
0b0001 Adds the SSAT and USAT instructions, and the Q bit in the PSRs.
0b0011 Adds the PKHBT, PKHTB, QADD16, QADD8, QASX, QSUB16, QSUB8, QSAX, SADD16, SADD8, SASX, SEL,
SHADD16, SHADD8, SHASX, SHSUB16, SHSUB8, SHSAX, SSAT16, SSUB16, SSUB8, SSAX, SXTAB16,
SXTB16, UADD16, UADD8, UASX, UHADD16, UHADD8, UHASX, UHSUB16, UHSUB8, UHSAX, UQADD16,
UQADD8, UQASX, UQSUB16, UQSUB8, UQSAX, USAD8, USADA8, USAT16, USUB16, USUB8, USAX,
UXTAB16, and UXTB16 instructions. Also adds support for the GE[3:0] bits in the PSRs.
A32 ISAR #2 LoadStore:
0000 No additional load/store instructions implemented.
0001 Adds the LDRD and STRD instructions.
0010 Adds Load Acquire (LDAB, LDAH, LDA, LDAEXB, LDAEXH, LDAEX, LDAEXD) and
Adds Store Release (STLB, STLH, STL, STLEXB, STLEXH, STLEX, STLEXD) instructions.
A32 ISAR #0 Divide:
0000 None implemented.
0001 Adds SDIV and UDIV in the T32 instruction set.
0010 Adds SDIV and UDIV in the A32 instruction set.
A32 ISAR #0 Debug:
0000 None implemented.
0001 Adds BKPT.
A32 ISAR #0 Coproc:
0000 None implemented, except for instructions separately attributed by the architecture to provide access to A32.
0001 Adds generic CDP, LDC, MCR, MRC, and STC.
0010 Adds generic CDP2, LDC2, MCR2, MRC2, and STC2.
0011 Adds generic MCRR and MRRC.
0100 Adds generic MCRR2 and MRRC2.
A32 ISAR #0 CmpBr:
0000 None implemented.
0001 Adds CBNZ and CBZ.
A32 ISAR #0 BitField:
0000 None implemented.
0001 Adds BFC, BFI, SBFX, and UBFX.
A32 ISAR #0 BitCount:
0000 None implemented.
0001 Adds CLZ.
A32 ISAR #0 Swap:
0000 None implemented.
0001 Adds SWP and SWPB.
A32 ISAR #1 Jazelle:
0000 No support for Jazelle.
0001 Adds the BXJ instruction and the J bit in the PSR.
A32 ISAR #1 Interwork:
0000 None implemented.
0001 Adds the BX instruction, and the T bit in the PSR.
0010 Adds the BLX instruction. PC loads have BX-like behavior.
A32 ISAR #1 Immediate:
0000 None implemented.
0001 Adds the MOVT instruction, encodings with zero-extended 16-bit immediates
Adds the T32 ADD and SUB instruction encodings with zero-extended 12-bit immediates.
A32 ISAR #1 IfThen:
0000 None implemented.
0001 Adds the IT instructions, and the IT bits in the PSRs.
A32 ISAR #1 Extend:
0000 No scalar sign-extend or zero-extend instructions are implemented, where scalar instructions means non-Advanced SIMD instructions.
0001 Adds the SXTB, SXTH, UXTB, and UXTH instructions.
0010 Adds the SXTB16, SXTAB, SXTAB16, SXTAH, UXTB16, UXTAB, UXTAB16, and UXTAH instructions.
A32 ISAR #1 ExceptAR:
0000 None implemented.
0001 Adds the SRS and RFE instructions, and the A and R-profile forms of the CPS instruction.
A32 ISAR #1 Except:
0000 Not implemented. This indicates that the User bank and Exception return forms of the LDM and STM instructions are not implemented.
0001 Adds the LDM (exception return), LDM (user registers), and STM (user registers) instruction versions.
A32 ISAR #1 Endian:
0000 None implemented.
0001 Adds the SETEND instruction, and the E bit in the PSRs.
A32 MVFR #2 FPmisc:
0000 Not implemented, or no support for miscellaneous features.
0001 Support for Floating-point selection.
0010 Adds Floating-point Conversion to Integer with Directed Rounding modes.
0011 Adds Floating-point Round to Integer Floating-point.
0100 Adds Floating-point MaxNum and MinNum.
A32 MVFR #2 SIMDmisc:
0000 Not implemented, or no support for miscellaneous features.
0001 Floating-point Conversion to Integer with Directed Rounding modes.
0010 Adds Floating-point Round to Integer Floating-point.
0011 Adds Floating-point MaxNum and MinNum.
A32 MIDR Implementer:
0x00 Reserved for software use.
0x41 Arm Limited.
0x42 Broadcom Corporation.
0x43 Cavium Inc.
0x44 Digital Equipment Corporation.
0x46 Fujitsu Ltd.
0x49 Infineon Technologies AG.
0x4D Motorola or Freescale Semiconductor Inc.
0x4E NVIDIA Corporation.
0x50 Applied Micro Circuits Corporation.
0x51 Qualcomm Inc.
0x56 Marvell International Ltd. 0x69 Intel Corporation.
0xC0 Ampere Computing.
A32 MIDR Arch:
0001 Armv4.
0010 Armv4T.
0011 Armv5.
0100 Armv5T.
0101 Armv5TE.
0110 Armv5TEJ.
0111 Armv6.