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ATSAM3N00B.xml
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ATSAM3N00B.xml
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<?xml version="1.0" encoding="UTF-8"?><!-- ============================================================================ --><!-- Atmel Microcontroller Software Support --><!-- ============================================================================ --><!-- Copyright (c) 2012, Atmel Corporation --><!-- --><!-- All rights reserved. --><!-- --><!-- Redistribution and use in source and binary forms, with or without --><!-- modification, are permitted provided that the following condition is met: --><!-- --><!-- - Redistributions of source code must retain the above copyright notice, --><!-- this list of conditions and the disclaimer below. --><!-- --><!-- Atmel's name may not be used to endorse or promote products derived from --><!-- this software without specific prior written permission. --><!-- --><!-- DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR --><!-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF --><!-- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE --><!-- DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, --><!-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT --><!-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, --><!-- OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF --><!-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING --><!-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, --><!-- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. --><!-- ============================================================================ --><avr-tools-device-file xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schema-version="0.3" xsi:noNamespaceSchemaLocation="../../schema/avr_tools_device_file.xsd">
<variants>
<variant ordercode="ATSAM3N00B-AU" package="LQFP64" speedmax="+0" tempmax="+0" tempmin="+0" vccmax="+0" vccmin="+0"/>
<variant ordercode="ATSAM3N00B-MU" package="QFN64" speedmax="+0" tempmax="+0" tempmin="+0" vccmax="+0" vccmin="+0"/>
</variants>
<devices>
<device architecture="CORTEX-M3" family="SAM3" name="ATSAM3N00B" series="SAM3N">
<address-spaces>
<address-space id="base" name="base" endianness="little" size="0x100000000" start="0">
<memory-segment name="IFLASH" start="0x00400000" size="0x00004000" type="flash" pagesize="256"/>
<memory-segment name="IROM" start="0x00800000" size="0x00400000" type="other"/>
<memory-segment name="IRAM" start="0x20000000" size="0x00001000" type="ram"/>
<memory-segment name="PERIPHERALS" start="0x40000000" size="0x20000000" type="io"/>
<memory-segment name="SYSTEM" start="0xE0000000" size="0x20000000" type="io"/>
</address-space>
<address-space id="fuses" name="fuses" endianness="little" size="1" start="0"/>
<address-space id="lockbits" name="lockbits" endianness="little" size="1" start="0"/>
</address-spaces>
<peripherals>
<module name="ADC" id="ADC" version="6489I">
<instance name="ADC">
<register-group address-space="base" name="ADC" name-in-module="ADC" offset="0x40038000"/>
<signals>
<signal pad="PA8" function="B" group="ADTRG"/>
<signal pad="PA17" function="X1" group="AD" index="0"/>
<signal pad="PA18" function="X1" group="AD" index="1"/>
<signal pad="PA19" function="X1" group="AD" index="2"/>
<signal pad="PA19" function="X1" group="WKUP" index="9"/>
<signal pad="PA20" function="X1" group="AD" index="3"/>
<signal pad="PA20" function="X1" group="WKUP" index="10"/>
<signal pad="PB0" function="X1" group="AD" index="4"/>
<signal pad="PB1" function="X1" group="AD" index="5"/>
<signal pad="PB2" function="X1" group="AD" index="6"/>
<signal pad="PB2" function="X1" group="WKUP" index="12"/>
<signal pad="PB3" function="X1" group="AD" index="7"/>
<signal pad="PA21" function="X1" group="AD" index="8"/>
<signal pad="PA22" function="X1" group="AD" index="9"/>
<signal pad="PC13" function="X1" group="AD" index="10"/>
<signal pad="PC15" function="X1" group="AD" index="11"/>
<signal pad="PC12" function="X1" group="AD" index="12"/>
<signal pad="PC29" function="X1" group="AD" index="13"/>
<signal pad="PC30" function="X1" group="AD" index="14"/>
<signal pad="PC31" function="X1" group="AD" index="15"/>
</signals>
</instance>
</module>
<module name="CHIPID" id="CHIPID" version="6417K">
<instance name="CHIPID">
<register-group address-space="base" name="CHIPID" name-in-module="CHIPID" offset="0x400E0740"/>
</instance>
</module>
<module name="DACC" id="DACC" version="11025A">
<instance name="DACC">
<register-group address-space="base" name="DACC" name-in-module="DACC" offset="0x4003C000"/>
<signals>
<signal pad="PB13" function="X1" group="DAC" index="0"/>
<signal pad="PA2" function="C" group="DATRG"/>
</signals>
</instance>
</module>
<module name="EFC" id="EFC" version="6450E">
<instance name="EFC">
<register-group address-space="base" name="EFC" name-in-module="EFC" offset="0x400E0A00"/>
</instance>
</module>
<module name="GPBR" id="GPBR" version="6378C">
<instance name="GPBR">
<register-group address-space="base" name="GPBR" name-in-module="GPBR" offset="0x400E1490"/>
</instance>
</module>
<module name="MATRIX" id="MATRIX" version="11049A">
<instance name="MATRIX">
<register-group address-space="base" name="MATRIX" name-in-module="MATRIX" offset="0x400E0200"/>
</instance>
</module>
<module name="PIO" id="PIO" version="11004F">
<instance name="PIOA">
<register-group address-space="base" name="PIOA" name-in-module="PIO" offset="0x400E0E00"/>
</instance>
<instance name="PIOB">
<register-group address-space="base" name="PIOB" name-in-module="PIO" offset="0x400E1000"/>
</instance>
</module>
<module name="PMC" id="PMC" version="11116C">
<instance name="PMC">
<register-group address-space="base" name="PMC" name-in-module="PMC" offset="0x400E0400"/>
<signals>
<signal pad="PA6" function="B" group="PCK" index="0"/>
<signal pad="PB13" function="B" group="PCK" index="0"/>
<signal pad="PC16" function="B" group="PCK" index="0"/>
<signal pad="PA17" function="B" group="PCK" index="1"/>
<signal pad="PA21" function="B" group="PCK" index="1"/>
<signal pad="PC17" function="B" group="PCK" index="1"/>
<signal pad="PA18" function="B" group="PCK" index="2"/>
<signal pad="PA31" function="B" group="PCK" index="2"/>
<signal pad="PB3" function="B" group="PCK" index="2"/>
<signal pad="PC14" function="B" group="PCK" index="2"/>
</signals>
</instance>
</module>
<module name="PWM" id="PWM" version="6044I">
<instance name="PWM">
<register-group address-space="base" name="PWM" name-in-module="PWM" offset="0x40020000"/>
<signals>
<signal pad="PA0" function="A" group="PWM" index="0"/>
<signal pad="PA11" function="B" group="PWM" index="0"/>
<signal pad="PA23" function="B" group="PWM" index="0"/>
<signal pad="PB0" function="A" group="PWM" index="0"/>
<signal pad="PC8" function="B" group="PWM" index="0"/>
<signal pad="PC18" function="B" group="PWM" index="0"/>
<signal pad="PC22" function="B" group="PWM" index="0"/>
<signal pad="PA1" function="A" group="PWM" index="1"/>
<signal pad="PA12" function="B" group="PWM" index="1"/>
<signal pad="PA24" function="B" group="PWM" index="1"/>
<signal pad="PB1" function="A" group="PWM" index="1"/>
<signal pad="PC9" function="B" group="PWM" index="1"/>
<signal pad="PC19" function="B" group="PWM" index="1"/>
<signal pad="PA2" function="A" group="PWM" index="2"/>
<signal pad="PA13" function="B" group="PWM" index="2"/>
<signal pad="PA25" function="B" group="PWM" index="2"/>
<signal pad="PB4" function="B" group="PWM" index="2"/>
<signal pad="PC10" function="B" group="PWM" index="2"/>
<signal pad="PC20" function="B" group="PWM" index="2"/>
<signal pad="PA7" function="B" group="PWM" index="3"/>
<signal pad="PA14" function="B" group="PWM" index="3"/>
<signal pad="PB14" function="B" group="PWM" index="3"/>
<signal pad="PC11" function="B" group="PWM" index="3"/>
<signal pad="PC21" function="B" group="PWM" index="3"/>
</signals>
</instance>
</module>
<module name="RSTC" id="RSTC" version="11009A">
<instance name="RSTC">
<register-group address-space="base" name="RSTC" name-in-module="RSTC" offset="0x400E1400"/>
</instance>
</module>
<module name="RTC" id="RTC" version="6056I">
<instance name="RTC">
<register-group address-space="base" name="RTC" name-in-module="RTC" offset="0x400E1460"/>
</instance>
</module>
<module name="RTT" id="RTT" version="6081F">
<instance name="RTT">
<register-group address-space="base" name="RTT" name-in-module="RTT" offset="0x400E1430"/>
</instance>
</module>
<module name="SPI" id="SPI" version="6088Q">
<instance name="SPI">
<register-group address-space="base" name="SPI" name-in-module="SPI" offset="0x40008000"/>
<signals>
<signal pad="PA12" function="A" group="MISO"/>
<signal pad="PA13" function="A" group="MOSI"/>
<signal pad="PA11" function="A" group="NPCS" index="0"/>
<signal pad="PA9" function="B" group="NPCS" index="1"/>
<signal pad="PA31" function="A" group="NPCS" index="1"/>
<signal pad="PB14" function="A" group="NPCS" index="1"/>
<signal pad="PC4" function="B" group="NPCS" index="1"/>
<signal pad="PA10" function="B" group="NPCS" index="2"/>
<signal pad="PA30" function="B" group="NPCS" index="2"/>
<signal pad="PB2" function="B" group="NPCS" index="2"/>
<signal pad="PC7" function="B" group="NPCS" index="2"/>
<signal pad="PA3" function="B" group="NPCS" index="3"/>
<signal pad="PA5" function="B" group="NPCS" index="3"/>
<signal pad="PA22" function="B" group="NPCS" index="3"/>
<signal pad="PA14" function="A" group="SPCK"/>
</signals>
</instance>
</module>
<module name="SUPC" id="SUPC" version="6452L">
<instance name="SUPC">
<register-group address-space="base" name="SUPC" name-in-module="SUPC" offset="0x400E1410"/>
</instance>
</module>
<module name="TC" id="TC" version="6082O">
<instance name="TC0">
<register-group address-space="base" name="TC0" name-in-module="TC" offset="0x40010000"/>
<signals>
<signal pad="PA4" function="B" group="TCLK" index="0"/>
<signal pad="PA28" function="B" group="TCLK" index="1"/>
<signal pad="PA29" function="B" group="TCLK" index="2"/>
<signal pad="PA0" function="B" group="TIOA" index="0"/>
<signal pad="PA15" function="B" group="TIOA" index="1"/>
<signal pad="PA26" function="B" group="TIOA" index="2"/>
<signal pad="PA1" function="B" group="TIOB" index="0"/>
<signal pad="PA16" function="B" group="TIOB" index="1"/>
<signal pad="PA27" function="B" group="TIOB" index="2"/>
</signals>
</instance>
</module>
<module name="TWI" id="TWI" version="6212L">
<instance name="TWI0">
<register-group address-space="base" name="TWI0" name-in-module="TWI" offset="0x40018000"/>
<signals>
<signal pad="PA4" function="A" group="TWCK" index="0"/>
<signal pad="PA3" function="A" group="TWD" index="0"/>
</signals>
</instance>
<instance name="TWI1">
<register-group address-space="base" name="TWI1" name-in-module="TWI" offset="0x4001C000"/>
<signals>
<signal pad="PB5" function="A" group="TWCK" index="1"/>
<signal pad="PB4" function="A" group="TWD" index="1"/>
</signals>
</instance>
</module>
<module name="UART" id="UART" version="6418E">
<instance name="UART0">
<register-group address-space="base" name="UART0" name-in-module="UART" offset="0x400E0600"/>
<signals>
<signal pad="PA9" function="A" group="URXD" index="0"/>
<signal pad="PA10" function="A" group="UTXD" index="0"/>
</signals>
</instance>
<instance name="UART1">
<register-group address-space="base" name="UART1" name-in-module="UART" offset="0x400E0800"/>
<signals>
<signal pad="PB2" function="A" group="URXD" index="1"/>
<signal pad="PB3" function="A" group="UTXD" index="1"/>
</signals>
</instance>
</module>
<module name="USART" id="USART" version="6089W">
<instance name="USART0">
<register-group address-space="base" name="USART0" name-in-module="USART" offset="0x40024000"/>
<signals>
<signal pad="PA8" function="A" group="CTS" index="0"/>
<signal pad="PA7" function="A" group="RTS" index="0"/>
<signal pad="PA5" function="A" group="RXD" index="0"/>
<signal pad="PA2" function="B" group="SCK" index="0"/>
<signal pad="PA6" function="A" group="TXD" index="0"/>
</signals>
</instance>
<instance name="USART1">
<register-group address-space="base" name="USART1" name-in-module="USART" offset="0x40028000"/>
<signals>
<signal pad="PA25" function="A" group="CTS" index="1"/>
<signal pad="PA24" function="A" group="RTS" index="1"/>
<signal pad="PA21" function="A" group="RXD" index="1"/>
<signal pad="PA23" function="A" group="SCK" index="1"/>
<signal pad="PA22" function="A" group="TXD" index="1"/>
</signals>
</instance>
</module>
<module name="WDT" id="WDT" version="6080B">
<instance name="WDT">
<register-group address-space="base" name="WDT" name-in-module="WDT" offset="0x400E1450"/>
</instance>
</module>
<module name="FUSES" id="FUSES" version="1">
<instance name="FUSES">
<register-group address-space="fuses" name="GPNVMBITS" name-in-module="GPNVMBITS" offset="0"/>
</instance>
</module>
<module name="LOCKBIT" id="LOCKBIT" version="1">
<instance name="LOCKBIT">
<register-group address-space="lockbits" name="LOCKBIT" name-in-module="LOCKBIT" offset="0"/>
</instance>
</module>
<module name="SystemControl">
<instance name="SystemControl">
<register-group address-space="base" offset="0xE000E000" name-in-module="SystemControl" name="SystemControl"/>
</instance>
</module>
<module name="SysTick">
<instance name="SysTick">
<register-group address-space="base" offset="0xE000E010" name-in-module="SysTick" name="SysTick"/>
</instance>
</module>
<module name="NVIC">
<instance name="NVIC">
<register-group address-space="base" offset="0xE000E100" name-in-module="NVIC" name="NVIC"/>
</instance>
</module>
</peripherals>
<interfaces>
<interface type="samjtag" name="JTAG"/>
<interface type="swd" name="SWD"/>
</interfaces>
<property-groups>
<property-group name="SIGNATURES">
<property name="JTAGID" value="0x05B2E03F"/>
<property name="CHIPID_CIDR" value="0x29450261"/>
<property name="CHIPID_EXID" value="0x0"/>
</property-group>
</property-groups>
</device>
</devices>
<modules>
<module caption="Analog-to-digital Converter" name="ADC" version="6489I">
<register-group name="ADC">
<register caption="Control Register" name="ADC_CR" offset="0x00" rw="W" size="4">
<bitfield caption="Software Reset" mask="0x00000001" name="SWRST"/>
<bitfield caption="Start Conversion" mask="0x00000002" name="START"/>
</register>
<register caption="Mode Register" name="ADC_MR" offset="0x04" rw="RW" size="4">
<bitfield caption="Trigger Enable" mask="0x00000001" name="TRGEN" values="ADC_MR__TRGEN"/>
<bitfield caption="Trigger Selection" mask="0x0000000E" name="TRGSEL" values="ADC_MR__TRGSEL"/>
<bitfield caption="Resolution" mask="0x00000010" name="LOWRES" values="ADC_MR__LOWRES"/>
<bitfield caption="Sleep Mode" mask="0x00000020" name="SLEEP" values="ADC_MR__SLEEP"/>
<bitfield caption="Fast Wake Up" mask="0x00000040" name="FWUP" values="ADC_MR__FWUP"/>
<bitfield caption="Free Run Mode" mask="0x00000080" name="FREERUN" values="ADC_MR__FREERUN"/>
<bitfield caption="Prescaler Rate Selection" mask="0x0000FF00" name="PRESCAL"/>
<bitfield caption="Start Up Time" mask="0x000F0000" name="STARTUP" values="ADC_MR__STARTUP"/>
<bitfield caption="Tracking Time" mask="0x0F000000" name="TRACKTIM"/>
<bitfield caption="Use Sequence Enable" mask="0x80000000" name="USEQ" values="ADC_MR__USEQ"/>
</register>
<register caption="Channel Sequence Register 1" name="ADC_SEQR1" offset="0x08" rw="RW" size="4">
<bitfield caption="User Sequence Number 1" mask="0x0000000F" name="USCH1"/>
<bitfield caption="User Sequence Number 2" mask="0x000000F0" name="USCH2"/>
<bitfield caption="User Sequence Number 3" mask="0x00000F00" name="USCH3"/>
<bitfield caption="User Sequence Number 4" mask="0x0000F000" name="USCH4"/>
<bitfield caption="User Sequence Number 5" mask="0x000F0000" name="USCH5"/>
<bitfield caption="User Sequence Number 6" mask="0x00F00000" name="USCH6"/>
<bitfield caption="User Sequence Number 7" mask="0x0F000000" name="USCH7"/>
<bitfield caption="User Sequence Number 8" mask="0xF0000000" name="USCH8"/>
</register>
<register caption="Channel Sequence Register 2" name="ADC_SEQR2" offset="0x0C" rw="RW" size="4">
<bitfield caption="User Sequence Number 9" mask="0x0000000F" name="USCH9"/>
<bitfield caption="User Sequence Number 10" mask="0x000000F0" name="USCH10"/>
<bitfield caption="User Sequence Number 11" mask="0x00000F00" name="USCH11"/>
<bitfield caption="User Sequence Number 12" mask="0x0000F000" name="USCH12"/>
<bitfield caption="User Sequence Number 13" mask="0x000F0000" name="USCH13"/>
<bitfield caption="User Sequence Number 14" mask="0x00F00000" name="USCH14"/>
<bitfield caption="User Sequence Number 15" mask="0x0F000000" name="USCH15"/>
<bitfield caption="User Sequence Number 16" mask="0xF0000000" name="USCH16"/>
</register>
<register caption="Channel Enable Register" name="ADC_CHER" offset="0x10" rw="W" size="4">
<bitfield caption="Channel 0 Enable" mask="0x00000001" name="CH0"/>
<bitfield caption="Channel 1 Enable" mask="0x00000002" name="CH1"/>
<bitfield caption="Channel 2 Enable" mask="0x00000004" name="CH2"/>
<bitfield caption="Channel 3 Enable" mask="0x00000008" name="CH3"/>
<bitfield caption="Channel 4 Enable" mask="0x00000010" name="CH4"/>
<bitfield caption="Channel 5 Enable" mask="0x00000020" name="CH5"/>
<bitfield caption="Channel 6 Enable" mask="0x00000040" name="CH6"/>
<bitfield caption="Channel 7 Enable" mask="0x00000080" name="CH7"/>
<bitfield caption="Channel 8 Enable" mask="0x00000100" name="CH8"/>
<bitfield caption="Channel 9 Enable" mask="0x00000200" name="CH9"/>
<bitfield caption="Channel 10 Enable" mask="0x00000400" name="CH10"/>
<bitfield caption="Channel 11 Enable" mask="0x00000800" name="CH11"/>
<bitfield caption="Channel 12 Enable" mask="0x00001000" name="CH12"/>
<bitfield caption="Channel 13 Enable" mask="0x00002000" name="CH13"/>
<bitfield caption="Channel 14 Enable" mask="0x00004000" name="CH14"/>
<bitfield caption="Channel 15 Enable" mask="0x00008000" name="CH15"/>
</register>
<register caption="Channel Disable Register" name="ADC_CHDR" offset="0x14" rw="W" size="4">
<bitfield caption="Channel 0 Disable" mask="0x00000001" name="CH0"/>
<bitfield caption="Channel 1 Disable" mask="0x00000002" name="CH1"/>
<bitfield caption="Channel 2 Disable" mask="0x00000004" name="CH2"/>
<bitfield caption="Channel 3 Disable" mask="0x00000008" name="CH3"/>
<bitfield caption="Channel 4 Disable" mask="0x00000010" name="CH4"/>
<bitfield caption="Channel 5 Disable" mask="0x00000020" name="CH5"/>
<bitfield caption="Channel 6 Disable" mask="0x00000040" name="CH6"/>
<bitfield caption="Channel 7 Disable" mask="0x00000080" name="CH7"/>
<bitfield caption="Channel 8 Disable" mask="0x00000100" name="CH8"/>
<bitfield caption="Channel 9 Disable" mask="0x00000200" name="CH9"/>
<bitfield caption="Channel 10 Disable" mask="0x00000400" name="CH10"/>
<bitfield caption="Channel 11 Disable" mask="0x00000800" name="CH11"/>
<bitfield caption="Channel 12 Disable" mask="0x00001000" name="CH12"/>
<bitfield caption="Channel 13 Disable" mask="0x00002000" name="CH13"/>
<bitfield caption="Channel 14 Disable" mask="0x00004000" name="CH14"/>
<bitfield caption="Channel 15 Disable" mask="0x00008000" name="CH15"/>
</register>
<register caption="Channel Status Register" name="ADC_CHSR" offset="0x18" rw="R" size="4">
<bitfield caption="Channel 0 Status" mask="0x00000001" name="CH0"/>
<bitfield caption="Channel 1 Status" mask="0x00000002" name="CH1"/>
<bitfield caption="Channel 2 Status" mask="0x00000004" name="CH2"/>
<bitfield caption="Channel 3 Status" mask="0x00000008" name="CH3"/>
<bitfield caption="Channel 4 Status" mask="0x00000010" name="CH4"/>
<bitfield caption="Channel 5 Status" mask="0x00000020" name="CH5"/>
<bitfield caption="Channel 6 Status" mask="0x00000040" name="CH6"/>
<bitfield caption="Channel 7 Status" mask="0x00000080" name="CH7"/>
<bitfield caption="Channel 8 Status" mask="0x00000100" name="CH8"/>
<bitfield caption="Channel 9 Status" mask="0x00000200" name="CH9"/>
<bitfield caption="Channel 10 Status" mask="0x00000400" name="CH10"/>
<bitfield caption="Channel 11 Status" mask="0x00000800" name="CH11"/>
<bitfield caption="Channel 12 Status" mask="0x00001000" name="CH12"/>
<bitfield caption="Channel 13 Status" mask="0x00002000" name="CH13"/>
<bitfield caption="Channel 14 Status" mask="0x00004000" name="CH14"/>
<bitfield caption="Channel 15 Status" mask="0x00008000" name="CH15"/>
</register>
<register caption="Last Converted Data Register" name="ADC_LCDR" offset="0x20" rw="R" size="4">
<bitfield caption="Last Data Converted" mask="0x00000FFF" name="LDATA"/>
<bitfield caption="Channel Number" mask="0x0000F000" name="CHNB"/>
</register>
<register caption="Interrupt Enable Register" name="ADC_IER" offset="0x24" rw="W" size="4">
<bitfield caption="End of Conversion Interrupt Enable 0" mask="0x00000001" name="EOC0"/>
<bitfield caption="End of Conversion Interrupt Enable 1" mask="0x00000002" name="EOC1"/>
<bitfield caption="End of Conversion Interrupt Enable 2" mask="0x00000004" name="EOC2"/>
<bitfield caption="End of Conversion Interrupt Enable 3" mask="0x00000008" name="EOC3"/>
<bitfield caption="End of Conversion Interrupt Enable 4" mask="0x00000010" name="EOC4"/>
<bitfield caption="End of Conversion Interrupt Enable 5" mask="0x00000020" name="EOC5"/>
<bitfield caption="End of Conversion Interrupt Enable 6" mask="0x00000040" name="EOC6"/>
<bitfield caption="End of Conversion Interrupt Enable 7" mask="0x00000080" name="EOC7"/>
<bitfield caption="End of Conversion Interrupt Enable 8" mask="0x00000100" name="EOC8"/>
<bitfield caption="End of Conversion Interrupt Enable 9" mask="0x00000200" name="EOC9"/>
<bitfield caption="End of Conversion Interrupt Enable 10" mask="0x00000400" name="EOC10"/>
<bitfield caption="End of Conversion Interrupt Enable 11" mask="0x00000800" name="EOC11"/>
<bitfield caption="End of Conversion Interrupt Enable 12" mask="0x00001000" name="EOC12"/>
<bitfield caption="End of Conversion Interrupt Enable 13" mask="0x00002000" name="EOC13"/>
<bitfield caption="End of Conversion Interrupt Enable 14" mask="0x00004000" name="EOC14"/>
<bitfield caption="End of Conversion Interrupt Enable 15" mask="0x00008000" name="EOC15"/>
<bitfield caption="Data Ready Interrupt Enable" mask="0x01000000" name="DRDY"/>
<bitfield caption="General Overrun Error Interrupt Enable" mask="0x02000000" name="GOVRE"/>
<bitfield caption="Comparison Event Interrupt Enable" mask="0x04000000" name="COMPE"/>
<bitfield caption="End of Receive Buffer Interrupt Enable" mask="0x08000000" name="ENDRX"/>
<bitfield caption="Receive Buffer Full Interrupt Enable" mask="0x10000000" name="RXBUFF"/>
</register>
<register caption="Interrupt Disable Register" name="ADC_IDR" offset="0x28" rw="W" size="4">
<bitfield caption="End of Conversion Interrupt Disable 0" mask="0x00000001" name="EOC0"/>
<bitfield caption="End of Conversion Interrupt Disable 1" mask="0x00000002" name="EOC1"/>
<bitfield caption="End of Conversion Interrupt Disable 2" mask="0x00000004" name="EOC2"/>
<bitfield caption="End of Conversion Interrupt Disable 3" mask="0x00000008" name="EOC3"/>
<bitfield caption="End of Conversion Interrupt Disable 4" mask="0x00000010" name="EOC4"/>
<bitfield caption="End of Conversion Interrupt Disable 5" mask="0x00000020" name="EOC5"/>
<bitfield caption="End of Conversion Interrupt Disable 6" mask="0x00000040" name="EOC6"/>
<bitfield caption="End of Conversion Interrupt Disable 7" mask="0x00000080" name="EOC7"/>
<bitfield caption="End of Conversion Interrupt Disable 8" mask="0x00000100" name="EOC8"/>
<bitfield caption="End of Conversion Interrupt Disable 9" mask="0x00000200" name="EOC9"/>
<bitfield caption="End of Conversion Interrupt Disable 10" mask="0x00000400" name="EOC10"/>
<bitfield caption="End of Conversion Interrupt Disable 11" mask="0x00000800" name="EOC11"/>
<bitfield caption="End of Conversion Interrupt Disable 12" mask="0x00001000" name="EOC12"/>
<bitfield caption="End of Conversion Interrupt Disable 13" mask="0x00002000" name="EOC13"/>
<bitfield caption="End of Conversion Interrupt Disable 14" mask="0x00004000" name="EOC14"/>
<bitfield caption="End of Conversion Interrupt Disable 15" mask="0x00008000" name="EOC15"/>
<bitfield caption="Data Ready Interrupt Disable" mask="0x01000000" name="DRDY"/>
<bitfield caption="General Overrun Error Interrupt Disable" mask="0x02000000" name="GOVRE"/>
<bitfield caption="Comparison Event Interrupt Disable" mask="0x04000000" name="COMPE"/>
<bitfield caption="End of Receive Buffer Interrupt Disable" mask="0x08000000" name="ENDRX"/>
<bitfield caption="Receive Buffer Full Interrupt Disable" mask="0x10000000" name="RXBUFF"/>
</register>
<register caption="Interrupt Mask Register" name="ADC_IMR" offset="0x2C" rw="R" size="4">
<bitfield caption="End of Conversion Interrupt Mask 0" mask="0x00000001" name="EOC0"/>
<bitfield caption="End of Conversion Interrupt Mask 1" mask="0x00000002" name="EOC1"/>
<bitfield caption="End of Conversion Interrupt Mask 2" mask="0x00000004" name="EOC2"/>
<bitfield caption="End of Conversion Interrupt Mask 3" mask="0x00000008" name="EOC3"/>
<bitfield caption="End of Conversion Interrupt Mask 4" mask="0x00000010" name="EOC4"/>
<bitfield caption="End of Conversion Interrupt Mask 5" mask="0x00000020" name="EOC5"/>
<bitfield caption="End of Conversion Interrupt Mask 6" mask="0x00000040" name="EOC6"/>
<bitfield caption="End of Conversion Interrupt Mask 7" mask="0x00000080" name="EOC7"/>
<bitfield caption="End of Conversion Interrupt Mask 8" mask="0x00000100" name="EOC8"/>
<bitfield caption="End of Conversion Interrupt Mask 9" mask="0x00000200" name="EOC9"/>
<bitfield caption="End of Conversion Interrupt Mask 10" mask="0x00000400" name="EOC10"/>
<bitfield caption="End of Conversion Interrupt Mask 11" mask="0x00000800" name="EOC11"/>
<bitfield caption="End of Conversion Interrupt Mask 12" mask="0x00001000" name="EOC12"/>
<bitfield caption="End of Conversion Interrupt Mask 13" mask="0x00002000" name="EOC13"/>
<bitfield caption="End of Conversion Interrupt Mask 14" mask="0x00004000" name="EOC14"/>
<bitfield caption="End of Conversion Interrupt Mask 15" mask="0x00008000" name="EOC15"/>
<bitfield caption="Data Ready Interrupt Mask" mask="0x01000000" name="DRDY"/>
<bitfield caption="General Overrun Error Interrupt Mask" mask="0x02000000" name="GOVRE"/>
<bitfield caption="Comparison Event Interrupt Mask" mask="0x04000000" name="COMPE"/>
<bitfield caption="End of Receive Buffer Interrupt Mask" mask="0x08000000" name="ENDRX"/>
<bitfield caption="Receive Buffer Full Interrupt Mask" mask="0x10000000" name="RXBUFF"/>
</register>
<register caption="Interrupt Status Register" name="ADC_ISR" offset="0x30" rw="R" size="4">
<bitfield caption="End of Conversion 0" mask="0x00000001" name="EOC0"/>
<bitfield caption="End of Conversion 1" mask="0x00000002" name="EOC1"/>
<bitfield caption="End of Conversion 2" mask="0x00000004" name="EOC2"/>
<bitfield caption="End of Conversion 3" mask="0x00000008" name="EOC3"/>
<bitfield caption="End of Conversion 4" mask="0x00000010" name="EOC4"/>
<bitfield caption="End of Conversion 5" mask="0x00000020" name="EOC5"/>
<bitfield caption="End of Conversion 6" mask="0x00000040" name="EOC6"/>
<bitfield caption="End of Conversion 7" mask="0x00000080" name="EOC7"/>
<bitfield caption="End of Conversion 8" mask="0x00000100" name="EOC8"/>
<bitfield caption="End of Conversion 9" mask="0x00000200" name="EOC9"/>
<bitfield caption="End of Conversion 10" mask="0x00000400" name="EOC10"/>
<bitfield caption="End of Conversion 11" mask="0x00000800" name="EOC11"/>
<bitfield caption="End of Conversion 12" mask="0x00001000" name="EOC12"/>
<bitfield caption="End of Conversion 13" mask="0x00002000" name="EOC13"/>
<bitfield caption="End of Conversion 14" mask="0x00004000" name="EOC14"/>
<bitfield caption="End of Conversion 15" mask="0x00008000" name="EOC15"/>
<bitfield caption="Data Ready" mask="0x01000000" name="DRDY"/>
<bitfield caption="General Overrun Error" mask="0x02000000" name="GOVRE"/>
<bitfield caption="Comparison Error" mask="0x04000000" name="COMPE"/>
<bitfield caption="End of RX Buffer" mask="0x08000000" name="ENDRX"/>
<bitfield caption="RX Buffer Full" mask="0x10000000" name="RXBUFF"/>
</register>
<register caption="Overrun Status Register" name="ADC_OVER" offset="0x3C" rw="R" size="4">
<bitfield caption="Overrun Error 0" mask="0x00000001" name="OVRE0"/>
<bitfield caption="Overrun Error 1" mask="0x00000002" name="OVRE1"/>
<bitfield caption="Overrun Error 2" mask="0x00000004" name="OVRE2"/>
<bitfield caption="Overrun Error 3" mask="0x00000008" name="OVRE3"/>
<bitfield caption="Overrun Error 4" mask="0x00000010" name="OVRE4"/>
<bitfield caption="Overrun Error 5" mask="0x00000020" name="OVRE5"/>
<bitfield caption="Overrun Error 6" mask="0x00000040" name="OVRE6"/>
<bitfield caption="Overrun Error 7" mask="0x00000080" name="OVRE7"/>
<bitfield caption="Overrun Error 8" mask="0x00000100" name="OVRE8"/>
<bitfield caption="Overrun Error 9" mask="0x00000200" name="OVRE9"/>
<bitfield caption="Overrun Error 10" mask="0x00000400" name="OVRE10"/>
<bitfield caption="Overrun Error 11" mask="0x00000800" name="OVRE11"/>
<bitfield caption="Overrun Error 12" mask="0x00001000" name="OVRE12"/>
<bitfield caption="Overrun Error 13" mask="0x00002000" name="OVRE13"/>
<bitfield caption="Overrun Error 14" mask="0x00004000" name="OVRE14"/>
<bitfield caption="Overrun Error 15" mask="0x00008000" name="OVRE15"/>
</register>
<register caption="Extended Mode Register" name="ADC_EMR" offset="0x40" rw="RW" size="4">
<bitfield caption="Comparison Mode" mask="0x00000003" name="CMPMODE" values="ADC_EMR__CMPMODE"/>
<bitfield caption="Comparison Selected Channel" mask="0x000000F0" name="CMPSEL"/>
<bitfield caption="Compare All Channels" mask="0x00000200" name="CMPALL"/>
<bitfield caption="TAG of ADC_LDCR register" mask="0x01000000" name="TAG"/>
</register>
<register caption="Compare Window Register" name="ADC_CWR" offset="0x44" rw="RW" size="4">
<bitfield caption="Low Threshold" mask="0x00000FFF" name="LOWTHRES"/>
<bitfield caption="High Threshold" mask="0x0FFF0000" name="HIGHTHRES"/>
</register>
<register caption="Channel Data Register 0" name="ADC_CDR0" offset="0x50" rw="R" size="4">
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
</register>
<register caption="Channel Data Register 1" name="ADC_CDR1" offset="0x54" rw="R" size="4">
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
</register>
<register caption="Channel Data Register 2" name="ADC_CDR2" offset="0x58" rw="R" size="4">
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
</register>
<register caption="Channel Data Register 3" name="ADC_CDR3" offset="0x5C" rw="R" size="4">
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
</register>
<register caption="Channel Data Register 4" name="ADC_CDR4" offset="0x60" rw="R" size="4">
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
</register>
<register caption="Channel Data Register 5" name="ADC_CDR5" offset="0x64" rw="R" size="4">
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
</register>
<register caption="Channel Data Register 6" name="ADC_CDR6" offset="0x68" rw="R" size="4">
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
</register>
<register caption="Channel Data Register 7" name="ADC_CDR7" offset="0x6C" rw="R" size="4">
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
</register>
<register caption="Channel Data Register 8" name="ADC_CDR8" offset="0x70" rw="R" size="4">
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
</register>
<register caption="Channel Data Register 9" name="ADC_CDR9" offset="0x74" rw="R" size="4">
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
</register>
<register caption="Channel Data Register 10" name="ADC_CDR10" offset="0x78" rw="R" size="4">
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
</register>
<register caption="Channel Data Register 11" name="ADC_CDR11" offset="0x7C" rw="R" size="4">
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
</register>
<register caption="Channel Data Register 12" name="ADC_CDR12" offset="0x80" rw="R" size="4">
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
</register>
<register caption="Channel Data Register 13" name="ADC_CDR13" offset="0x84" rw="R" size="4">
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
</register>
<register caption="Channel Data Register 14" name="ADC_CDR14" offset="0x88" rw="R" size="4">
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
</register>
<register caption="Channel Data Register 15" name="ADC_CDR15" offset="0x8C" rw="R" size="4">
<bitfield caption="Converted Data" mask="0x00000FFF" name="DATA"/>
</register>
<register caption="Write Protect Mode Register" name="ADC_WPMR" offset="0xE4" rw="RW" size="4">
<bitfield caption="Write Protect Enable" mask="0x00000001" name="WPEN"/>
<bitfield caption="Write Protect KEY" mask="0xFFFFFF00" name="WPKEY"/>
</register>
<register caption="Write Protect Status Register" name="ADC_WPSR" offset="0xE8" rw="R" size="4">
<bitfield caption="Write Protect Violation Status" mask="0x00000001" name="WPVS"/>
<bitfield caption="Write Protect Violation Source" mask="0x00FFFF00" name="WPVSRC"/>
</register>
<register caption="Receive Pointer Register" name="ADC_RPR" offset="0x100" rw="RW" size="4">
<bitfield caption="Receive Pointer Register" mask="0xFFFFFFFF" name="RXPTR"/>
</register>
<register caption="Receive Counter Register" name="ADC_RCR" offset="0x104" rw="RW" size="4">
<bitfield caption="Receive Counter Register" mask="0x0000FFFF" name="RXCTR"/>
</register>
<register caption="Receive Next Pointer Register" name="ADC_RNPR" offset="0x110" rw="RW" size="4">
<bitfield caption="Receive Next Pointer" mask="0xFFFFFFFF" name="RXNPTR"/>
</register>
<register caption="Receive Next Counter Register" name="ADC_RNCR" offset="0x114" rw="RW" size="4">
<bitfield caption="Receive Next Counter" mask="0x0000FFFF" name="RXNCTR"/>
</register>
<register caption="Transfer Control Register" name="ADC_PTCR" offset="0x120" rw="W" size="4">
<bitfield caption="Receiver Transfer Enable" mask="0x00000001" name="RXTEN"/>
<bitfield caption="Receiver Transfer Disable" mask="0x00000002" name="RXTDIS"/>
<bitfield caption="Transmitter Transfer Enable" mask="0x00000100" name="TXTEN"/>
<bitfield caption="Transmitter Transfer Disable" mask="0x00000200" name="TXTDIS"/>
</register>
<register caption="Transfer Status Register" name="ADC_PTSR" offset="0x124" rw="R" size="4">
<bitfield caption="Receiver Transfer Enable" mask="0x00000001" name="RXTEN"/>
<bitfield caption="Transmitter Transfer Enable" mask="0x00000100" name="TXTEN"/>
</register>
</register-group>
<value-group caption="" name="ADC_MR__TRGEN">
<value caption="Hardware triggers are disabled. Starting a conversion is only possible by software." name="DIS" value="0"/>
<value caption="Hardware trigger selected by TRGSEL field is enabled." name="EN" value="1"/>
</value-group>
<value-group caption="" name="ADC_MR__TRGSEL">
<value caption="External trigger" name="ADC_TRIG0" value="0x0"/>
<value caption="TIO Output of the Timer Counter Channel 0" name="ADC_TRIG1" value="0x1"/>
<value caption="TIO Output of the Timer Counter Channel 1" name="ADC_TRIG2" value="0x2"/>
<value caption="TIO Output of the Timer Counter Channel 2" name="ADC_TRIG3" value="0x3"/>
</value-group>
<value-group caption="" name="ADC_MR__LOWRES">
<value caption="10-bit resolution" name="BITS_10" value="0"/>
<value caption="8-bit resolution" name="BITS_8" value="1"/>
</value-group>
<value-group caption="" name="ADC_MR__SLEEP">
<value caption="Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions" name="NORMAL" value="0"/>
<value caption="Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions" name="SLEEP" value="1"/>
</value-group>
<value-group caption="" name="ADC_MR__FWUP">
<value caption="Normal Sleep Mode: The sleep mode is defined by the SLEEP bit" name="OFF" value="0"/>
<value caption="Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF" name="ON" value="1"/>
</value-group>
<value-group caption="" name="ADC_MR__FREERUN">
<value caption="Normal Mode" name="OFF" value="0"/>
<value caption="Free Run Mode: Never wait for any trigger." name="ON" value="1"/>
</value-group>
<value-group caption="" name="ADC_MR__STARTUP">
<value caption="0 periods of ADCClock" name="SUT0" value="0x0"/>
<value caption="8 periods of ADCClock" name="SUT8" value="0x1"/>
<value caption="16 periods of ADCClock" name="SUT16" value="0x2"/>
<value caption="24 periods of ADCClock" name="SUT24" value="0x3"/>
<value caption="64 periods of ADCClock" name="SUT64" value="0x4"/>
<value caption="80 periods of ADCClock" name="SUT80" value="0x5"/>
<value caption="96 periods of ADCClock" name="SUT96" value="0x6"/>
<value caption="112 periods of ADCClock" name="SUT112" value="0x7"/>
<value caption="512 periods of ADCClock" name="SUT512" value="0x8"/>
<value caption="576 periods of ADCClock" name="SUT576" value="0x9"/>
<value caption="640 periods of ADCClock" name="SUT640" value="0xA"/>
<value caption="704 periods of ADCClock" name="SUT704" value="0xB"/>
<value caption="768 periods of ADCClock" name="SUT768" value="0xC"/>
<value caption="832 periods of ADCClock" name="SUT832" value="0xD"/>
<value caption="896 periods of ADCClock" name="SUT896" value="0xE"/>
<value caption="960 periods of ADCClock" name="SUT960" value="0xF"/>
</value-group>
<value-group caption="" name="ADC_MR__USEQ">
<value caption="Normal Mode: The controller converts channels in a simple numeric order." name="NUM_ORDER" value="0"/>
<value caption="User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers." name="REG_ORDER" value="1"/>
</value-group>
<value-group caption="" name="ADC_EMR__CMPMODE">
<value caption="Generates an event when the converted data is lower than the low threshold of the window." name="LOW" value="0x0"/>
<value caption="Generates an event when the converted data is higher than the high threshold of the window." name="HIGH" value="0x1"/>
<value caption="Generates an event when the converted data is in the comparison window." name="IN" value="0x2"/>
<value caption="Generates an event when the converted data is out of the comparison window." name="OUT" value="0x3"/>
</value-group>
</module>
<module caption="Chip Identifier" name="CHIPID" version="6417K">
<register-group name="CHIPID">
<register caption="Chip ID Register" name="CHIPID_CIDR" offset="0x0" rw="R" size="4">
<bitfield caption="Version of the Device" mask="0x0000001F" name="VERSION"/>
<bitfield caption="Embedded Processor" mask="0x000000E0" name="EPROC" values="CHIPID_CIDR__EPROC"/>
<bitfield caption="Nonvolatile Program Memory Size" mask="0x00000F00" name="NVPSIZ" values="CHIPID_CIDR__NVPSIZ"/>
<bitfield caption="Second Nonvolatile Program Memory Size" mask="0x0000F000" name="NVPSIZ2" values="CHIPID_CIDR__NVPSIZ2"/>
<bitfield caption="Internal SRAM Size" mask="0x000F0000" name="SRAMSIZ" values="CHIPID_CIDR__SRAMSIZ"/>
<bitfield caption="Architecture Identifier" mask="0x0FF00000" name="ARCH" values="CHIPID_CIDR__ARCH"/>
<bitfield caption="Nonvolatile Program Memory Type" mask="0x70000000" name="NVPTYP" values="CHIPID_CIDR__NVPTYP"/>
<bitfield caption="Extension Flag" mask="0x80000000" name="EXT"/>
</register>
<register caption="Chip ID Extension Register" name="CHIPID_EXID" offset="0x4" rw="R" size="4">
<bitfield caption="Chip ID Extension" mask="0xFFFFFFFF" name="EXID"/>
</register>
</register-group>
<value-group caption="" name="CHIPID_CIDR__EPROC">
<value caption="ARM946ES" name="ARM946ES" value="0x1"/>
<value caption="ARM7TDMI" name="ARM7TDMI" value="0x2"/>
<value caption="Cortex-M3" name="CM3" value="0x3"/>
<value caption="ARM920T" name="ARM920T" value="0x4"/>
<value caption="ARM926EJS" name="ARM926EJS" value="0x5"/>
<value caption="Cortex-A5" name="CA5" value="0x6"/>
<value caption="Cortex-M4" name="CM4" value="0x7"/>
</value-group>
<value-group caption="" name="CHIPID_CIDR__NVPSIZ">
<value caption="None" name="NONE" value="0x0"/>
<value caption="8K bytes" name="_8K" value="0x1"/>
<value caption="16K bytes" name="_16K" value="0x2"/>
<value caption="32K bytes" name="_32K" value="0x3"/>
<value caption="64K bytes" name="_64K" value="0x5"/>
<value caption="128K bytes" name="_128K" value="0x7"/>
<value caption="256K bytes" name="_256K" value="0x9"/>
<value caption="512K bytes" name="_512K" value="0xA"/>
<value caption="1024K bytes" name="_1024K" value="0xC"/>
<value caption="2048K bytes" name="_2048K" value="0xE"/>
</value-group>
<value-group caption="" name="CHIPID_CIDR__NVPSIZ2">
<value caption="None" name="NONE" value="0x0"/>
<value caption="8K bytes" name="_8K" value="0x1"/>
<value caption="16K bytes" name="_16K" value="0x2"/>
<value caption="32K bytes" name="_32K" value="0x3"/>
<value caption="64K bytes" name="_64K" value="0x5"/>
<value caption="128K bytes" name="_128K" value="0x7"/>
<value caption="256K bytes" name="_256K" value="0x9"/>
<value caption="512K bytes" name="_512K" value="0xA"/>
<value caption="1024K bytes" name="_1024K" value="0xC"/>
<value caption="2048K bytes" name="_2048K" value="0xE"/>
</value-group>
<value-group caption="" name="CHIPID_CIDR__SRAMSIZ">
<value caption="48K bytes" name="_48K" value="0x0"/>
<value caption="1K bytes" name="_1K" value="0x1"/>
<value caption="2K bytes" name="_2K" value="0x2"/>
<value caption="6K bytes" name="_6K" value="0x3"/>
<value caption="24K bytes" name="_24K" value="0x4"/>
<value caption="4K bytes" name="_4K" value="0x5"/>
<value caption="80K bytes" name="_80K" value="0x6"/>
<value caption="160K bytes" name="_160K" value="0x7"/>
<value caption="8K bytes" name="_8K" value="0x8"/>
<value caption="16K bytes" name="_16K" value="0x9"/>
<value caption="32K bytes" name="_32K" value="0xA"/>
<value caption="64K bytes" name="_64K" value="0xB"/>
<value caption="128K bytes" name="_128K" value="0xC"/>
<value caption="256K bytes" name="_256K" value="0xD"/>
<value caption="96K bytes" name="_96K" value="0xE"/>
<value caption="512K bytes" name="_512K" value="0xF"/>
</value-group>
<value-group caption="" name="CHIPID_CIDR__ARCH">
<value caption="AT91SAM9xx Series" name="AT91SAM9xx" value="0x19"/>
<value caption="AT91SAM9XExx Series" name="AT91SAM9XExx" value="0x29"/>
<value caption="AT91x34 Series" name="AT91x34" value="0x34"/>
<value caption="CAP7 Series" name="CAP7" value="0x37"/>
<value caption="CAP9 Series" name="CAP9" value="0x39"/>
<value caption="CAP11 Series" name="CAP11" value="0x3B"/>
<value caption="AT91x40 Series" name="AT91x40" value="0x40"/>
<value caption="AT91x42 Series" name="AT91x42" value="0x42"/>
<value caption="AT91x55 Series" name="AT91x55" value="0x55"/>
<value caption="AT91SAM7Axx Series" name="AT91SAM7Axx" value="0x60"/>
<value caption="AT91SAM7AQxx Series" name="AT91SAM7AQxx" value="0x61"/>
<value caption="AT91x63 Series" name="AT91x63" value="0x63"/>
<value caption="AT91SAM7Sxx Series" name="AT91SAM7Sxx" value="0x70"/>
<value caption="AT91SAM7XCxx Series" name="AT91SAM7XCxx" value="0x71"/>
<value caption="AT91SAM7SExx Series" name="AT91SAM7SExx" value="0x72"/>
<value caption="AT91SAM7Lxx Series" name="AT91SAM7Lxx" value="0x73"/>
<value caption="AT91SAM7Xxx Series" name="AT91SAM7Xxx" value="0x75"/>
<value caption="AT91SAM7SLxx Series" name="AT91SAM7SLxx" value="0x76"/>
<value caption="SAM3UxC Series (100-pin version)" name="SAM3UxC" value="0x80"/>
<value caption="SAM3UxE Series (144-pin version)" name="SAM3UxE" value="0x81"/>
<value caption="SAM3AxC Series (100-pin version)" name="SAM3AxC" value="0x83"/>
<value caption="SAM4AxC Series (100-pin version)" name="SAM4AxC" value="0x83"/>
<value caption="SAM3XxC Series (100-pin version)" name="SAM3XxC" value="0x84"/>
<value caption="SAM4XxC Series (100-pin version)" name="SAM4XxC" value="0x84"/>
<value caption="SAM3XxE Series (144-pin version)" name="SAM3XxE" value="0x85"/>
<value caption="SAM4XxE Series (144-pin version)" name="SAM4XxE" value="0x85"/>
<value caption="SAM3XxG Series (208/217-pin version)" name="SAM3XxG" value="0x86"/>
<value caption="SAM4XxG Series (208/217-pin version)" name="SAM4XxG" value="0x86"/>
<value caption="SAM3SxASeries (48-pin version)" name="SAM3SxA" value="0x88"/>
<value caption="SAM4SxA Series (48-pin version)" name="SAM4SxA" value="0x88"/>
<value caption="SAM3SxB Series (64-pin version)" name="SAM3SxB" value="0x89"/>
<value caption="SAM4SxB Series (64-pin version)" name="SAM4SxB" value="0x89"/>
<value caption="SAM3SxC Series (100-pin version)" name="SAM3SxC" value="0x8A"/>
<value caption="SAM4SxC Series (100-pin version)" name="SAM4SxC" value="0x8A"/>
<value caption="AT91x92 Series" name="AT91x92" value="0x92"/>
<value caption="SAM3NxA Series (48-pin version)" name="SAM3NxA" value="0x93"/>
<value caption="SAM3NxB Series (64-pin version)" name="SAM3NxB" value="0x94"/>
<value caption="SAM3NxC Series (100-pin version)" name="SAM3NxC" value="0x95"/>
<value caption="SAM3SDxB Series (64-pin version)" name="SAM3SDxB" value="0x99"/>
<value caption="SAM3SDxC Series (100-pin version)" name="SAM3SDxC" value="0x9A"/>
<value caption="SAM5A" name="SAM5A" value="0xA5"/>
<value caption="AT75Cxx Series" name="AT75Cxx" value="0xF0"/>
</value-group>
<value-group caption="" name="CHIPID_CIDR__NVPTYP">
<value caption="ROM" name="ROM" value="0x0"/>
<value caption="ROMless or on-chip Flash" name="ROMLESS" value="0x1"/>
<value caption="Embedded Flash Memory" name="FLASH" value="0x2"/>
<value caption="ROM and Embedded Flash MemoryNVPSIZ is ROM size NVPSIZ2 is Flash size" name="ROM_FLASH" value="0x3"/>
<value caption="SRAM emulating ROM" name="SRAM" value="0x4"/>
</value-group>
</module>
<module caption="Digital-to-Analog Converter Controller" name="DACC" version="11025A">
<register-group name="DACC">
<register caption="Control Register" name="DACC_CR" offset="0x00" rw="W" size="4">
<bitfield caption="Software Reset" mask="0x00000001" name="SWRST"/>
</register>
<register caption="Mode Register" name="DACC_MR" offset="0x04" rw="RW" size="4">
<bitfield caption="Trigger Enable" mask="0x00000001" name="TRGEN"/>
<bitfield caption="Trigger Selection" mask="0x0000000E" name="TRGSEL" values="DACC_MR__TRGSEL"/>
<bitfield caption="DAC enable" mask="0x00000010" name="DACEN"/>
<bitfield caption="Word Transfer" mask="0x00000020" name="WORD"/>
<bitfield caption="Startup Time Selection" mask="0x0000FF00" name="STARTUP"/>
<bitfield caption="DAC Clock Divider for Internal Trigger" mask="0xFFFF0000" name="CLKDIV"/>
</register>
<register caption="Conversion Data Register" name="DACC_CDR" offset="0x08" rw="W" size="4">
<bitfield caption="Data to Convert" mask="0xFFFFFFFF" name="DATA"/>
</register>
<register caption="Interrupt Enable Register" name="DACC_IER" offset="0x0C" rw="W" size="4">
<bitfield caption="Transmission Ready Interrupt Enable" mask="0x00000001" name="TXRDY"/>
<bitfield caption="End of PDC Interrupt Enable" mask="0x00000002" name="ENDTX"/>
<bitfield caption="Buffer Empty Interrupt Enable" mask="0x00000004" name="TXBUFE"/>
</register>
<register caption="Interrupt Disable Register" name="DACC_IDR" offset="0x10" rw="W" size="4">
<bitfield caption="Transmission Ready Interrupt Disable" mask="0x00000001" name="TXRDY"/>
<bitfield caption="End of PDC Interrupt Disable" mask="0x00000002" name="ENDTX"/>
<bitfield caption="Buffer Empty Interrupt Disable" mask="0x00000004" name="TXBUFE"/>
</register>
<register caption="Interrupt Mask Register" name="DACC_IMR" offset="0x14" rw="R" size="4">
<bitfield caption="Transmission Ready Interrupt Mask" mask="0x00000001" name="TXRDY"/>
<bitfield caption="End of PDC Interrupt Mask" mask="0x00000002" name="ENDTX"/>
<bitfield caption="Buffer Empty Interrupt Mask" mask="0x00000004" name="TXBUFE"/>
</register>
<register caption="Interrupt Status Register" name="DACC_ISR" offset="0x18" rw="R" size="4">
<bitfield caption="Transmission Ready Interrupt Flag" mask="0x00000001" name="TXRDY"/>
<bitfield caption="End of PDC Interrupt Flag" mask="0x00000002" name="ENDTX"/>
<bitfield caption="Buffer Empty Interrupt Flag" mask="0x00000004" name="TXBUFE"/>
</register>
<register caption="Write Protect Mode Register" name="DACC_WPMR" offset="0xE4" rw="RW" size="4">
<bitfield caption="Write Protect Enable" mask="0x00000001" name="WPEN"/>
<bitfield caption="Write Protect KEY" mask="0xFFFFFF00" name="WPKEY"/>
</register>
<register caption="Write Protect Status Register" name="DACC_WPSR" offset="0xE8" rw="R" size="4">
<bitfield caption="Write protection error" mask="0x00000001" name="WPROTERR"/>
<bitfield caption="Write protection error address" mask="0x0000FF00" name="WPROTADDR"/>
</register>
<register caption="Transmit Pointer Register" name="DACC_TPR" offset="0x108" rw="RW" size="4">
<bitfield caption="Transmit Counter Register" mask="0xFFFFFFFF" name="TXPTR"/>
</register>
<register caption="Transmit Counter Register" name="DACC_TCR" offset="0x10C" rw="RW" size="4">
<bitfield caption="Transmit Counter Register" mask="0x0000FFFF" name="TXCTR"/>
</register>
<register caption="Transmit Next Pointer Register" name="DACC_TNPR" offset="0x118" rw="RW" size="4">
<bitfield caption="Transmit Next Pointer" mask="0xFFFFFFFF" name="TXNPTR"/>
</register>
<register caption="Transmit Next Counter Register" name="DACC_TNCR" offset="0x11C" rw="RW" size="4">
<bitfield caption="Transmit Counter Next" mask="0x0000FFFF" name="TXNCTR"/>
</register>
<register caption="Transfer Control Register" name="DACC_PTCR" offset="0x120" rw="W" size="4">
<bitfield caption="Receiver Transfer Enable" mask="0x00000001" name="RXTEN"/>
<bitfield caption="Receiver Transfer Disable" mask="0x00000002" name="RXTDIS"/>
<bitfield caption="Transmitter Transfer Enable" mask="0x00000100" name="TXTEN"/>
<bitfield caption="Transmitter Transfer Disable" mask="0x00000200" name="TXTDIS"/>
</register>
<register caption="Transfer Status Register" name="DACC_PTSR" offset="0x124" rw="R" size="4">
<bitfield caption="Receiver Transfer Enable" mask="0x00000001" name="RXTEN"/>
<bitfield caption="Transmitter Transfer Enable" mask="0x00000100" name="TXTEN"/>
</register>
</register-group>
<value-group caption="" name="DACC_MR__TRGSEL">
<value caption="External trigger" name="TRGSEL0" value="0x0"/>
<value caption="TIO Output of the Timer Counter Channel 0" name="TRGSEL1" value="0x1"/>
<value caption="TIO Output of the Timer Counter Channel 1" name="TRGSEL2" value="0x2"/>
<value caption="TIO Output of the Timer Counter Channel 2" name="TRGSEL3" value="0x3"/>
</value-group>
</module>
<module caption="Embedded Flash Controller" name="EFC" version="6450E">
<register-group name="EFC">
<register caption="EEFC Flash Mode Register" name="EEFC_FMR" offset="0x00" rw="RW" size="4">
<bitfield caption="Ready Interrupt Enable" mask="0x00000001" name="FRDY"/>
<bitfield caption="Flash Wait State" mask="0x00000F00" name="FWS"/>
<bitfield caption="Sequential Code Optimization Disable" mask="0x00010000" name="SCOD"/>
<bitfield caption="Flash Access Mode" mask="0x01000000" name="FAM"/>
</register>
<register caption="EEFC Flash Command Register" name="EEFC_FCR" offset="0x04" rw="W" size="4">
<bitfield caption="Flash Command" mask="0x000000FF" name="FCMD"/>
<bitfield caption="Flash Command Argument" mask="0x00FFFF00" name="FARG"/>
<bitfield caption="Flash Writing Protection Key" mask="0xFF000000" name="FKEY"/>
</register>
<register caption="EEFC Flash Status Register" name="EEFC_FSR" offset="0x08" rw="R" size="4">
<bitfield caption="Flash Ready Status" mask="0x00000001" name="FRDY"/>
<bitfield caption="Flash Command Error Status" mask="0x00000002" name="FCMDE"/>
<bitfield caption="Flash Lock Error Status" mask="0x00000004" name="FLOCKE"/>
</register>
<register caption="EEFC Flash Result Register" name="EEFC_FRR" offset="0x0C" rw="R" size="4">
<bitfield caption="Flash Result Value" mask="0xFFFFFFFF" name="FVALUE"/>
</register>
</register-group>
</module>
<module caption="General Purpose Backup Register" name="GPBR" version="6378C">
<register-group name="GPBR">
<register caption="General Purpose Backup Register 0" name="SYS_GPBR0" offset="0x0" rw="RW" size="4">
<bitfield caption="Value of GPBR x" mask="0xFFFFFFFF" name="GPBR_VALUE"/>
</register>
<register caption="General Purpose Backup Register 1" name="SYS_GPBR1" offset="0x4" rw="RW" size="4">
<bitfield caption="Value of GPBR x" mask="0xFFFFFFFF" name="GPBR_VALUE"/>
</register>
<register caption="General Purpose Backup Register 2" name="SYS_GPBR2" offset="0x8" rw="RW" size="4">
<bitfield caption="Value of GPBR x" mask="0xFFFFFFFF" name="GPBR_VALUE"/>
</register>
<register caption="General Purpose Backup Register 3" name="SYS_GPBR3" offset="0xC" rw="RW" size="4">
<bitfield caption="Value of GPBR x" mask="0xFFFFFFFF" name="GPBR_VALUE"/>
</register>
<register caption="General Purpose Backup Register 4" name="SYS_GPBR4" offset="0x10" rw="RW" size="4">
<bitfield caption="Value of GPBR x" mask="0xFFFFFFFF" name="GPBR_VALUE"/>
</register>
<register caption="General Purpose Backup Register 5" name="SYS_GPBR5" offset="0x14" rw="RW" size="4">
<bitfield caption="Value of GPBR x" mask="0xFFFFFFFF" name="GPBR_VALUE"/>
</register>
<register caption="General Purpose Backup Register 6" name="SYS_GPBR6" offset="0x18" rw="RW" size="4">
<bitfield caption="Value of GPBR x" mask="0xFFFFFFFF" name="GPBR_VALUE"/>
</register>
<register caption="General Purpose Backup Register 7" name="SYS_GPBR7" offset="0x1C" rw="RW" size="4">
<bitfield caption="Value of GPBR x" mask="0xFFFFFFFF" name="GPBR_VALUE"/>
</register>
</register-group>
</module>
<module caption="AHB Bus Matrix" name="MATRIX" version="11049A">
<register-group name="MATRIX">
<register caption="Master Configuration Register 0" name="MATRIX_MCFG0" offset="0x0" rw="RW" size="4">
<bitfield caption="Undefined Length Burst Type" mask="0x00000007" name="ULBT"/>
</register>
<register caption="Master Configuration Register 1" name="MATRIX_MCFG1" offset="0x4" rw="RW" size="4">
<bitfield caption="Undefined Length Burst Type" mask="0x00000007" name="ULBT"/>
</register>
<register caption="Master Configuration Register 2" name="MATRIX_MCFG2" offset="0x8" rw="RW" size="4">
<bitfield caption="Undefined Length Burst Type" mask="0x00000007" name="ULBT"/>
</register>
<register caption="Slave Configuration Register 0" name="MATRIX_SCFG0" offset="0x40" rw="RW" size="4">
<bitfield caption="Maximum Number of Allowed Cycles for a Burst" mask="0x000000FF" name="SLOT_CYCLE"/>
<bitfield caption="Default Master Type" mask="0x00030000" name="DEFMSTR_TYPE"/>
<bitfield caption="Fixed Default Master" mask="0x001C0000" name="FIXED_DEFMSTR"/>
<bitfield caption="Arbitration Type" mask="0x03000000" name="ARBT"/>
</register>
<register caption="Slave Configuration Register 1" name="MATRIX_SCFG1" offset="0x44" rw="RW" size="4">
<bitfield caption="Maximum Number of Allowed Cycles for a Burst" mask="0x000000FF" name="SLOT_CYCLE"/>
<bitfield caption="Default Master Type" mask="0x00030000" name="DEFMSTR_TYPE"/>
<bitfield caption="Fixed Default Master" mask="0x001C0000" name="FIXED_DEFMSTR"/>
<bitfield caption="Arbitration Type" mask="0x03000000" name="ARBT"/>
</register>
<register caption="Slave Configuration Register 2" name="MATRIX_SCFG2" offset="0x48" rw="RW" size="4">
<bitfield caption="Maximum Number of Allowed Cycles for a Burst" mask="0x000000FF" name="SLOT_CYCLE"/>
<bitfield caption="Default Master Type" mask="0x00030000" name="DEFMSTR_TYPE"/>
<bitfield caption="Fixed Default Master" mask="0x001C0000" name="FIXED_DEFMSTR"/>
<bitfield caption="Arbitration Type" mask="0x03000000" name="ARBT"/>
</register>
<register caption="Slave Configuration Register 3" name="MATRIX_SCFG3" offset="0x4C" rw="RW" size="4">
<bitfield caption="Maximum Number of Allowed Cycles for a Burst" mask="0x000000FF" name="SLOT_CYCLE"/>
<bitfield caption="Default Master Type" mask="0x00030000" name="DEFMSTR_TYPE"/>
<bitfield caption="Fixed Default Master" mask="0x001C0000" name="FIXED_DEFMSTR"/>
<bitfield caption="Arbitration Type" mask="0x03000000" name="ARBT"/>
</register>
<register caption="Priority Register A for Slave 0" name="MATRIX_PRAS0" offset="0x0080" rw="RW" size="4">
<bitfield caption="Master 0 Priority" mask="0x00000003" name="M0PR"/>
<bitfield caption="Master 1 Priority" mask="0x00000030" name="M1PR"/>
<bitfield caption="Master 2 Priority" mask="0x00000300" name="M2PR"/>
<bitfield caption="Master 3 Priority" mask="0x00003000" name="M3PR"/>
</register>
<register caption="Priority Register A for Slave 1" name="MATRIX_PRAS1" offset="0x0088" rw="RW" size="4">
<bitfield caption="Master 0 Priority" mask="0x00000003" name="M0PR"/>
<bitfield caption="Master 1 Priority" mask="0x00000030" name="M1PR"/>
<bitfield caption="Master 2 Priority" mask="0x00000300" name="M2PR"/>
<bitfield caption="Master 3 Priority" mask="0x00003000" name="M3PR"/>
</register>
<register caption="Priority Register A for Slave 2" name="MATRIX_PRAS2" offset="0x0090" rw="RW" size="4">
<bitfield caption="Master 0 Priority" mask="0x00000003" name="M0PR"/>
<bitfield caption="Master 1 Priority" mask="0x00000030" name="M1PR"/>
<bitfield caption="Master 2 Priority" mask="0x00000300" name="M2PR"/>
<bitfield caption="Master 3 Priority" mask="0x00003000" name="M3PR"/>
</register>
<register caption="Priority Register A for Slave 3" name="MATRIX_PRAS3" offset="0x0098" rw="RW" size="4">
<bitfield caption="Master 0 Priority" mask="0x00000003" name="M0PR"/>
<bitfield caption="Master 1 Priority" mask="0x00000030" name="M1PR"/>
<bitfield caption="Master 2 Priority" mask="0x00000300" name="M2PR"/>
<bitfield caption="Master 3 Priority" mask="0x00003000" name="M3PR"/>
</register>
<register caption="System I/O Configuration register" name="CCFG_SYSIO" offset="0x0114" rw="RW" size="4">
<bitfield caption="PB4 or TDI Assignment" mask="0x00000010" name="SYSIO4"/>
<bitfield caption="PB5 or TDO/TRACESWO Assignment" mask="0x00000020" name="SYSIO5"/>
<bitfield caption="PB6 or TMS/SWDIO Assignment" mask="0x00000040" name="SYSIO6"/>
<bitfield caption="PB7 or TCK/SWCLK Assignment" mask="0x00000080" name="SYSIO7"/>
<bitfield caption="PB12 or ERASE Assignment" mask="0x00001000" name="SYSIO12"/>
</register>
<register caption="Write Protect Mode Register" name="MATRIX_WPMR" offset="0x1E4" rw="RW" size="4">
<bitfield caption="Write Protect ENable" mask="0x00000001" name="WPEN"/>
<bitfield caption="Write Protect KEY (Write-only)" mask="0xFFFFFF00" name="WPKEY"/>
</register>
<register caption="Write Protect Status Register" name="MATRIX_WPSR" offset="0x1E8" rw="R" size="4">
<bitfield caption="Write Protect Violation Status" mask="0x00000001" name="WPVS"/>
<bitfield caption="Write Protect Violation Source" mask="0x00FFFF00" name="WPVSRC"/>
</register>
</register-group>
</module>
<module caption="Peripheral DMA Controller" name="PDC" version="6031C">
<register-group name="PDC">
<register caption="Receive Pointer Register" name="PERIPH_RPR" offset="0x0" rw="RW" size="4">
<bitfield caption="Receive Pointer Register" mask="0xFFFFFFFF" name="RXPTR"/>
</register>
<register caption="Receive Counter Register" name="PERIPH_RCR" offset="0x4" rw="RW" size="4">
<bitfield caption="Receive Counter Register" mask="0x0000FFFF" name="RXCTR"/>
</register>
<register caption="Transmit Pointer Register" name="PERIPH_TPR" offset="0x8" rw="RW" size="4">
<bitfield caption="Transmit Counter Register" mask="0xFFFFFFFF" name="TXPTR"/>
</register>
<register caption="Transmit Counter Register" name="PERIPH_TCR" offset="0xC" rw="RW" size="4">
<bitfield caption="Transmit Counter Register" mask="0x0000FFFF" name="TXCTR"/>
</register>
<register caption="Receive Next Pointer Register" name="PERIPH_RNPR" offset="0x10" rw="RW" size="4">
<bitfield caption="Receive Next Pointer" mask="0xFFFFFFFF" name="RXNPTR"/>
</register>
<register caption="Receive Next Counter Register" name="PERIPH_RNCR" offset="0x14" rw="RW" size="4">
<bitfield caption="Receive Next Counter" mask="0x0000FFFF" name="RXNCTR"/>
</register>
<register caption="Transmit Next Pointer Register" name="PERIPH_TNPR" offset="0x18" rw="RW" size="4">
<bitfield caption="Transmit Next Pointer" mask="0xFFFFFFFF" name="TXNPTR"/>
</register>
<register caption="Transmit Next Counter Register" name="PERIPH_TNCR" offset="0x1C" rw="RW" size="4">
<bitfield caption="Transmit Counter Next" mask="0x0000FFFF" name="TXNCTR"/>
</register>
<register caption="Transfer Control Register" name="PERIPH_PTCR" offset="0x20" rw="W" size="4">
<bitfield caption="Receiver Transfer Enable" mask="0x00000001" name="RXTEN"/>
<bitfield caption="Receiver Transfer Disable" mask="0x00000002" name="RXTDIS"/>
<bitfield caption="Transmitter Transfer Enable" mask="0x00000100" name="TXTEN"/>
<bitfield caption="Transmitter Transfer Disable" mask="0x00000200" name="TXTDIS"/>
</register>
<register caption="Transfer Status Register" name="PERIPH_PTSR" offset="0x24" rw="R" size="4">
<bitfield caption="Receiver Transfer Enable" mask="0x00000001" name="RXTEN"/>
<bitfield caption="Transmitter Transfer Enable" mask="0x00000100" name="TXTEN"/>
</register>
</register-group>
</module>
<module caption="Parallel Input/Output Controller" name="PIO" version="11004F">
<register-group name="PIO">