Special case in Verilog parser.

berkeley-abc · Dec 6, 2019 · 24d9ce6 · 24d9ce6
1 parent 95a6aa2
commit 24d9ce6
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diff --git a/src/base/ver/verCore.c b/src/base/ver/verCore.c
@@ -1329,13 +1329,15 @@ int Ver_ParseAssign( Ver_Man_t * pMan, Abc_Ntk_t * pNtk )
 ***********************************************************************/
 int Ver_ParseGateStandard( Ver_Man_t * pMan, Abc_Ntk_t * pNtk, Ver_GateType_t GateType )
 {
+    extern void Ver_StreamMove( Ver_Stream_t * p );
     Ver_Stream_t * p = pMan->pReader;
     Abc_Obj_t * pNet, * pNode;
     char * pWord, Symbol;
 
     // convert from the blackbox into the network with local functions representated by AIGs
     if ( !Ver_ParseConvertNetwork( pMan, pNtk, pMan->fMapped ) )
         return 0;
+    Ver_StreamMove( p );
 
     // this is gate name - throw it away
     if ( Ver_StreamPopChar(p) != '(' )

diff --git a/src/base/ver/verStream.c b/src/base/ver/verStream.c
@@ -441,6 +441,24 @@ char * Ver_StreamGetWord( Ver_Stream_t * p, char * pCharsToStop )
     return NULL;
 }
 
+/**Function*************************************************************
+
+  Synopsis    []
+
+  Description []
+               
+  SideEffects []
+
+  SeeAlso     []
+
+***********************************************************************/
+void Ver_StreamMove( Ver_Stream_t * p )
+{
+    if ( !strncmp(p->pBufferCur+1, "z_g_", 4) )
+        while ( p->pBufferCur[0] != '(' )
+            p->pBufferCur++;
+}
+
 ////////////////////////////////////////////////////////////////////////
 ///                       END OF FILE                                ///
 ////////////////////////////////////////////////////////////////////////