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bnxt_hwrm.c
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bnxt_hwrm.c
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/* SPDX-License-Identifier: BSD-3-Clause
* Copyright(c) 2014-2021 Broadcom
* All rights reserved.
*/
#include <unistd.h>
#include <rte_byteorder.h>
#include <rte_common.h>
#include <rte_cycles.h>
#include <rte_malloc.h>
#include <rte_memzone.h>
#include <rte_version.h>
#include <rte_io.h>
#include "bnxt.h"
#include "bnxt_filter.h"
#include "bnxt_hwrm.h"
#include "bnxt_rxq.h"
#include "bnxt_rxr.h"
#include "bnxt_ring.h"
#include "bnxt_txq.h"
#include "bnxt_txr.h"
#include "bnxt_vnic.h"
#include "hsi_struct_def_dpdk.h"
#define HWRM_SPEC_CODE_1_8_3 0x10803
#define HWRM_VERSION_1_9_1 0x10901
#define HWRM_VERSION_1_9_2 0x10903
#define HWRM_VERSION_1_10_2_13 0x10a020d
struct bnxt_plcmodes_cfg {
uint32_t flags;
uint16_t jumbo_thresh;
uint16_t hds_offset;
uint16_t hds_threshold;
};
static int page_getenum(size_t size)
{
if (size <= 1 << 4)
return 4;
if (size <= 1 << 12)
return 12;
if (size <= 1 << 13)
return 13;
if (size <= 1 << 16)
return 16;
if (size <= 1 << 21)
return 21;
if (size <= 1 << 22)
return 22;
if (size <= 1 << 30)
return 30;
PMD_DRV_LOG(ERR, "Page size %zu out of range\n", size);
return sizeof(int) * 8 - 1;
}
static int page_roundup(size_t size)
{
return 1 << page_getenum(size);
}
static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem,
uint8_t *pg_attr,
uint64_t *pg_dir)
{
if (rmem->nr_pages == 0)
return;
if (rmem->nr_pages > 1) {
*pg_attr = 1;
*pg_dir = rte_cpu_to_le_64(rmem->pg_tbl_map);
} else {
*pg_dir = rte_cpu_to_le_64(rmem->dma_arr[0]);
}
}
static struct bnxt_cp_ring_info*
bnxt_get_ring_info_by_id(struct bnxt *bp, uint16_t rid, uint16_t type)
{
struct bnxt_cp_ring_info *cp_ring = NULL;
uint16_t i;
switch (type) {
case HWRM_RING_FREE_INPUT_RING_TYPE_RX:
case HWRM_RING_FREE_INPUT_RING_TYPE_RX_AGG:
/* FALLTHROUGH */
for (i = 0; i < bp->rx_cp_nr_rings; i++) {
struct bnxt_rx_queue *rxq = bp->rx_queues[i];
if (rxq->cp_ring->cp_ring_struct->fw_ring_id ==
rte_cpu_to_le_16(rid)) {
return rxq->cp_ring;
}
}
break;
case HWRM_RING_FREE_INPUT_RING_TYPE_TX:
for (i = 0; i < bp->tx_cp_nr_rings; i++) {
struct bnxt_tx_queue *txq = bp->tx_queues[i];
if (txq->cp_ring->cp_ring_struct->fw_ring_id ==
rte_cpu_to_le_16(rid)) {
return txq->cp_ring;
}
}
break;
default:
return cp_ring;
}
return cp_ring;
}
/* Complete a sweep of the CQ ring for the corresponding Tx/Rx/AGG ring.
* If the CMPL_BASE_TYPE_HWRM_DONE is not encountered by the last pass,
* before timeout, we force the done bit for the cleanup to proceed.
* Also if cpr is null, do nothing.. The HWRM command is not for a
* Tx/Rx/AGG ring cleanup.
*/
static int
bnxt_check_cq_hwrm_done(struct bnxt_cp_ring_info *cpr,
bool tx, bool rx, bool timeout)
{
int done = 0;
if (cpr != NULL) {
if (tx)
done = bnxt_flush_tx_cmp(cpr);
if (rx)
done = bnxt_flush_rx_cmp(cpr);
if (done)
PMD_DRV_LOG(DEBUG, "HWRM DONE for %s ring\n",
rx ? "Rx" : "Tx");
/* We are about to timeout and still haven't seen the
* HWRM done for the Ring free. Force the cleanup.
*/
if (!done && timeout) {
done = 1;
PMD_DRV_LOG(DEBUG, "Timing out for %s ring\n",
rx ? "Rx" : "Tx");
}
} else {
/* This HWRM command is not for a Tx/Rx/AGG ring cleanup.
* Otherwise the cpr would have been valid. So do nothing.
*/
done = 1;
}
return done;
}
/*
* HWRM Functions (sent to HWRM)
* These are named bnxt_hwrm_*() and return 0 on success or -110 if the
* HWRM command times out, or a negative error code if the HWRM
* command was failed by the FW.
*/
static int bnxt_hwrm_send_message(struct bnxt *bp, void *msg,
uint32_t msg_len, bool use_kong_mb)
{
unsigned int i;
struct input *req = msg;
struct output *resp = bp->hwrm_cmd_resp_addr;
uint32_t *data = msg;
uint8_t *bar;
uint8_t *valid;
uint16_t max_req_len = bp->max_req_len;
struct hwrm_short_input short_input = { 0 };
uint16_t bar_offset = use_kong_mb ?
GRCPF_REG_KONG_CHANNEL_OFFSET : GRCPF_REG_CHIMP_CHANNEL_OFFSET;
uint16_t mb_trigger_offset = use_kong_mb ?
GRCPF_REG_KONG_COMM_TRIGGER : GRCPF_REG_CHIMP_COMM_TRIGGER;
struct bnxt_cp_ring_info *cpr = NULL;
bool is_rx = false;
bool is_tx = false;
uint32_t timeout;
/* Do not send HWRM commands to firmware in error state */
if (bp->flags & BNXT_FLAG_FATAL_ERROR)
return 0;
timeout = bp->hwrm_cmd_timeout;
/* Update the message length for backing store config for new FW. */
if (bp->fw_ver >= HWRM_VERSION_1_10_2_13 &&
rte_cpu_to_le_16(req->req_type) == HWRM_FUNC_BACKING_STORE_CFG)
msg_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
if (bp->flags & BNXT_FLAG_SHORT_CMD ||
msg_len > bp->max_req_len) {
void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
memset(short_cmd_req, 0, bp->hwrm_max_ext_req_len);
memcpy(short_cmd_req, req, msg_len);
short_input.req_type = rte_cpu_to_le_16(req->req_type);
short_input.signature = rte_cpu_to_le_16(
HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD);
short_input.size = rte_cpu_to_le_16(msg_len);
short_input.req_addr =
rte_cpu_to_le_64(bp->hwrm_short_cmd_req_dma_addr);
data = (uint32_t *)&short_input;
msg_len = sizeof(short_input);
max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
}
/* Write request msg to hwrm channel */
for (i = 0; i < msg_len; i += 4) {
bar = (uint8_t *)bp->bar0 + bar_offset + i;
rte_write32(*data, bar);
data++;
}
/* Zero the rest of the request space */
for (; i < max_req_len; i += 4) {
bar = (uint8_t *)bp->bar0 + bar_offset + i;
rte_write32(0, bar);
}
/* Ring channel doorbell */
bar = (uint8_t *)bp->bar0 + mb_trigger_offset;
rte_write32(1, bar);
/*
* Make sure the channel doorbell ring command complete before
* reading the response to avoid getting stale or invalid
* responses.
*/
rte_io_mb();
/* Check ring flush is done.
* This is valid only for Tx and Rx rings (including AGG rings).
* The Tx and Rx rings should be freed once the HW confirms all
* the internal buffers and BDs associated with the rings are
* consumed and the corresponding DMA is handled.
*/
if (rte_cpu_to_le_16(req->cmpl_ring) != INVALID_HW_RING_ID) {
/* Check if the TxCQ matches. If that fails check if RxCQ
* matches. And if neither match, is_rx = false, is_tx = false.
*/
cpr = bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
HWRM_RING_FREE_INPUT_RING_TYPE_TX);
if (cpr == NULL) {
/* Not a TxCQ. Check if the RxCQ matches. */
cpr =
bnxt_get_ring_info_by_id(bp, req->cmpl_ring,
HWRM_RING_FREE_INPUT_RING_TYPE_RX);
if (cpr != NULL)
is_rx = true;
} else {
is_tx = true;
}
}
/* Poll for the valid bit */
for (i = 0; i < timeout; i++) {
int done;
done = bnxt_check_cq_hwrm_done(cpr, is_tx, is_rx,
i == timeout - 1);
/* Sanity check on the resp->resp_len */
rte_io_rmb();
if (resp->resp_len && resp->resp_len <= bp->max_resp_len) {
/* Last byte of resp contains the valid key */
valid = (uint8_t *)resp + resp->resp_len - 1;
if (*valid == HWRM_RESP_VALID_KEY && done)
break;
}
rte_delay_us(1);
}
if (i >= timeout) {
/* Suppress VER_GET timeout messages during reset recovery */
if (bp->flags & BNXT_FLAG_FW_RESET &&
rte_cpu_to_le_16(req->req_type) == HWRM_VER_GET)
return -ETIMEDOUT;
PMD_DRV_LOG(ERR,
"Error(timeout) sending msg 0x%04x, seq_id %d\n",
req->req_type, req->seq_id);
return -ETIMEDOUT;
}
return 0;
}
/*
* HWRM_PREP() should be used to prepare *ALL* HWRM commands. It grabs the
* spinlock, and does initial processing.
*
* HWRM_CHECK_RESULT() returns errors on failure and may not be used. It
* releases the spinlock only if it returns. If the regular int return codes
* are not used by the function, HWRM_CHECK_RESULT() should not be used
* directly, rather it should be copied and modified to suit the function.
*
* HWRM_UNLOCK() must be called after all response processing is completed.
*/
#define HWRM_PREP(req, type, kong) do { \
rte_spinlock_lock(&bp->hwrm_lock); \
if (bp->hwrm_cmd_resp_addr == NULL) { \
rte_spinlock_unlock(&bp->hwrm_lock); \
return -EACCES; \
} \
memset(bp->hwrm_cmd_resp_addr, 0, bp->max_resp_len); \
(req)->req_type = rte_cpu_to_le_16(type); \
(req)->cmpl_ring = rte_cpu_to_le_16(-1); \
(req)->seq_id = kong ? rte_cpu_to_le_16(bp->kong_cmd_seq++) :\
rte_cpu_to_le_16(bp->chimp_cmd_seq++); \
(req)->target_id = rte_cpu_to_le_16(0xffff); \
(req)->resp_addr = rte_cpu_to_le_64(bp->hwrm_cmd_resp_dma_addr); \
} while (0)
#define HWRM_CHECK_RESULT_SILENT() do {\
if (rc) { \
rte_spinlock_unlock(&bp->hwrm_lock); \
return rc; \
} \
if (resp->error_code) { \
rc = rte_le_to_cpu_16(resp->error_code); \
rte_spinlock_unlock(&bp->hwrm_lock); \
return rc; \
} \
} while (0)
#define HWRM_CHECK_RESULT() do {\
if (rc) { \
PMD_DRV_LOG(ERR, "failed rc:%d\n", rc); \
rte_spinlock_unlock(&bp->hwrm_lock); \
if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
rc = -EACCES; \
else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
rc = -ENOSPC; \
else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
rc = -EINVAL; \
else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
rc = -ENOTSUP; \
else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
rc = -EAGAIN; \
else if (rc > 0) \
rc = -EIO; \
return rc; \
} \
if (resp->error_code) { \
rc = rte_le_to_cpu_16(resp->error_code); \
if (resp->resp_len >= 16) { \
struct hwrm_err_output *tmp_hwrm_err_op = \
(void *)resp; \
PMD_DRV_LOG(ERR, \
"error %d:%d:%08x:%04x\n", \
rc, tmp_hwrm_err_op->cmd_err, \
rte_le_to_cpu_32(\
tmp_hwrm_err_op->opaque_0), \
rte_le_to_cpu_16(\
tmp_hwrm_err_op->opaque_1)); \
} else { \
PMD_DRV_LOG(ERR, "error %d\n", rc); \
} \
rte_spinlock_unlock(&bp->hwrm_lock); \
if (rc == HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED) \
rc = -EACCES; \
else if (rc == HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR) \
rc = -ENOSPC; \
else if (rc == HWRM_ERR_CODE_INVALID_PARAMS) \
rc = -EINVAL; \
else if (rc == HWRM_ERR_CODE_CMD_NOT_SUPPORTED) \
rc = -ENOTSUP; \
else if (rc == HWRM_ERR_CODE_HOT_RESET_PROGRESS) \
rc = -EAGAIN; \
else if (rc > 0) \
rc = -EIO; \
return rc; \
} \
} while (0)
#define HWRM_UNLOCK() rte_spinlock_unlock(&bp->hwrm_lock)
int bnxt_hwrm_tf_message_direct(struct bnxt *bp,
bool use_kong_mb,
uint16_t msg_type,
void *msg,
uint32_t msg_len,
void *resp_msg,
uint32_t resp_len)
{
int rc = 0;
bool mailbox = BNXT_USE_CHIMP_MB;
struct input *req = msg;
struct output *resp = bp->hwrm_cmd_resp_addr;
if (use_kong_mb)
mailbox = BNXT_USE_KONG(bp);
HWRM_PREP(req, msg_type, mailbox);
rc = bnxt_hwrm_send_message(bp, req, msg_len, mailbox);
HWRM_CHECK_RESULT();
if (resp_msg)
memcpy(resp_msg, resp, resp_len);
HWRM_UNLOCK();
return rc;
}
int bnxt_hwrm_tf_message_tunneled(struct bnxt *bp,
bool use_kong_mb,
uint16_t tf_type,
uint16_t tf_subtype,
uint32_t *tf_response_code,
void *msg,
uint32_t msg_len,
void *response,
uint32_t response_len)
{
int rc = 0;
struct hwrm_cfa_tflib_input req = { .req_type = 0 };
struct hwrm_cfa_tflib_output *resp = bp->hwrm_cmd_resp_addr;
bool mailbox = BNXT_USE_CHIMP_MB;
if (msg_len > sizeof(req.tf_req))
return -ENOMEM;
if (use_kong_mb)
mailbox = BNXT_USE_KONG(bp);
HWRM_PREP(&req, HWRM_TF, mailbox);
/* Build request using the user supplied request payload.
* TLV request size is checked at build time against HWRM
* request max size, thus no checking required.
*/
req.tf_type = tf_type;
req.tf_subtype = tf_subtype;
memcpy(req.tf_req, msg, msg_len);
rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), mailbox);
HWRM_CHECK_RESULT();
/* Copy the resp to user provided response buffer */
if (response != NULL)
/* Post process response data. We need to copy only
* the 'payload' as the HWRM data structure really is
* HWRM header + msg header + payload and the TFLIB
* only provided a payload place holder.
*/
if (response_len != 0) {
memcpy(response,
resp->tf_resp,
response_len);
}
/* Extract the internal tflib response code */
*tf_response_code = resp->tf_resp_code;
HWRM_UNLOCK();
return rc;
}
int bnxt_hwrm_cfa_l2_clear_rx_mask(struct bnxt *bp, struct bnxt_vnic_info *vnic)
{
int rc = 0;
struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
req.mask = 0;
rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
HWRM_CHECK_RESULT();
HWRM_UNLOCK();
return rc;
}
int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp,
struct bnxt_vnic_info *vnic,
uint16_t vlan_count,
struct bnxt_vlan_table_entry *vlan_table)
{
int rc = 0;
struct hwrm_cfa_l2_set_rx_mask_input req = {.req_type = 0 };
struct hwrm_cfa_l2_set_rx_mask_output *resp = bp->hwrm_cmd_resp_addr;
uint32_t mask = 0;
if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
return rc;
HWRM_PREP(&req, HWRM_CFA_L2_SET_RX_MASK, BNXT_USE_CHIMP_MB);
req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
if (vnic->flags & BNXT_VNIC_INFO_BCAST)
mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_BCAST;
if (vnic->flags & BNXT_VNIC_INFO_UNTAGGED)
mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN;
if (vnic->flags & BNXT_VNIC_INFO_PROMISC)
mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_PROMISCUOUS;
if (vnic->flags & BNXT_VNIC_INFO_ALLMULTI) {
mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_ALL_MCAST;
} else if (vnic->flags & BNXT_VNIC_INFO_MCAST) {
mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_MCAST;
req.num_mc_entries = rte_cpu_to_le_32(bp->nb_mc_addr);
req.mc_tbl_addr = rte_cpu_to_le_64(bp->mc_list_dma_addr);
}
if (vlan_table) {
if (!(mask & HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLAN_NONVLAN))
mask |= HWRM_CFA_L2_SET_RX_MASK_INPUT_MASK_VLANONLY;
req.vlan_tag_tbl_addr =
rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
req.num_vlan_tags = rte_cpu_to_le_32((uint32_t)vlan_count);
}
req.mask = rte_cpu_to_le_32(mask);
rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
HWRM_CHECK_RESULT();
HWRM_UNLOCK();
return rc;
}
int bnxt_hwrm_cfa_vlan_antispoof_cfg(struct bnxt *bp, uint16_t fid,
uint16_t vlan_count,
struct bnxt_vlan_antispoof_table_entry *vlan_table)
{
int rc = 0;
struct hwrm_cfa_vlan_antispoof_cfg_input req = {.req_type = 0 };
struct hwrm_cfa_vlan_antispoof_cfg_output *resp =
bp->hwrm_cmd_resp_addr;
/*
* Older HWRM versions did not support this command, and the set_rx_mask
* list was used for anti-spoof. In 1.8.0, the TX path configuration was
* removed from set_rx_mask call, and this command was added.
*
* This command is also present from 1.7.8.11 and higher,
* as well as 1.7.8.0
*/
if (bp->fw_ver < ((1 << 24) | (8 << 16))) {
if (bp->fw_ver != ((1 << 24) | (7 << 16) | (8 << 8))) {
if (bp->fw_ver < ((1 << 24) | (7 << 16) | (8 << 8) |
(11)))
return 0;
}
}
HWRM_PREP(&req, HWRM_CFA_VLAN_ANTISPOOF_CFG, BNXT_USE_CHIMP_MB);
req.fid = rte_cpu_to_le_16(fid);
req.vlan_tag_mask_tbl_addr =
rte_cpu_to_le_64(rte_malloc_virt2iova(vlan_table));
req.num_vlan_entries = rte_cpu_to_le_32((uint32_t)vlan_count);
rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
HWRM_CHECK_RESULT();
HWRM_UNLOCK();
return rc;
}
int bnxt_hwrm_clear_l2_filter(struct bnxt *bp,
struct bnxt_filter_info *filter)
{
int rc = 0;
struct bnxt_filter_info *l2_filter = filter;
struct bnxt_vnic_info *vnic = NULL;
struct hwrm_cfa_l2_filter_free_input req = {.req_type = 0 };
struct hwrm_cfa_l2_filter_free_output *resp = bp->hwrm_cmd_resp_addr;
if (filter->fw_l2_filter_id == UINT64_MAX)
return 0;
if (filter->matching_l2_fltr_ptr)
l2_filter = filter->matching_l2_fltr_ptr;
PMD_DRV_LOG(DEBUG, "filter: %p l2_filter: %p ref_cnt: %d\n",
filter, l2_filter, l2_filter->l2_ref_cnt);
if (l2_filter->l2_ref_cnt == 0)
return 0;
if (l2_filter->l2_ref_cnt > 0)
l2_filter->l2_ref_cnt--;
if (l2_filter->l2_ref_cnt > 0)
return 0;
HWRM_PREP(&req, HWRM_CFA_L2_FILTER_FREE, BNXT_USE_CHIMP_MB);
req.l2_filter_id = rte_cpu_to_le_64(filter->fw_l2_filter_id);
rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
HWRM_CHECK_RESULT();
HWRM_UNLOCK();
filter->fw_l2_filter_id = UINT64_MAX;
if (l2_filter->l2_ref_cnt == 0) {
vnic = l2_filter->vnic;
if (vnic) {
STAILQ_REMOVE(&vnic->filter, l2_filter,
bnxt_filter_info, next);
bnxt_free_filter(bp, l2_filter);
}
}
return 0;
}
int bnxt_hwrm_set_l2_filter(struct bnxt *bp,
uint16_t dst_id,
struct bnxt_filter_info *filter)
{
int rc = 0;
struct hwrm_cfa_l2_filter_alloc_input req = {.req_type = 0 };
struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
const struct rte_eth_vmdq_rx_conf *conf =
&dev_conf->rx_adv_conf.vmdq_rx_conf;
uint32_t enables = 0;
uint16_t j = dst_id - 1;
//TODO: Is there a better way to add VLANs to each VNIC in case of VMDQ
if ((dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_VMDQ_FLAG) &&
conf->pool_map[j].pools & (1UL << j)) {
PMD_DRV_LOG(DEBUG,
"Add vlan %u to vmdq pool %u\n",
conf->pool_map[j].vlan_id, j);
filter->l2_ivlan = conf->pool_map[j].vlan_id;
filter->enables |=
HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN |
HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK;
}
if (filter->fw_l2_filter_id != UINT64_MAX)
bnxt_hwrm_clear_l2_filter(bp, filter);
HWRM_PREP(&req, HWRM_CFA_L2_FILTER_ALLOC, BNXT_USE_CHIMP_MB);
/* PMD does not support XDP and RoCE */
filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE |
HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_L2;
req.flags = rte_cpu_to_le_32(filter->flags);
enables = filter->enables |
HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_DST_ID;
req.dst_id = rte_cpu_to_le_16(dst_id);
if (enables &
HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR)
memcpy(req.l2_addr, filter->l2_addr,
RTE_ETHER_ADDR_LEN);
if (enables &
HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK)
memcpy(req.l2_addr_mask, filter->l2_addr_mask,
RTE_ETHER_ADDR_LEN);
if (enables &
HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN)
req.l2_ovlan = filter->l2_ovlan;
if (enables &
HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN)
req.l2_ivlan = filter->l2_ivlan;
if (enables &
HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK)
req.l2_ovlan_mask = filter->l2_ovlan_mask;
if (enables &
HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK)
req.l2_ivlan_mask = filter->l2_ivlan_mask;
if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_ID)
req.src_id = rte_cpu_to_le_32(filter->src_id);
if (enables & HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_SRC_TYPE)
req.src_type = filter->src_type;
if (filter->pri_hint) {
req.pri_hint = filter->pri_hint;
req.l2_filter_id_hint =
rte_cpu_to_le_64(filter->l2_filter_id_hint);
}
req.enables = rte_cpu_to_le_32(enables);
rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
HWRM_CHECK_RESULT();
filter->fw_l2_filter_id = rte_le_to_cpu_64(resp->l2_filter_id);
filter->flow_id = rte_le_to_cpu_32(resp->flow_id);
HWRM_UNLOCK();
filter->l2_ref_cnt++;
return rc;
}
int bnxt_hwrm_ptp_cfg(struct bnxt *bp)
{
struct hwrm_port_mac_cfg_input req = {.req_type = 0};
struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
uint32_t flags = 0;
int rc;
if (!ptp)
return 0;
HWRM_PREP(&req, HWRM_PORT_MAC_CFG, BNXT_USE_CHIMP_MB);
if (ptp->rx_filter)
flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_ENABLE;
else
flags |=
HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_RX_TS_CAPTURE_DISABLE;
if (ptp->tx_tstamp_en)
flags |= HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_ENABLE;
else
flags |=
HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_TX_TS_CAPTURE_DISABLE;
req.flags = rte_cpu_to_le_32(flags);
req.enables = rte_cpu_to_le_32
(HWRM_PORT_MAC_CFG_INPUT_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE);
req.rx_ts_capture_ptp_msg_type = rte_cpu_to_le_16(ptp->rxctl);
rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
HWRM_UNLOCK();
return rc;
}
static int bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
{
int rc = 0;
struct hwrm_port_mac_ptp_qcfg_input req = {.req_type = 0};
struct hwrm_port_mac_ptp_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
struct bnxt_ptp_cfg *ptp = bp->ptp_cfg;
if (ptp)
return 0;
HWRM_PREP(&req, HWRM_PORT_MAC_PTP_QCFG, BNXT_USE_CHIMP_MB);
req.port_id = rte_cpu_to_le_16(bp->pf->port_id);
rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
HWRM_CHECK_RESULT();
if (BNXT_CHIP_P5(bp)) {
if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS))
return 0;
} else {
if (!(resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_DIRECT_ACCESS))
return 0;
}
if (resp->flags & HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS)
bp->flags |= BNXT_FLAG_FW_CAP_ONE_STEP_TX_TS;
ptp = rte_zmalloc("ptp_cfg", sizeof(*ptp), 0);
if (!ptp)
return -ENOMEM;
if (!BNXT_CHIP_P5(bp)) {
ptp->rx_regs[BNXT_PTP_RX_TS_L] =
rte_le_to_cpu_32(resp->rx_ts_reg_off_lower);
ptp->rx_regs[BNXT_PTP_RX_TS_H] =
rte_le_to_cpu_32(resp->rx_ts_reg_off_upper);
ptp->rx_regs[BNXT_PTP_RX_SEQ] =
rte_le_to_cpu_32(resp->rx_ts_reg_off_seq_id);
ptp->rx_regs[BNXT_PTP_RX_FIFO] =
rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo);
ptp->rx_regs[BNXT_PTP_RX_FIFO_ADV] =
rte_le_to_cpu_32(resp->rx_ts_reg_off_fifo_adv);
ptp->tx_regs[BNXT_PTP_TX_TS_L] =
rte_le_to_cpu_32(resp->tx_ts_reg_off_lower);
ptp->tx_regs[BNXT_PTP_TX_TS_H] =
rte_le_to_cpu_32(resp->tx_ts_reg_off_upper);
ptp->tx_regs[BNXT_PTP_TX_SEQ] =
rte_le_to_cpu_32(resp->tx_ts_reg_off_seq_id);
ptp->tx_regs[BNXT_PTP_TX_FIFO] =
rte_le_to_cpu_32(resp->tx_ts_reg_off_fifo);
}
ptp->bp = bp;
bp->ptp_cfg = ptp;
return 0;
}
void bnxt_free_vf_info(struct bnxt *bp)
{
int i;
if (bp->pf == NULL)
return;
if (bp->pf->vf_info == NULL)
return;
for (i = 0; i < bp->pf->max_vfs; i++) {
rte_free(bp->pf->vf_info[i].vlan_table);
bp->pf->vf_info[i].vlan_table = NULL;
rte_free(bp->pf->vf_info[i].vlan_as_table);
bp->pf->vf_info[i].vlan_as_table = NULL;
}
rte_free(bp->pf->vf_info);
bp->pf->vf_info = NULL;
}
static int bnxt_alloc_vf_info(struct bnxt *bp, uint16_t max_vfs)
{
struct bnxt_child_vf_info *vf_info = bp->pf->vf_info;
int i;
if (vf_info)
bnxt_free_vf_info(bp);
vf_info = rte_zmalloc("bnxt_vf_info", sizeof(*vf_info) * max_vfs, 0);
if (vf_info == NULL) {
PMD_DRV_LOG(ERR, "Failed to alloc vf info\n");
return -ENOMEM;
}
bp->pf->max_vfs = max_vfs;
for (i = 0; i < max_vfs; i++) {
vf_info[i].fid = bp->pf->first_vf_id + i;
vf_info[i].vlan_table = rte_zmalloc("VF VLAN table",
getpagesize(), getpagesize());
if (vf_info[i].vlan_table == NULL) {
PMD_DRV_LOG(ERR, "Failed to alloc VLAN table for VF %d\n", i);
goto err;
}
rte_mem_lock_page(vf_info[i].vlan_table);
vf_info[i].vlan_as_table = rte_zmalloc("VF VLAN AS table",
getpagesize(), getpagesize());
if (vf_info[i].vlan_as_table == NULL) {
PMD_DRV_LOG(ERR, "Failed to alloc VLAN AS table for VF %d\n", i);
goto err;
}
rte_mem_lock_page(vf_info[i].vlan_as_table);
STAILQ_INIT(&vf_info[i].filter);
}
bp->pf->vf_info = vf_info;
return 0;
err:
bnxt_free_vf_info(bp);
return -ENOMEM;
}
static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
{
int rc = 0;
struct hwrm_func_qcaps_input req = {.req_type = 0 };
struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
uint16_t new_max_vfs;
uint32_t flags;
HWRM_PREP(&req, HWRM_FUNC_QCAPS, BNXT_USE_CHIMP_MB);
req.fid = rte_cpu_to_le_16(0xffff);
rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
HWRM_CHECK_RESULT();
bp->max_ring_grps = rte_le_to_cpu_32(resp->max_hw_ring_grps);
flags = rte_le_to_cpu_32(resp->flags);
if (BNXT_PF(bp)) {
bp->pf->port_id = resp->port_id;
bp->pf->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
bp->pf->total_vfs = rte_le_to_cpu_16(resp->max_vfs);
new_max_vfs = bp->pdev->max_vfs;
if (new_max_vfs != bp->pf->max_vfs) {
rc = bnxt_alloc_vf_info(bp, new_max_vfs);
if (rc)
goto unlock;
}
}
bp->fw_fid = rte_le_to_cpu_32(resp->fid);
if (!bnxt_check_zero_bytes(resp->mac_address, RTE_ETHER_ADDR_LEN)) {
bp->flags |= BNXT_FLAG_DFLT_MAC_SET;
memcpy(bp->mac_addr, &resp->mac_address, RTE_ETHER_ADDR_LEN);
} else {
bp->flags &= ~BNXT_FLAG_DFLT_MAC_SET;
}
bp->max_rsscos_ctx = rte_le_to_cpu_16(resp->max_rsscos_ctx);
bp->max_cp_rings = rte_le_to_cpu_16(resp->max_cmpl_rings);
bp->max_tx_rings = rte_le_to_cpu_16(resp->max_tx_rings);
bp->max_rx_rings = rte_le_to_cpu_16(resp->max_rx_rings);
bp->first_vf_id = rte_le_to_cpu_16(resp->first_vf_id);
bp->max_rx_em_flows = rte_le_to_cpu_16(resp->max_rx_em_flows);
bp->max_l2_ctx = rte_le_to_cpu_16(resp->max_l2_ctxs);
if (!BNXT_CHIP_P5(bp) && !bp->pdev->max_vfs)
bp->max_l2_ctx += bp->max_rx_em_flows;
/* TODO: For now, do not support VMDq/RFS on VFs. */
if (BNXT_PF(bp)) {
if (bp->pf->max_vfs)
bp->max_vnics = 1;
else
bp->max_vnics = rte_le_to_cpu_16(resp->max_vnics);
} else {
bp->max_vnics = 1;
}
PMD_DRV_LOG(DEBUG, "Max l2_cntxts is %d vnics is %d\n",
bp->max_l2_ctx, bp->max_vnics);
bp->max_stat_ctx = rte_le_to_cpu_16(resp->max_stat_ctx);
bp->max_mcast_addr = rte_le_to_cpu_32(resp->max_mcast_filters);
if (BNXT_PF(bp)) {
bp->pf->total_vnics = rte_le_to_cpu_16(resp->max_vnics);
if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_PTP_SUPPORTED) {
bp->flags |= BNXT_FLAG_PTP_SUPPORTED;
PMD_DRV_LOG(DEBUG, "PTP SUPPORTED\n");
HWRM_UNLOCK();
bnxt_hwrm_ptp_qcfg(bp);
}
}
if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED)
bp->flags |= BNXT_FLAG_EXT_STATS_SUPPORTED;
if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE) {
bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
PMD_DRV_LOG(DEBUG, "Adapter Error recovery SUPPORTED\n");
}
if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERR_RECOVER_RELOAD)
bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE)
bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
if (flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_LINK_ADMIN_STATUS_SUPPORTED)
bp->fw_cap |= BNXT_FW_CAP_LINK_ADMIN;
if (!(flags & HWRM_FUNC_QCAPS_OUTPUT_FLAGS_VLAN_ACCELERATION_TX_DISABLED)) {
bp->fw_cap |= BNXT_FW_CAP_VLAN_TX_INSERT;
PMD_DRV_LOG(DEBUG, "VLAN acceleration for TX is enabled\n");
}
unlock:
HWRM_UNLOCK();
return rc;
}
int bnxt_hwrm_func_qcaps(struct bnxt *bp)
{
int rc;
rc = __bnxt_hwrm_func_qcaps(bp);
if (rc == -ENOMEM)
return rc;
if (!rc && bp->hwrm_spec_code >= HWRM_SPEC_CODE_1_8_3) {
rc = bnxt_alloc_ctx_mem(bp);
if (rc)
return rc;
/* On older FW,
* bnxt_hwrm_func_resc_qcaps can fail and cause init failure.
* But the error can be ignored. Return success.
*/
rc = bnxt_hwrm_func_resc_qcaps(bp);
if (!rc)
bp->flags |= BNXT_FLAG_NEW_RM;
}
return 0;
}
/* VNIC cap covers capability of all VNICs. So no need to pass vnic_id */
int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
{
int rc = 0;
uint32_t flags;
struct hwrm_vnic_qcaps_input req = {.req_type = 0 };
struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
HWRM_PREP(&req, HWRM_VNIC_QCAPS, BNXT_USE_CHIMP_MB);
req.target_id = rte_cpu_to_le_16(0xffff);
rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
HWRM_CHECK_RESULT();
flags = rte_le_to_cpu_32(resp->flags);
if (flags & HWRM_VNIC_QCAPS_OUTPUT_FLAGS_COS_ASSIGNMENT_CAP) {
bp->vnic_cap_flags |= BNXT_VNIC_CAP_COS_CLASSIFY;