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hns3_ethdev.c
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hns3_ethdev.c
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/* SPDX-License-Identifier: BSD-3-Clause
* Copyright(c) 2018-2021 HiSilicon Limited.
*/
#include <rte_alarm.h>
#include <rte_bus_pci.h>
#include <rte_ethdev_pci.h>
#include <rte_io.h>
#include <rte_pci.h>
#include "hns3_ethdev.h"
#include "hns3_logs.h"
#include "hns3_rxtx.h"
#include "hns3_intr.h"
#include "hns3_regs.h"
#include "hns3_dcb.h"
#include "hns3_mp.h"
#define HNS3_DEFAULT_PORT_CONF_BURST_SIZE 32
#define HNS3_DEFAULT_PORT_CONF_QUEUES_NUM 1
#define HNS3_SERVICE_INTERVAL 1000000 /* us */
#define HNS3_INVALID_PVID 0xFFFF
#define HNS3_FILTER_TYPE_VF 0
#define HNS3_FILTER_TYPE_PORT 1
#define HNS3_FILTER_FE_EGRESS_V1_B BIT(0)
#define HNS3_FILTER_FE_NIC_INGRESS_B BIT(0)
#define HNS3_FILTER_FE_NIC_EGRESS_B BIT(1)
#define HNS3_FILTER_FE_ROCE_INGRESS_B BIT(2)
#define HNS3_FILTER_FE_ROCE_EGRESS_B BIT(3)
#define HNS3_FILTER_FE_EGRESS (HNS3_FILTER_FE_NIC_EGRESS_B \
| HNS3_FILTER_FE_ROCE_EGRESS_B)
#define HNS3_FILTER_FE_INGRESS (HNS3_FILTER_FE_NIC_INGRESS_B \
| HNS3_FILTER_FE_ROCE_INGRESS_B)
/* Reset related Registers */
#define HNS3_GLOBAL_RESET_BIT 0
#define HNS3_CORE_RESET_BIT 1
#define HNS3_IMP_RESET_BIT 2
#define HNS3_FUN_RST_ING_B 0
#define HNS3_VECTOR0_IMP_RESET_INT_B 1
#define HNS3_VECTOR0_IMP_CMDQ_ERR_B 4U
#define HNS3_VECTOR0_IMP_RD_POISON_B 5U
#define HNS3_VECTOR0_ALL_MSIX_ERR_B 6U
#define HNS3_RESET_WAIT_MS 100
#define HNS3_RESET_WAIT_CNT 200
/* FEC mode order defined in HNS3 hardware */
#define HNS3_HW_FEC_MODE_NOFEC 0
#define HNS3_HW_FEC_MODE_BASER 1
#define HNS3_HW_FEC_MODE_RS 2
enum hns3_evt_cause {
HNS3_VECTOR0_EVENT_RST,
HNS3_VECTOR0_EVENT_MBX,
HNS3_VECTOR0_EVENT_ERR,
HNS3_VECTOR0_EVENT_OTHER,
};
static const struct rte_eth_fec_capa speed_fec_capa_tbl[] = {
{ ETH_SPEED_NUM_10G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
{ ETH_SPEED_NUM_25G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
{ ETH_SPEED_NUM_40G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
RTE_ETH_FEC_MODE_CAPA_MASK(BASER) },
{ ETH_SPEED_NUM_50G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
RTE_ETH_FEC_MODE_CAPA_MASK(BASER) |
RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
{ ETH_SPEED_NUM_100G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
RTE_ETH_FEC_MODE_CAPA_MASK(RS) },
{ ETH_SPEED_NUM_200G, RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) |
RTE_ETH_FEC_MODE_CAPA_MASK(AUTO) |
RTE_ETH_FEC_MODE_CAPA_MASK(RS) }
};
static enum hns3_reset_level hns3_get_reset_level(struct hns3_adapter *hns,
uint64_t *levels);
static int hns3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
static int hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid,
int on);
static int hns3_update_link_info(struct rte_eth_dev *eth_dev);
static int hns3_add_mc_addr(struct hns3_hw *hw,
struct rte_ether_addr *mac_addr);
static int hns3_remove_mc_addr(struct hns3_hw *hw,
struct rte_ether_addr *mac_addr);
static int hns3_restore_fec(struct hns3_hw *hw);
static int hns3_query_dev_fec_info(struct hns3_hw *hw);
static int hns3_do_stop(struct hns3_adapter *hns);
static void
hns3_pf_disable_irq0(struct hns3_hw *hw)
{
hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 0);
}
static void
hns3_pf_enable_irq0(struct hns3_hw *hw)
{
hns3_write_dev(hw, HNS3_MISC_VECTOR_REG_BASE, 1);
}
static enum hns3_evt_cause
hns3_check_event_cause(struct hns3_adapter *hns, uint32_t *clearval)
{
struct hns3_hw *hw = &hns->hw;
uint32_t vector0_int_stats;
uint32_t cmdq_src_val;
uint32_t hw_err_src_reg;
uint32_t val;
enum hns3_evt_cause ret;
/* fetch the events from their corresponding regs */
vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
cmdq_src_val = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG);
hw_err_src_reg = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG);
/*
* Assumption: If by any chance reset and mailbox events are reported
* together then we will only process reset event and defer the
* processing of the mailbox events. Since, we would have not cleared
* RX CMDQ event this time we would receive again another interrupt
* from H/W just for the mailbox.
*/
if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats) { /* IMP */
rte_atomic16_set(&hw->reset.disable_cmd, 1);
hns3_atomic_set_bit(HNS3_IMP_RESET, &hw->reset.pending);
val = BIT(HNS3_VECTOR0_IMPRESET_INT_B);
if (clearval) {
hw->reset.stats.imp_cnt++;
hns3_warn(hw, "IMP reset detected, clear reset status");
} else {
hns3_schedule_delayed_reset(hns);
hns3_warn(hw, "IMP reset detected, don't clear reset status");
}
ret = HNS3_VECTOR0_EVENT_RST;
goto out;
}
/* Global reset */
if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats) {
rte_atomic16_set(&hw->reset.disable_cmd, 1);
hns3_atomic_set_bit(HNS3_GLOBAL_RESET, &hw->reset.pending);
val = BIT(HNS3_VECTOR0_GLOBALRESET_INT_B);
if (clearval) {
hw->reset.stats.global_cnt++;
hns3_warn(hw, "Global reset detected, clear reset status");
} else {
hns3_schedule_delayed_reset(hns);
hns3_warn(hw, "Global reset detected, don't clear reset status");
}
ret = HNS3_VECTOR0_EVENT_RST;
goto out;
}
/* check for vector0 msix event source */
if (vector0_int_stats & HNS3_VECTOR0_REG_MSIX_MASK ||
hw_err_src_reg & HNS3_RAS_REG_NFE_MASK) {
val = vector0_int_stats | hw_err_src_reg;
ret = HNS3_VECTOR0_EVENT_ERR;
goto out;
}
/* check for vector0 mailbox(=CMDQ RX) event source */
if (BIT(HNS3_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_val) {
cmdq_src_val &= ~BIT(HNS3_VECTOR0_RX_CMDQ_INT_B);
val = cmdq_src_val;
ret = HNS3_VECTOR0_EVENT_MBX;
goto out;
}
if (clearval && (vector0_int_stats || cmdq_src_val || hw_err_src_reg))
hns3_warn(hw, "vector0_int_stats:0x%x cmdq_src_val:0x%x hw_err_src_reg:0x%x",
vector0_int_stats, cmdq_src_val, hw_err_src_reg);
val = vector0_int_stats;
ret = HNS3_VECTOR0_EVENT_OTHER;
out:
if (clearval)
*clearval = val;
return ret;
}
static void
hns3_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr)
{
if (event_type == HNS3_VECTOR0_EVENT_RST)
hns3_write_dev(hw, HNS3_MISC_RESET_STS_REG, regclr);
else if (event_type == HNS3_VECTOR0_EVENT_MBX)
hns3_write_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG, regclr);
}
static void
hns3_clear_all_event_cause(struct hns3_hw *hw)
{
uint32_t vector0_int_stats;
vector0_int_stats = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG);
if (BIT(HNS3_VECTOR0_IMPRESET_INT_B) & vector0_int_stats)
hns3_warn(hw, "Probe during IMP reset interrupt");
if (BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) & vector0_int_stats)
hns3_warn(hw, "Probe during Global reset interrupt");
hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_RST,
BIT(HNS3_VECTOR0_IMPRESET_INT_B) |
BIT(HNS3_VECTOR0_GLOBALRESET_INT_B) |
BIT(HNS3_VECTOR0_CORERESET_INT_B));
hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0);
}
static void
hns3_interrupt_handler(void *param)
{
struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
struct hns3_adapter *hns = dev->data->dev_private;
struct hns3_hw *hw = &hns->hw;
enum hns3_evt_cause event_cause;
uint32_t clearval = 0;
/* Disable interrupt */
hns3_pf_disable_irq0(hw);
event_cause = hns3_check_event_cause(hns, &clearval);
hns3_clear_event_cause(hw, event_cause, clearval);
/* vector 0 interrupt is shared with reset and mailbox source events. */
if (event_cause == HNS3_VECTOR0_EVENT_ERR) {
hns3_warn(hw, "Received err interrupt");
hns3_handle_msix_error(hns, &hw->reset.request);
hns3_handle_ras_error(hns, &hw->reset.request);
hns3_schedule_reset(hns);
} else if (event_cause == HNS3_VECTOR0_EVENT_RST) {
hns3_warn(hw, "Received reset interrupt");
hns3_schedule_reset(hns);
} else if (event_cause == HNS3_VECTOR0_EVENT_MBX)
hns3_dev_handle_mbx_msg(hw);
else
hns3_err(hw, "Received unknown event");
/* Enable interrupt if it is not cause by reset */
hns3_pf_enable_irq0(hw);
}
static int
hns3_set_port_vlan_filter(struct hns3_adapter *hns, uint16_t vlan_id, int on)
{
#define HNS3_VLAN_ID_OFFSET_STEP 160
#define HNS3_VLAN_BYTE_SIZE 8
struct hns3_vlan_filter_pf_cfg_cmd *req;
struct hns3_hw *hw = &hns->hw;
uint8_t vlan_offset_byte_val;
struct hns3_cmd_desc desc;
uint8_t vlan_offset_byte;
uint8_t vlan_offset_base;
int ret;
hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_PF_CFG, false);
vlan_offset_base = vlan_id / HNS3_VLAN_ID_OFFSET_STEP;
vlan_offset_byte = (vlan_id % HNS3_VLAN_ID_OFFSET_STEP) /
HNS3_VLAN_BYTE_SIZE;
vlan_offset_byte_val = 1 << (vlan_id % HNS3_VLAN_BYTE_SIZE);
req = (struct hns3_vlan_filter_pf_cfg_cmd *)desc.data;
req->vlan_offset = vlan_offset_base;
req->vlan_cfg = on ? 0 : 1;
req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
ret = hns3_cmd_send(hw, &desc, 1);
if (ret)
hns3_err(hw, "set port vlan id failed, vlan_id =%u, ret =%d",
vlan_id, ret);
return ret;
}
static void
hns3_rm_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id)
{
struct hns3_user_vlan_table *vlan_entry;
struct hns3_pf *pf = &hns->pf;
LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
if (vlan_entry->vlan_id == vlan_id) {
if (vlan_entry->hd_tbl_status)
hns3_set_port_vlan_filter(hns, vlan_id, 0);
LIST_REMOVE(vlan_entry, next);
rte_free(vlan_entry);
break;
}
}
}
static void
hns3_add_dev_vlan_table(struct hns3_adapter *hns, uint16_t vlan_id,
bool writen_to_tbl)
{
struct hns3_user_vlan_table *vlan_entry;
struct hns3_hw *hw = &hns->hw;
struct hns3_pf *pf = &hns->pf;
LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
if (vlan_entry->vlan_id == vlan_id)
return;
}
vlan_entry = rte_zmalloc("hns3_vlan_tbl", sizeof(*vlan_entry), 0);
if (vlan_entry == NULL) {
hns3_err(hw, "Failed to malloc hns3 vlan table");
return;
}
vlan_entry->hd_tbl_status = writen_to_tbl;
vlan_entry->vlan_id = vlan_id;
LIST_INSERT_HEAD(&pf->vlan_list, vlan_entry, next);
}
static int
hns3_restore_vlan_table(struct hns3_adapter *hns)
{
struct hns3_user_vlan_table *vlan_entry;
struct hns3_hw *hw = &hns->hw;
struct hns3_pf *pf = &hns->pf;
uint16_t vlan_id;
int ret = 0;
if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_ENABLE)
return hns3_vlan_pvid_configure(hns,
hw->port_base_vlan_cfg.pvid, 1);
LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
if (vlan_entry->hd_tbl_status) {
vlan_id = vlan_entry->vlan_id;
ret = hns3_set_port_vlan_filter(hns, vlan_id, 1);
if (ret)
break;
}
}
return ret;
}
static int
hns3_vlan_filter_configure(struct hns3_adapter *hns, uint16_t vlan_id, int on)
{
struct hns3_hw *hw = &hns->hw;
bool writen_to_tbl = false;
int ret = 0;
/*
* When vlan filter is enabled, hardware regards packets without vlan
* as packets with vlan 0. So, to receive packets without vlan, vlan id
* 0 is not allowed to be removed by rte_eth_dev_vlan_filter.
*/
if (on == 0 && vlan_id == 0)
return 0;
/*
* When port base vlan enabled, we use port base vlan as the vlan
* filter condition. In this case, we don't update vlan filter table
* when user add new vlan or remove exist vlan, just update the
* vlan list. The vlan id in vlan list will be written in vlan filter
* table until port base vlan disabled
*/
if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
ret = hns3_set_port_vlan_filter(hns, vlan_id, on);
writen_to_tbl = true;
}
if (ret == 0) {
if (on)
hns3_add_dev_vlan_table(hns, vlan_id, writen_to_tbl);
else
hns3_rm_dev_vlan_table(hns, vlan_id);
}
return ret;
}
static int
hns3_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
{
struct hns3_adapter *hns = dev->data->dev_private;
struct hns3_hw *hw = &hns->hw;
int ret;
rte_spinlock_lock(&hw->lock);
ret = hns3_vlan_filter_configure(hns, vlan_id, on);
rte_spinlock_unlock(&hw->lock);
return ret;
}
static int
hns3_vlan_tpid_configure(struct hns3_adapter *hns, enum rte_vlan_type vlan_type,
uint16_t tpid)
{
struct hns3_rx_vlan_type_cfg_cmd *rx_req;
struct hns3_tx_vlan_type_cfg_cmd *tx_req;
struct hns3_hw *hw = &hns->hw;
struct hns3_cmd_desc desc;
int ret;
if ((vlan_type != ETH_VLAN_TYPE_INNER &&
vlan_type != ETH_VLAN_TYPE_OUTER)) {
hns3_err(hw, "Unsupported vlan type, vlan_type =%d", vlan_type);
return -EINVAL;
}
if (tpid != RTE_ETHER_TYPE_VLAN) {
hns3_err(hw, "Unsupported vlan tpid, vlan_type =%d", vlan_type);
return -EINVAL;
}
hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_TYPE_ID, false);
rx_req = (struct hns3_rx_vlan_type_cfg_cmd *)desc.data;
if (vlan_type == ETH_VLAN_TYPE_OUTER) {
rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
} else if (vlan_type == ETH_VLAN_TYPE_INNER) {
rx_req->ot_fst_vlan_type = rte_cpu_to_le_16(tpid);
rx_req->ot_sec_vlan_type = rte_cpu_to_le_16(tpid);
rx_req->in_fst_vlan_type = rte_cpu_to_le_16(tpid);
rx_req->in_sec_vlan_type = rte_cpu_to_le_16(tpid);
}
ret = hns3_cmd_send(hw, &desc, 1);
if (ret) {
hns3_err(hw, "Send rxvlan protocol type command fail, ret =%d",
ret);
return ret;
}
hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_VLAN_INSERT, false);
tx_req = (struct hns3_tx_vlan_type_cfg_cmd *)desc.data;
tx_req->ot_vlan_type = rte_cpu_to_le_16(tpid);
tx_req->in_vlan_type = rte_cpu_to_le_16(tpid);
ret = hns3_cmd_send(hw, &desc, 1);
if (ret)
hns3_err(hw, "Send txvlan protocol type command fail, ret =%d",
ret);
return ret;
}
static int
hns3_vlan_tpid_set(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type,
uint16_t tpid)
{
struct hns3_adapter *hns = dev->data->dev_private;
struct hns3_hw *hw = &hns->hw;
int ret;
rte_spinlock_lock(&hw->lock);
ret = hns3_vlan_tpid_configure(hns, vlan_type, tpid);
rte_spinlock_unlock(&hw->lock);
return ret;
}
static int
hns3_set_vlan_rx_offload_cfg(struct hns3_adapter *hns,
struct hns3_rx_vtag_cfg *vcfg)
{
struct hns3_vport_vtag_rx_cfg_cmd *req;
struct hns3_hw *hw = &hns->hw;
struct hns3_cmd_desc desc;
uint16_t vport_id;
uint8_t bitmap;
int ret;
hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_RX_CFG, false);
req = (struct hns3_vport_vtag_rx_cfg_cmd *)desc.data;
hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG1_EN_B,
vcfg->strip_tag1_en ? 1 : 0);
hns3_set_bit(req->vport_vlan_cfg, HNS3_REM_TAG2_EN_B,
vcfg->strip_tag2_en ? 1 : 0);
hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG1_EN_B,
vcfg->vlan1_vlan_prionly ? 1 : 0);
hns3_set_bit(req->vport_vlan_cfg, HNS3_SHOW_TAG2_EN_B,
vcfg->vlan2_vlan_prionly ? 1 : 0);
/* firmware will ignore this configuration for PCI_REVISION_ID_HIP08 */
hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG1_EN_B,
vcfg->strip_tag1_discard_en ? 1 : 0);
hns3_set_bit(req->vport_vlan_cfg, HNS3_DISCARD_TAG2_EN_B,
vcfg->strip_tag2_discard_en ? 1 : 0);
/*
* In current version VF is not supported when PF is driven by DPDK
* driver, just need to configure parameters for PF vport.
*/
vport_id = HNS3_PF_FUNC_ID;
req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
req->vf_bitmap[req->vf_offset] = bitmap;
ret = hns3_cmd_send(hw, &desc, 1);
if (ret)
hns3_err(hw, "Send port rxvlan cfg command fail, ret =%d", ret);
return ret;
}
static void
hns3_update_rx_offload_cfg(struct hns3_adapter *hns,
struct hns3_rx_vtag_cfg *vcfg)
{
struct hns3_pf *pf = &hns->pf;
memcpy(&pf->vtag_config.rx_vcfg, vcfg, sizeof(pf->vtag_config.rx_vcfg));
}
static void
hns3_update_tx_offload_cfg(struct hns3_adapter *hns,
struct hns3_tx_vtag_cfg *vcfg)
{
struct hns3_pf *pf = &hns->pf;
memcpy(&pf->vtag_config.tx_vcfg, vcfg, sizeof(pf->vtag_config.tx_vcfg));
}
static int
hns3_en_hw_strip_rxvtag(struct hns3_adapter *hns, bool enable)
{
struct hns3_rx_vtag_cfg rxvlan_cfg;
struct hns3_hw *hw = &hns->hw;
int ret;
if (hw->port_base_vlan_cfg.state == HNS3_PORT_BASE_VLAN_DISABLE) {
rxvlan_cfg.strip_tag1_en = false;
rxvlan_cfg.strip_tag2_en = enable;
rxvlan_cfg.strip_tag2_discard_en = false;
} else {
rxvlan_cfg.strip_tag1_en = enable;
rxvlan_cfg.strip_tag2_en = true;
rxvlan_cfg.strip_tag2_discard_en = true;
}
rxvlan_cfg.strip_tag1_discard_en = false;
rxvlan_cfg.vlan1_vlan_prionly = false;
rxvlan_cfg.vlan2_vlan_prionly = false;
rxvlan_cfg.rx_vlan_offload_en = enable;
ret = hns3_set_vlan_rx_offload_cfg(hns, &rxvlan_cfg);
if (ret) {
hns3_err(hw, "%s strip rx vtag failed, ret = %d.",
enable ? "enable" : "disable", ret);
return ret;
}
hns3_update_rx_offload_cfg(hns, &rxvlan_cfg);
return ret;
}
static int
hns3_set_vlan_filter_ctrl(struct hns3_hw *hw, uint8_t vlan_type,
uint8_t fe_type, bool filter_en, uint8_t vf_id)
{
struct hns3_vlan_filter_ctrl_cmd *req;
struct hns3_cmd_desc desc;
int ret;
hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_FILTER_CTRL, false);
req = (struct hns3_vlan_filter_ctrl_cmd *)desc.data;
req->vlan_type = vlan_type;
req->vlan_fe = filter_en ? fe_type : 0;
req->vf_id = vf_id;
ret = hns3_cmd_send(hw, &desc, 1);
if (ret)
hns3_err(hw, "set vlan filter fail, ret =%d", ret);
return ret;
}
static int
hns3_vlan_filter_init(struct hns3_adapter *hns)
{
struct hns3_hw *hw = &hns->hw;
int ret;
ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_VF,
HNS3_FILTER_FE_EGRESS, false,
HNS3_PF_FUNC_ID);
if (ret) {
hns3_err(hw, "failed to init vf vlan filter, ret = %d", ret);
return ret;
}
ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
HNS3_FILTER_FE_INGRESS, false,
HNS3_PF_FUNC_ID);
if (ret)
hns3_err(hw, "failed to init port vlan filter, ret = %d", ret);
return ret;
}
static int
hns3_enable_vlan_filter(struct hns3_adapter *hns, bool enable)
{
struct hns3_hw *hw = &hns->hw;
int ret;
ret = hns3_set_vlan_filter_ctrl(hw, HNS3_FILTER_TYPE_PORT,
HNS3_FILTER_FE_INGRESS, enable,
HNS3_PF_FUNC_ID);
if (ret)
hns3_err(hw, "failed to %s port vlan filter, ret = %d",
enable ? "enable" : "disable", ret);
return ret;
}
static int
hns3_vlan_offload_set(struct rte_eth_dev *dev, int mask)
{
struct hns3_adapter *hns = dev->data->dev_private;
struct hns3_hw *hw = &hns->hw;
struct rte_eth_rxmode *rxmode;
unsigned int tmp_mask;
bool enable;
int ret = 0;
rte_spinlock_lock(&hw->lock);
rxmode = &dev->data->dev_conf.rxmode;
tmp_mask = (unsigned int)mask;
if (tmp_mask & ETH_VLAN_FILTER_MASK) {
/* ignore vlan filter configuration during promiscuous mode */
if (!dev->data->promiscuous) {
/* Enable or disable VLAN filter */
enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER ?
true : false;
ret = hns3_enable_vlan_filter(hns, enable);
if (ret) {
rte_spinlock_unlock(&hw->lock);
hns3_err(hw, "failed to %s rx filter, ret = %d",
enable ? "enable" : "disable", ret);
return ret;
}
}
}
if (tmp_mask & ETH_VLAN_STRIP_MASK) {
/* Enable or disable VLAN stripping */
enable = rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP ?
true : false;
ret = hns3_en_hw_strip_rxvtag(hns, enable);
if (ret) {
rte_spinlock_unlock(&hw->lock);
hns3_err(hw, "failed to %s rx strip, ret = %d",
enable ? "enable" : "disable", ret);
return ret;
}
}
rte_spinlock_unlock(&hw->lock);
return ret;
}
static int
hns3_set_vlan_tx_offload_cfg(struct hns3_adapter *hns,
struct hns3_tx_vtag_cfg *vcfg)
{
struct hns3_vport_vtag_tx_cfg_cmd *req;
struct hns3_cmd_desc desc;
struct hns3_hw *hw = &hns->hw;
uint16_t vport_id;
uint8_t bitmap;
int ret;
hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_VLAN_PORT_TX_CFG, false);
req = (struct hns3_vport_vtag_tx_cfg_cmd *)desc.data;
req->def_vlan_tag1 = vcfg->default_tag1;
req->def_vlan_tag2 = vcfg->default_tag2;
hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG1_B,
vcfg->accept_tag1 ? 1 : 0);
hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG1_B,
vcfg->accept_untag1 ? 1 : 0);
hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_TAG2_B,
vcfg->accept_tag2 ? 1 : 0);
hns3_set_bit(req->vport_vlan_cfg, HNS3_ACCEPT_UNTAG2_B,
vcfg->accept_untag2 ? 1 : 0);
hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG1_EN_B,
vcfg->insert_tag1_en ? 1 : 0);
hns3_set_bit(req->vport_vlan_cfg, HNS3_PORT_INS_TAG2_EN_B,
vcfg->insert_tag2_en ? 1 : 0);
hns3_set_bit(req->vport_vlan_cfg, HNS3_CFG_NIC_ROCE_SEL_B, 0);
/* firmware will ignore this configuration for PCI_REVISION_ID_HIP08 */
hns3_set_bit(req->vport_vlan_cfg, HNS3_TAG_SHIFT_MODE_EN_B,
vcfg->tag_shift_mode_en ? 1 : 0);
/*
* In current version VF is not supported when PF is driven by DPDK
* driver, just need to configure parameters for PF vport.
*/
vport_id = HNS3_PF_FUNC_ID;
req->vf_offset = vport_id / HNS3_VF_NUM_PER_CMD;
bitmap = 1 << (vport_id % HNS3_VF_NUM_PER_BYTE);
req->vf_bitmap[req->vf_offset] = bitmap;
ret = hns3_cmd_send(hw, &desc, 1);
if (ret)
hns3_err(hw, "Send port txvlan cfg command fail, ret =%d", ret);
return ret;
}
static int
hns3_vlan_txvlan_cfg(struct hns3_adapter *hns, uint16_t port_base_vlan_state,
uint16_t pvid)
{
struct hns3_hw *hw = &hns->hw;
struct hns3_tx_vtag_cfg txvlan_cfg;
int ret;
if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_DISABLE) {
txvlan_cfg.accept_tag1 = true;
txvlan_cfg.insert_tag1_en = false;
txvlan_cfg.default_tag1 = 0;
} else {
txvlan_cfg.accept_tag1 =
hw->vlan_mode == HNS3_HW_SHIFT_AND_DISCARD_MODE;
txvlan_cfg.insert_tag1_en = true;
txvlan_cfg.default_tag1 = pvid;
}
txvlan_cfg.accept_untag1 = true;
txvlan_cfg.accept_tag2 = true;
txvlan_cfg.accept_untag2 = true;
txvlan_cfg.insert_tag2_en = false;
txvlan_cfg.default_tag2 = 0;
txvlan_cfg.tag_shift_mode_en = true;
ret = hns3_set_vlan_tx_offload_cfg(hns, &txvlan_cfg);
if (ret) {
hns3_err(hw, "pf vlan set pvid failed, pvid =%u ,ret =%d", pvid,
ret);
return ret;
}
hns3_update_tx_offload_cfg(hns, &txvlan_cfg);
return ret;
}
static void
hns3_rm_all_vlan_table(struct hns3_adapter *hns, bool is_del_list)
{
struct hns3_user_vlan_table *vlan_entry;
struct hns3_pf *pf = &hns->pf;
LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
if (vlan_entry->hd_tbl_status) {
hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 0);
vlan_entry->hd_tbl_status = false;
}
}
if (is_del_list) {
vlan_entry = LIST_FIRST(&pf->vlan_list);
while (vlan_entry) {
LIST_REMOVE(vlan_entry, next);
rte_free(vlan_entry);
vlan_entry = LIST_FIRST(&pf->vlan_list);
}
}
}
static void
hns3_add_all_vlan_table(struct hns3_adapter *hns)
{
struct hns3_user_vlan_table *vlan_entry;
struct hns3_pf *pf = &hns->pf;
LIST_FOREACH(vlan_entry, &pf->vlan_list, next) {
if (!vlan_entry->hd_tbl_status) {
hns3_set_port_vlan_filter(hns, vlan_entry->vlan_id, 1);
vlan_entry->hd_tbl_status = true;
}
}
}
static void
hns3_remove_all_vlan_table(struct hns3_adapter *hns)
{
struct hns3_hw *hw = &hns->hw;
int ret;
hns3_rm_all_vlan_table(hns, true);
if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID) {
ret = hns3_set_port_vlan_filter(hns,
hw->port_base_vlan_cfg.pvid, 0);
if (ret) {
hns3_err(hw, "Failed to remove all vlan table, ret =%d",
ret);
return;
}
}
}
static int
hns3_update_vlan_filter_entries(struct hns3_adapter *hns,
uint16_t port_base_vlan_state, uint16_t new_pvid)
{
struct hns3_hw *hw = &hns->hw;
uint16_t old_pvid;
int ret;
if (port_base_vlan_state == HNS3_PORT_BASE_VLAN_ENABLE) {
old_pvid = hw->port_base_vlan_cfg.pvid;
if (old_pvid != HNS3_INVALID_PVID) {
ret = hns3_set_port_vlan_filter(hns, old_pvid, 0);
if (ret) {
hns3_err(hw, "failed to remove old pvid %u, "
"ret = %d", old_pvid, ret);
return ret;
}
}
hns3_rm_all_vlan_table(hns, false);
ret = hns3_set_port_vlan_filter(hns, new_pvid, 1);
if (ret) {
hns3_err(hw, "failed to add new pvid %u, ret = %d",
new_pvid, ret);
return ret;
}
} else {
ret = hns3_set_port_vlan_filter(hns, new_pvid, 0);
if (ret) {
hns3_err(hw, "failed to remove pvid %u, ret = %d",
new_pvid, ret);
return ret;
}
hns3_add_all_vlan_table(hns);
}
return 0;
}
static int
hns3_en_pvid_strip(struct hns3_adapter *hns, int on)
{
struct hns3_rx_vtag_cfg *old_cfg = &hns->pf.vtag_config.rx_vcfg;
struct hns3_rx_vtag_cfg rx_vlan_cfg;
bool rx_strip_en;
int ret;
rx_strip_en = old_cfg->rx_vlan_offload_en;
if (on) {
rx_vlan_cfg.strip_tag1_en = rx_strip_en;
rx_vlan_cfg.strip_tag2_en = true;
rx_vlan_cfg.strip_tag2_discard_en = true;
} else {
rx_vlan_cfg.strip_tag1_en = false;
rx_vlan_cfg.strip_tag2_en = rx_strip_en;
rx_vlan_cfg.strip_tag2_discard_en = false;
}
rx_vlan_cfg.strip_tag1_discard_en = false;
rx_vlan_cfg.vlan1_vlan_prionly = false;
rx_vlan_cfg.vlan2_vlan_prionly = false;
rx_vlan_cfg.rx_vlan_offload_en = old_cfg->rx_vlan_offload_en;
ret = hns3_set_vlan_rx_offload_cfg(hns, &rx_vlan_cfg);
if (ret)
return ret;
hns3_update_rx_offload_cfg(hns, &rx_vlan_cfg);
return ret;
}
static int
hns3_vlan_pvid_configure(struct hns3_adapter *hns, uint16_t pvid, int on)
{
struct hns3_hw *hw = &hns->hw;
uint16_t port_base_vlan_state;
int ret, err;
if (on == 0 && pvid != hw->port_base_vlan_cfg.pvid) {
if (hw->port_base_vlan_cfg.pvid != HNS3_INVALID_PVID)
hns3_warn(hw, "Invalid operation! As current pvid set "
"is %u, disable pvid %u is invalid",
hw->port_base_vlan_cfg.pvid, pvid);
return 0;
}
port_base_vlan_state = on ? HNS3_PORT_BASE_VLAN_ENABLE :
HNS3_PORT_BASE_VLAN_DISABLE;
ret = hns3_vlan_txvlan_cfg(hns, port_base_vlan_state, pvid);
if (ret) {
hns3_err(hw, "failed to config tx vlan for pvid, ret = %d",
ret);
return ret;
}
ret = hns3_en_pvid_strip(hns, on);
if (ret) {
hns3_err(hw, "failed to config rx vlan strip for pvid, "
"ret = %d", ret);
goto pvid_vlan_strip_fail;
}
if (pvid == HNS3_INVALID_PVID)
goto out;
ret = hns3_update_vlan_filter_entries(hns, port_base_vlan_state, pvid);
if (ret) {
hns3_err(hw, "failed to update vlan filter entries, ret = %d",
ret);
goto vlan_filter_set_fail;
}
out:
hw->port_base_vlan_cfg.state = port_base_vlan_state;
hw->port_base_vlan_cfg.pvid = on ? pvid : HNS3_INVALID_PVID;
return ret;
vlan_filter_set_fail:
err = hns3_en_pvid_strip(hns, hw->port_base_vlan_cfg.state ==
HNS3_PORT_BASE_VLAN_ENABLE);
if (err)
hns3_err(hw, "fail to rollback pvid strip, ret = %d", err);
pvid_vlan_strip_fail:
err = hns3_vlan_txvlan_cfg(hns, hw->port_base_vlan_cfg.state,
hw->port_base_vlan_cfg.pvid);
if (err)
hns3_err(hw, "fail to rollback txvlan status, ret = %d", err);
return ret;
}
static int
hns3_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
{
struct hns3_adapter *hns = dev->data->dev_private;
struct hns3_hw *hw = &hns->hw;
bool pvid_en_state_change;
uint16_t pvid_state;
int ret;
if (pvid > RTE_ETHER_MAX_VLAN_ID) {
hns3_err(hw, "Invalid vlan_id = %u > %d", pvid,
RTE_ETHER_MAX_VLAN_ID);
return -EINVAL;
}
/*
* If PVID configuration state change, should refresh the PVID
* configuration state in struct hns3_tx_queue/hns3_rx_queue.
*/
pvid_state = hw->port_base_vlan_cfg.state;
if ((on && pvid_state == HNS3_PORT_BASE_VLAN_ENABLE) ||
(!on && pvid_state == HNS3_PORT_BASE_VLAN_DISABLE))
pvid_en_state_change = false;
else
pvid_en_state_change = true;
rte_spinlock_lock(&hw->lock);
ret = hns3_vlan_pvid_configure(hns, pvid, on);
rte_spinlock_unlock(&hw->lock);
if (ret)
return ret;
/*
* Only in HNS3_SW_SHIFT_AND_MODE the PVID related operation in Tx/Rx
* need be processed by PMD.
*/
if (pvid_en_state_change &&
hw->vlan_mode == HNS3_SW_SHIFT_AND_DISCARD_MODE)
hns3_update_all_queues_pvid_proc_en(hw);
return 0;
}
static int
hns3_default_vlan_config(struct hns3_adapter *hns)
{
struct hns3_hw *hw = &hns->hw;
int ret;