-
Notifications
You must be signed in to change notification settings - Fork 4
/
i40e_pf.c
1399 lines (1215 loc) · 36.4 KB
/
i40e_pf.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*-
* BSD LICENSE
*
* Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/queue.h>
#include <stdio.h>
#include <errno.h>
#include <stdint.h>
#include <string.h>
#include <unistd.h>
#include <stdarg.h>
#include <inttypes.h>
#include <rte_string_fns.h>
#include <rte_pci.h>
#include <rte_ether.h>
#include <rte_ethdev.h>
#include <rte_memzone.h>
#include <rte_malloc.h>
#include <rte_memcpy.h>
#include "i40e_logs.h"
#include "base/i40e_prototype.h"
#include "base/i40e_adminq_cmd.h"
#include "base/i40e_type.h"
#include "i40e_ethdev.h"
#include "i40e_rxtx.h"
#include "i40e_pf.h"
#include "rte_pmd_i40e.h"
#define I40E_CFG_CRCSTRIP_DEFAULT 1
static int
i40e_pf_host_switch_queues(struct i40e_pf_vf *vf,
struct i40e_virtchnl_queue_select *qsel,
bool on);
/**
* Bind PF queues with VSI and VF.
**/
static int
i40e_pf_vf_queues_mapping(struct i40e_pf_vf *vf)
{
int i;
struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
uint16_t vsi_id = vf->vsi->vsi_id;
uint16_t vf_id = vf->vf_idx;
uint16_t nb_qps = vf->vsi->nb_qps;
uint16_t qbase = vf->vsi->base_queue;
uint16_t q1, q2;
uint32_t val;
/*
* VF should use scatter range queues. So, it needn't
* to set QBASE in this register.
*/
i40e_write_rx_ctl(hw, I40E_VSILAN_QBASE(vsi_id),
I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK);
/* Set to enable VFLAN_QTABLE[] registers valid */
I40E_WRITE_REG(hw, I40E_VPLAN_MAPENA(vf_id),
I40E_VPLAN_MAPENA_TXRX_ENA_MASK);
/* map PF queues to VF */
for (i = 0; i < nb_qps; i++) {
val = ((qbase + i) & I40E_VPLAN_QTABLE_QINDEX_MASK);
I40E_WRITE_REG(hw, I40E_VPLAN_QTABLE(i, vf_id), val);
}
/* map PF queues to VSI */
for (i = 0; i < I40E_MAX_QP_NUM_PER_VF / 2; i++) {
if (2 * i > nb_qps - 1)
q1 = I40E_VSILAN_QTABLE_QINDEX_0_MASK;
else
q1 = qbase + 2 * i;
if (2 * i + 1 > nb_qps - 1)
q2 = I40E_VSILAN_QTABLE_QINDEX_0_MASK;
else
q2 = qbase + 2 * i + 1;
val = (q2 << I40E_VSILAN_QTABLE_QINDEX_1_SHIFT) + q1;
i40e_write_rx_ctl(hw, I40E_VSILAN_QTABLE(i, vsi_id), val);
}
I40E_WRITE_FLUSH(hw);
return I40E_SUCCESS;
}
/**
* Proceed VF reset operation.
*/
int
i40e_pf_host_vf_reset(struct i40e_pf_vf *vf, bool do_hw_reset)
{
uint32_t val, i;
struct i40e_hw *hw;
struct i40e_pf *pf;
uint16_t vf_id, abs_vf_id, vf_msix_num;
int ret;
struct i40e_virtchnl_queue_select qsel;
if (vf == NULL)
return -EINVAL;
pf = vf->pf;
hw = I40E_PF_TO_HW(vf->pf);
vf_id = vf->vf_idx;
abs_vf_id = vf_id + hw->func_caps.vf_base_id;
/* Notify VF that we are in VFR progress */
I40E_WRITE_REG(hw, I40E_VFGEN_RSTAT1(vf_id), I40E_VFR_INPROGRESS);
/*
* If require a SW VF reset, a VFLR interrupt will be generated,
* this function will be called again. To avoid it,
* disable interrupt first.
*/
if (do_hw_reset) {
vf->state = I40E_VF_INRESET;
val = I40E_READ_REG(hw, I40E_VPGEN_VFRTRIG(vf_id));
val |= I40E_VPGEN_VFRTRIG_VFSWR_MASK;
I40E_WRITE_REG(hw, I40E_VPGEN_VFRTRIG(vf_id), val);
I40E_WRITE_FLUSH(hw);
}
#define VFRESET_MAX_WAIT_CNT 100
/* Wait until VF reset is done */
for (i = 0; i < VFRESET_MAX_WAIT_CNT; i++) {
rte_delay_us(10);
val = I40E_READ_REG(hw, I40E_VPGEN_VFRSTAT(vf_id));
if (val & I40E_VPGEN_VFRSTAT_VFRD_MASK)
break;
}
if (i >= VFRESET_MAX_WAIT_CNT) {
PMD_DRV_LOG(ERR, "VF reset timeout");
return -ETIMEDOUT;
}
/* This is not first time to do reset, do cleanup job first */
if (vf->vsi) {
/* Disable queues */
memset(&qsel, 0, sizeof(qsel));
for (i = 0; i < vf->vsi->nb_qps; i++)
qsel.rx_queues |= 1 << i;
qsel.tx_queues = qsel.rx_queues;
ret = i40e_pf_host_switch_queues(vf, &qsel, false);
if (ret != I40E_SUCCESS) {
PMD_DRV_LOG(ERR, "Disable VF queues failed");
return -EFAULT;
}
/* Disable VF interrupt setting */
vf_msix_num = hw->func_caps.num_msix_vectors_vf;
for (i = 0; i < vf_msix_num; i++) {
if (!i)
val = I40E_VFINT_DYN_CTL0(vf_id);
else
val = I40E_VFINT_DYN_CTLN(((vf_msix_num - 1) *
(vf_id)) + (i - 1));
I40E_WRITE_REG(hw, val, I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
}
I40E_WRITE_FLUSH(hw);
/* remove VSI */
ret = i40e_vsi_release(vf->vsi);
if (ret != I40E_SUCCESS) {
PMD_DRV_LOG(ERR, "Release VSI failed");
return -EFAULT;
}
}
#define I40E_VF_PCI_ADDR 0xAA
#define I40E_VF_PEND_MASK 0x20
/* Check the pending transactions of this VF */
/* Use absolute VF id, refer to datasheet for details */
I40E_WRITE_REG(hw, I40E_PF_PCI_CIAA, I40E_VF_PCI_ADDR |
(abs_vf_id << I40E_PF_PCI_CIAA_VF_NUM_SHIFT));
for (i = 0; i < VFRESET_MAX_WAIT_CNT; i++) {
rte_delay_us(1);
val = I40E_READ_REG(hw, I40E_PF_PCI_CIAD);
if ((val & I40E_VF_PEND_MASK) == 0)
break;
}
if (i >= VFRESET_MAX_WAIT_CNT) {
PMD_DRV_LOG(ERR, "Wait VF PCI transaction end timeout");
return -ETIMEDOUT;
}
/* Reset done, Set COMPLETE flag and clear reset bit */
I40E_WRITE_REG(hw, I40E_VFGEN_RSTAT1(vf_id), I40E_VFR_COMPLETED);
val = I40E_READ_REG(hw, I40E_VPGEN_VFRTRIG(vf_id));
val &= ~I40E_VPGEN_VFRTRIG_VFSWR_MASK;
I40E_WRITE_REG(hw, I40E_VPGEN_VFRTRIG(vf_id), val);
vf->reset_cnt++;
I40E_WRITE_FLUSH(hw);
/* Allocate resource again */
if (pf->floating_veb && pf->floating_veb_list[vf_id]) {
vf->vsi = i40e_vsi_setup(vf->pf, I40E_VSI_SRIOV,
NULL, vf->vf_idx);
} else {
vf->vsi = i40e_vsi_setup(vf->pf, I40E_VSI_SRIOV,
vf->pf->main_vsi, vf->vf_idx);
}
if (vf->vsi == NULL) {
PMD_DRV_LOG(ERR, "Add vsi failed");
return -EFAULT;
}
ret = i40e_pf_vf_queues_mapping(vf);
if (ret != I40E_SUCCESS) {
PMD_DRV_LOG(ERR, "queue mapping error");
i40e_vsi_release(vf->vsi);
return -EFAULT;
}
I40E_WRITE_REG(hw, I40E_VFGEN_RSTAT1(vf_id), I40E_VFR_VFACTIVE);
return ret;
}
int
i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf,
uint32_t opcode,
uint32_t retval,
uint8_t *msg,
uint16_t msglen)
{
struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
uint16_t abs_vf_id = hw->func_caps.vf_base_id + vf->vf_idx;
int ret;
ret = i40e_aq_send_msg_to_vf(hw, abs_vf_id, opcode, retval,
msg, msglen, NULL);
if (ret) {
PMD_INIT_LOG(ERR, "Fail to send message to VF, err %u",
hw->aq.asq_last_status);
}
return ret;
}
static void
i40e_pf_host_process_cmd_version(struct i40e_pf_vf *vf, bool b_op)
{
struct i40e_virtchnl_version_info info;
/* Respond like a Linux PF host in order to support both DPDK VF and
* Linux VF driver. The expense is original DPDK host specific feature
* like CFG_VLAN_PVID and CONFIG_VSI_QUEUES_EXT will not available.
*
* DPDK VF also can't identify host driver by version number returned.
* It always assume talking with Linux PF.
*/
info.major = I40E_VIRTCHNL_VERSION_MAJOR;
info.minor = I40E_VIRTCHNL_VERSION_MINOR_NO_VF_CAPS;
if (b_op)
i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_VERSION,
I40E_SUCCESS,
(uint8_t *)&info,
sizeof(info));
else
i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_VERSION,
I40E_NOT_SUPPORTED,
(uint8_t *)&info,
sizeof(info));
}
static int
i40e_pf_host_process_cmd_reset_vf(struct i40e_pf_vf *vf)
{
i40e_pf_host_vf_reset(vf, 1);
/* No feedback will be sent to VF for VFLR */
return I40E_SUCCESS;
}
static int
i40e_pf_host_process_cmd_get_vf_resource(struct i40e_pf_vf *vf, bool b_op)
{
struct i40e_virtchnl_vf_resource *vf_res = NULL;
struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
uint32_t len = 0;
int ret = I40E_SUCCESS;
if (!b_op) {
i40e_pf_host_send_msg_to_vf(vf,
I40E_VIRTCHNL_OP_GET_VF_RESOURCES,
I40E_NOT_SUPPORTED, NULL, 0);
return ret;
}
/* only have 1 VSI by default */
len = sizeof(struct i40e_virtchnl_vf_resource) +
I40E_DEFAULT_VF_VSI_NUM *
sizeof(struct i40e_virtchnl_vsi_resource);
vf_res = rte_zmalloc("i40e_vf_res", len, 0);
if (vf_res == NULL) {
PMD_DRV_LOG(ERR, "failed to allocate mem");
ret = I40E_ERR_NO_MEMORY;
vf_res = NULL;
len = 0;
goto send_msg;
}
vf_res->vf_offload_flags = I40E_VIRTCHNL_VF_OFFLOAD_L2 |
I40E_VIRTCHNL_VF_OFFLOAD_VLAN;
vf_res->max_vectors = hw->func_caps.num_msix_vectors_vf;
vf_res->num_queue_pairs = vf->vsi->nb_qps;
vf_res->num_vsis = I40E_DEFAULT_VF_VSI_NUM;
/* Change below setting if PF host can support more VSIs for VF */
vf_res->vsi_res[0].vsi_type = I40E_VSI_SRIOV;
vf_res->vsi_res[0].vsi_id = vf->vsi->vsi_id;
vf_res->vsi_res[0].num_queue_pairs = vf->vsi->nb_qps;
ether_addr_copy(&vf->mac_addr,
(struct ether_addr *)vf_res->vsi_res[0].default_mac_addr);
send_msg:
i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_GET_VF_RESOURCES,
ret, (uint8_t *)vf_res, len);
rte_free(vf_res);
return ret;
}
static int
i40e_pf_host_hmc_config_rxq(struct i40e_hw *hw,
struct i40e_pf_vf *vf,
struct i40e_virtchnl_rxq_info *rxq,
uint8_t crcstrip)
{
int err = I40E_SUCCESS;
struct i40e_hmc_obj_rxq rx_ctx;
uint16_t abs_queue_id = vf->vsi->base_queue + rxq->queue_id;
/* Clear the context structure first */
memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
rx_ctx.dbuff = rxq->databuffer_size >> I40E_RXQ_CTX_DBUFF_SHIFT;
rx_ctx.hbuff = rxq->hdr_size >> I40E_RXQ_CTX_HBUFF_SHIFT;
rx_ctx.base = rxq->dma_ring_addr / I40E_QUEUE_BASE_ADDR_UNIT;
rx_ctx.qlen = rxq->ring_len;
#ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
rx_ctx.dsize = 1;
#endif
if (rxq->splithdr_enabled) {
rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
rx_ctx.dtype = i40e_header_split_enabled;
} else {
rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
rx_ctx.dtype = i40e_header_split_none;
}
rx_ctx.rxmax = rxq->max_pkt_size;
rx_ctx.tphrdesc_ena = 1;
rx_ctx.tphwdesc_ena = 1;
rx_ctx.tphdata_ena = 1;
rx_ctx.tphhead_ena = 1;
rx_ctx.lrxqthresh = 2;
rx_ctx.crcstrip = crcstrip;
rx_ctx.l2tsel = 1;
rx_ctx.prefena = 1;
err = i40e_clear_lan_rx_queue_context(hw, abs_queue_id);
if (err != I40E_SUCCESS)
return err;
err = i40e_set_lan_rx_queue_context(hw, abs_queue_id, &rx_ctx);
return err;
}
static int
i40e_pf_host_hmc_config_txq(struct i40e_hw *hw,
struct i40e_pf_vf *vf,
struct i40e_virtchnl_txq_info *txq)
{
int err = I40E_SUCCESS;
struct i40e_hmc_obj_txq tx_ctx;
uint32_t qtx_ctl;
uint16_t abs_queue_id = vf->vsi->base_queue + txq->queue_id;
/* clear the context structure first */
memset(&tx_ctx, 0, sizeof(tx_ctx));
tx_ctx.base = txq->dma_ring_addr / I40E_QUEUE_BASE_ADDR_UNIT;
tx_ctx.qlen = txq->ring_len;
tx_ctx.rdylist = rte_le_to_cpu_16(vf->vsi->info.qs_handle[0]);
tx_ctx.head_wb_ena = txq->headwb_enabled;
tx_ctx.head_wb_addr = txq->dma_headwb_addr;
err = i40e_clear_lan_tx_queue_context(hw, abs_queue_id);
if (err != I40E_SUCCESS)
return err;
err = i40e_set_lan_tx_queue_context(hw, abs_queue_id, &tx_ctx);
if (err != I40E_SUCCESS)
return err;
/* bind queue with VF function, since TX/QX will appear in pair,
* so only has QTX_CTL to set.
*/
qtx_ctl = (I40E_QTX_CTL_VF_QUEUE << I40E_QTX_CTL_PFVF_Q_SHIFT) |
((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
I40E_QTX_CTL_PF_INDX_MASK) |
(((vf->vf_idx + hw->func_caps.vf_base_id) <<
I40E_QTX_CTL_VFVM_INDX_SHIFT) &
I40E_QTX_CTL_VFVM_INDX_MASK);
I40E_WRITE_REG(hw, I40E_QTX_CTL(abs_queue_id), qtx_ctl);
I40E_WRITE_FLUSH(hw);
return I40E_SUCCESS;
}
static int
i40e_pf_host_process_cmd_config_vsi_queues(struct i40e_pf_vf *vf,
uint8_t *msg,
uint16_t msglen,
bool b_op)
{
struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
struct i40e_vsi *vsi = vf->vsi;
struct i40e_virtchnl_vsi_queue_config_info *vc_vqci =
(struct i40e_virtchnl_vsi_queue_config_info *)msg;
struct i40e_virtchnl_queue_pair_info *vc_qpi;
int i, ret = I40E_SUCCESS;
if (!b_op) {
i40e_pf_host_send_msg_to_vf(vf,
I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES,
I40E_NOT_SUPPORTED, NULL, 0);
return ret;
}
if (!msg || vc_vqci->num_queue_pairs > vsi->nb_qps ||
vc_vqci->num_queue_pairs > I40E_MAX_VSI_QP ||
msglen < I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci,
vc_vqci->num_queue_pairs)) {
PMD_DRV_LOG(ERR, "vsi_queue_config_info argument wrong\n");
ret = I40E_ERR_PARAM;
goto send_msg;
}
vc_qpi = vc_vqci->qpair;
for (i = 0; i < vc_vqci->num_queue_pairs; i++) {
if (vc_qpi[i].rxq.queue_id > vsi->nb_qps - 1 ||
vc_qpi[i].txq.queue_id > vsi->nb_qps - 1) {
ret = I40E_ERR_PARAM;
goto send_msg;
}
/*
* Apply VF RX queue setting to HMC.
* If the opcode is I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT,
* then the extra information of
* 'struct i40e_virtchnl_queue_pair_extra_info' is needed,
* otherwise set the last parameter to NULL.
*/
if (i40e_pf_host_hmc_config_rxq(hw, vf, &vc_qpi[i].rxq,
I40E_CFG_CRCSTRIP_DEFAULT) != I40E_SUCCESS) {
PMD_DRV_LOG(ERR, "Configure RX queue HMC failed");
ret = I40E_ERR_PARAM;
goto send_msg;
}
/* Apply VF TX queue setting to HMC */
if (i40e_pf_host_hmc_config_txq(hw, vf,
&vc_qpi[i].txq) != I40E_SUCCESS) {
PMD_DRV_LOG(ERR, "Configure TX queue HMC failed");
ret = I40E_ERR_PARAM;
goto send_msg;
}
}
send_msg:
i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES,
ret, NULL, 0);
return ret;
}
static int
i40e_pf_host_process_cmd_config_vsi_queues_ext(struct i40e_pf_vf *vf,
uint8_t *msg,
uint16_t msglen,
bool b_op)
{
struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
struct i40e_vsi *vsi = vf->vsi;
struct i40e_virtchnl_vsi_queue_config_ext_info *vc_vqcei =
(struct i40e_virtchnl_vsi_queue_config_ext_info *)msg;
struct i40e_virtchnl_queue_pair_ext_info *vc_qpei;
int i, ret = I40E_SUCCESS;
if (!b_op) {
i40e_pf_host_send_msg_to_vf(
vf,
I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT,
I40E_NOT_SUPPORTED, NULL, 0);
return ret;
}
if (!msg || vc_vqcei->num_queue_pairs > vsi->nb_qps ||
vc_vqcei->num_queue_pairs > I40E_MAX_VSI_QP ||
msglen < I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqcei,
vc_vqcei->num_queue_pairs)) {
PMD_DRV_LOG(ERR, "vsi_queue_config_ext_info argument wrong\n");
ret = I40E_ERR_PARAM;
goto send_msg;
}
vc_qpei = vc_vqcei->qpair;
for (i = 0; i < vc_vqcei->num_queue_pairs; i++) {
if (vc_qpei[i].rxq.queue_id > vsi->nb_qps - 1 ||
vc_qpei[i].txq.queue_id > vsi->nb_qps - 1) {
ret = I40E_ERR_PARAM;
goto send_msg;
}
/*
* Apply VF RX queue setting to HMC.
* If the opcode is I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT,
* then the extra information of
* 'struct i40e_virtchnl_queue_pair_ext_info' is needed,
* otherwise set the last parameter to NULL.
*/
if (i40e_pf_host_hmc_config_rxq(hw, vf, &vc_qpei[i].rxq,
vc_qpei[i].rxq_ext.crcstrip) != I40E_SUCCESS) {
PMD_DRV_LOG(ERR, "Configure RX queue HMC failed");
ret = I40E_ERR_PARAM;
goto send_msg;
}
/* Apply VF TX queue setting to HMC */
if (i40e_pf_host_hmc_config_txq(hw, vf, &vc_qpei[i].txq) !=
I40E_SUCCESS) {
PMD_DRV_LOG(ERR, "Configure TX queue HMC failed");
ret = I40E_ERR_PARAM;
goto send_msg;
}
}
send_msg:
i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT,
ret, NULL, 0);
return ret;
}
static void
i40e_pf_config_irq_link_list(struct i40e_pf_vf *vf,
struct i40e_virtchnl_vector_map *vvm)
{
#define BITS_PER_CHAR 8
uint64_t linklistmap = 0, tempmap;
struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
uint16_t qid;
bool b_first_q = true;
enum i40e_queue_type qtype;
uint16_t vector_id;
uint32_t reg, reg_idx;
uint16_t itr_idx = 0, i;
vector_id = vvm->vector_id;
/* setup the head */
if (!vector_id)
reg_idx = I40E_VPINT_LNKLST0(vf->vf_idx);
else
reg_idx = I40E_VPINT_LNKLSTN(
((hw->func_caps.num_msix_vectors_vf - 1) * vf->vf_idx)
+ (vector_id - 1));
if (vvm->rxq_map == 0 && vvm->txq_map == 0) {
I40E_WRITE_REG(hw, reg_idx,
I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK);
goto cfg_irq_done;
}
/* sort all rx and tx queues */
tempmap = vvm->rxq_map;
for (i = 0; i < sizeof(vvm->rxq_map) * BITS_PER_CHAR; i++) {
if (tempmap & 0x1)
linklistmap |= (1 << (2 * i));
tempmap >>= 1;
}
tempmap = vvm->txq_map;
for (i = 0; i < sizeof(vvm->txq_map) * BITS_PER_CHAR; i++) {
if (tempmap & 0x1)
linklistmap |= (1 << (2 * i + 1));
tempmap >>= 1;
}
/* Link all rx and tx queues into a chained list */
tempmap = linklistmap;
i = 0;
b_first_q = true;
do {
if (tempmap & 0x1) {
qtype = (enum i40e_queue_type)(i % 2);
qid = vf->vsi->base_queue + i / 2;
if (b_first_q) {
/* This is header */
b_first_q = false;
reg = ((qtype <<
I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)
| qid);
} else {
/* element in the link list */
reg = (vector_id) |
(qtype << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
(qid << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
BIT(I40E_QINT_RQCTL_CAUSE_ENA_SHIFT) |
(itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT);
}
I40E_WRITE_REG(hw, reg_idx, reg);
/* find next register to program */
switch (qtype) {
case I40E_QUEUE_TYPE_RX:
reg_idx = I40E_QINT_RQCTL(qid);
itr_idx = vvm->rxitr_idx;
break;
case I40E_QUEUE_TYPE_TX:
reg_idx = I40E_QINT_TQCTL(qid);
itr_idx = vvm->txitr_idx;
break;
default:
break;
}
}
i++;
tempmap >>= 1;
} while (tempmap);
/* Terminate the link list */
reg = (vector_id) |
(0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
(0x7FF << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
BIT(I40E_QINT_RQCTL_CAUSE_ENA_SHIFT) |
(itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT);
I40E_WRITE_REG(hw, reg_idx, reg);
cfg_irq_done:
I40E_WRITE_FLUSH(hw);
}
static int
i40e_pf_host_process_cmd_config_irq_map(struct i40e_pf_vf *vf,
uint8_t *msg, uint16_t msglen,
bool b_op)
{
int ret = I40E_SUCCESS;
struct i40e_pf *pf = vf->pf;
struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
struct i40e_virtchnl_irq_map_info *irqmap =
(struct i40e_virtchnl_irq_map_info *)msg;
struct i40e_virtchnl_vector_map *map;
int i;
uint16_t vector_id;
unsigned long qbit_max;
if (!b_op) {
i40e_pf_host_send_msg_to_vf(
vf,
I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP,
I40E_NOT_SUPPORTED, NULL, 0);
return ret;
}
if (msg == NULL || msglen < sizeof(struct i40e_virtchnl_irq_map_info)) {
PMD_DRV_LOG(ERR, "buffer too short");
ret = I40E_ERR_PARAM;
goto send_msg;
}
/* PF host will support both DPDK VF or Linux VF driver, identify by
* number of vectors requested.
*/
/* DPDK VF only requires single vector */
if (irqmap->num_vectors == 1) {
/* This MSIX intr store the intr in VF range */
vf->vsi->msix_intr = irqmap->vecmap[0].vector_id;
vf->vsi->nb_msix = irqmap->num_vectors;
vf->vsi->nb_used_qps = vf->vsi->nb_qps;
/* Don't care how the TX/RX queue mapping with this vector.
* Link all VF RX queues together. Only did mapping work.
* VF can disable/enable the intr by itself.
*/
i40e_vsi_queues_bind_intr(vf->vsi);
goto send_msg;
}
/* Then, it's Linux VF driver */
qbit_max = 1 << pf->vf_nb_qp_max;
for (i = 0; i < irqmap->num_vectors; i++) {
map = &irqmap->vecmap[i];
vector_id = map->vector_id;
/* validate msg params */
if (vector_id >= hw->func_caps.num_msix_vectors_vf) {
ret = I40E_ERR_PARAM;
goto send_msg;
}
if ((map->rxq_map < qbit_max) && (map->txq_map < qbit_max)) {
i40e_pf_config_irq_link_list(vf, map);
} else {
/* configured queue size excceed limit */
ret = I40E_ERR_PARAM;
goto send_msg;
}
}
send_msg:
i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP,
ret, NULL, 0);
return ret;
}
static int
i40e_pf_host_switch_queues(struct i40e_pf_vf *vf,
struct i40e_virtchnl_queue_select *qsel,
bool on)
{
int ret = I40E_SUCCESS;
int i;
struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
uint16_t baseq = vf->vsi->base_queue;
if (qsel->rx_queues + qsel->tx_queues == 0)
return I40E_ERR_PARAM;
/* always enable RX first and disable last */
/* Enable RX if it's enable */
if (on) {
for (i = 0; i < I40E_MAX_QP_NUM_PER_VF; i++)
if (qsel->rx_queues & (1 << i)) {
ret = i40e_switch_rx_queue(hw, baseq + i, on);
if (ret != I40E_SUCCESS)
return ret;
}
}
/* Enable/Disable TX */
for (i = 0; i < I40E_MAX_QP_NUM_PER_VF; i++)
if (qsel->tx_queues & (1 << i)) {
ret = i40e_switch_tx_queue(hw, baseq + i, on);
if (ret != I40E_SUCCESS)
return ret;
}
/* disable RX last if it's disable */
if (!on) {
/* disable RX */
for (i = 0; i < I40E_MAX_QP_NUM_PER_VF; i++)
if (qsel->rx_queues & (1 << i)) {
ret = i40e_switch_rx_queue(hw, baseq + i, on);
if (ret != I40E_SUCCESS)
return ret;
}
}
return ret;
}
static int
i40e_pf_host_process_cmd_enable_queues(struct i40e_pf_vf *vf,
uint8_t *msg,
uint16_t msglen)
{
int ret = I40E_SUCCESS;
struct i40e_virtchnl_queue_select *q_sel =
(struct i40e_virtchnl_queue_select *)msg;
if (msg == NULL || msglen != sizeof(*q_sel)) {
ret = I40E_ERR_PARAM;
goto send_msg;
}
ret = i40e_pf_host_switch_queues(vf, q_sel, true);
send_msg:
i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_ENABLE_QUEUES,
ret, NULL, 0);
return ret;
}
static int
i40e_pf_host_process_cmd_disable_queues(struct i40e_pf_vf *vf,
uint8_t *msg,
uint16_t msglen,
bool b_op)
{
int ret = I40E_SUCCESS;
struct i40e_virtchnl_queue_select *q_sel =
(struct i40e_virtchnl_queue_select *)msg;
if (!b_op) {
i40e_pf_host_send_msg_to_vf(
vf,
I40E_VIRTCHNL_OP_DISABLE_QUEUES,
I40E_NOT_SUPPORTED, NULL, 0);
return ret;
}
if (msg == NULL || msglen != sizeof(*q_sel)) {
ret = I40E_ERR_PARAM;
goto send_msg;
}
ret = i40e_pf_host_switch_queues(vf, q_sel, false);
send_msg:
i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_DISABLE_QUEUES,
ret, NULL, 0);
return ret;
}
static int
i40e_pf_host_process_cmd_add_ether_address(struct i40e_pf_vf *vf,
uint8_t *msg,
uint16_t msglen,
bool b_op)
{
int ret = I40E_SUCCESS;
struct i40e_virtchnl_ether_addr_list *addr_list =
(struct i40e_virtchnl_ether_addr_list *)msg;
struct i40e_mac_filter_info filter;
int i;
struct ether_addr *mac;
if (!b_op) {
i40e_pf_host_send_msg_to_vf(
vf,
I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS,
I40E_NOT_SUPPORTED, NULL, 0);
return ret;
}
memset(&filter, 0 , sizeof(struct i40e_mac_filter_info));
if (msg == NULL || msglen <= sizeof(*addr_list)) {
PMD_DRV_LOG(ERR, "add_ether_address argument too short");
ret = I40E_ERR_PARAM;
goto send_msg;
}
for (i = 0; i < addr_list->num_elements; i++) {
mac = (struct ether_addr *)(addr_list->list[i].addr);
(void)rte_memcpy(&filter.mac_addr, mac, ETHER_ADDR_LEN);
filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
if (is_zero_ether_addr(mac) ||
i40e_vsi_add_mac(vf->vsi, &filter)) {
ret = I40E_ERR_INVALID_MAC_ADDR;
goto send_msg;
}
}
send_msg:
i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS,
ret, NULL, 0);
return ret;
}
static int
i40e_pf_host_process_cmd_del_ether_address(struct i40e_pf_vf *vf,
uint8_t *msg,
uint16_t msglen,
bool b_op)
{
int ret = I40E_SUCCESS;
struct i40e_virtchnl_ether_addr_list *addr_list =
(struct i40e_virtchnl_ether_addr_list *)msg;
int i;
struct ether_addr *mac;
if (!b_op) {
i40e_pf_host_send_msg_to_vf(
vf,
I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS,
I40E_NOT_SUPPORTED, NULL, 0);
return ret;
}
if (msg == NULL || msglen <= sizeof(*addr_list)) {
PMD_DRV_LOG(ERR, "delete_ether_address argument too short");
ret = I40E_ERR_PARAM;
goto send_msg;
}
for (i = 0; i < addr_list->num_elements; i++) {
mac = (struct ether_addr *)(addr_list->list[i].addr);
if(!is_valid_assigned_ether_addr(mac) ||
i40e_vsi_delete_mac(vf->vsi, mac)) {
ret = I40E_ERR_INVALID_MAC_ADDR;
goto send_msg;
}
}
send_msg:
i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS,
ret, NULL, 0);
return ret;
}
static int
i40e_pf_host_process_cmd_add_vlan(struct i40e_pf_vf *vf,
uint8_t *msg, uint16_t msglen,
bool b_op)
{
int ret = I40E_SUCCESS;
struct i40e_virtchnl_vlan_filter_list *vlan_filter_list =
(struct i40e_virtchnl_vlan_filter_list *)msg;
int i;
uint16_t *vid;
if (!b_op) {
i40e_pf_host_send_msg_to_vf(
vf,
I40E_VIRTCHNL_OP_ADD_VLAN,
I40E_NOT_SUPPORTED, NULL, 0);
return ret;
}
if (msg == NULL || msglen <= sizeof(*vlan_filter_list)) {
PMD_DRV_LOG(ERR, "add_vlan argument too short");
ret = I40E_ERR_PARAM;
goto send_msg;
}
vid = vlan_filter_list->vlan_id;
for (i = 0; i < vlan_filter_list->num_elements; i++) {
ret = i40e_vsi_add_vlan(vf->vsi, vid[i]);
if(ret != I40E_SUCCESS)
goto send_msg;
}
send_msg:
i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_ADD_VLAN,
ret, NULL, 0);
return ret;
}
static int
i40e_pf_host_process_cmd_del_vlan(struct i40e_pf_vf *vf,
uint8_t *msg,
uint16_t msglen,
bool b_op)
{
int ret = I40E_SUCCESS;
struct i40e_virtchnl_vlan_filter_list *vlan_filter_list =
(struct i40e_virtchnl_vlan_filter_list *)msg;
int i;
uint16_t *vid;
if (!b_op) {
i40e_pf_host_send_msg_to_vf(
vf,