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rte_acc100_pmd.c
4718 lines (4178 loc) · 136 KB
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rte_acc100_pmd.c
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/* SPDX-License-Identifier: BSD-3-Clause
* Copyright(c) 2020 Intel Corporation
*/
#include <unistd.h>
#include <rte_common.h>
#include <rte_log.h>
#include <rte_dev.h>
#include <rte_malloc.h>
#include <rte_mempool.h>
#include <rte_byteorder.h>
#include <rte_errno.h>
#include <rte_branch_prediction.h>
#include <rte_hexdump.h>
#include <rte_pci.h>
#include <rte_bus_pci.h>
#ifdef RTE_BBDEV_OFFLOAD_COST
#include <rte_cycles.h>
#endif
#include <rte_bbdev.h>
#include <rte_bbdev_pmd.h>
#include "rte_acc100_pmd.h"
#ifdef RTE_LIBRTE_BBDEV_DEBUG
RTE_LOG_REGISTER(acc100_logtype, pmd.bb.acc100, DEBUG);
#else
RTE_LOG_REGISTER(acc100_logtype, pmd.bb.acc100, NOTICE);
#endif
/* Write to MMIO register address */
static inline void
mmio_write(void *addr, uint32_t value)
{
*((volatile uint32_t *)(addr)) = rte_cpu_to_le_32(value);
}
/* Write a register of a ACC100 device */
static inline void
acc100_reg_write(struct acc100_device *d, uint32_t offset, uint32_t value)
{
void *reg_addr = RTE_PTR_ADD(d->mmio_base, offset);
mmio_write(reg_addr, value);
usleep(ACC100_LONG_WAIT);
}
/* Read a register of a ACC100 device */
static inline uint32_t
acc100_reg_read(struct acc100_device *d, uint32_t offset)
{
void *reg_addr = RTE_PTR_ADD(d->mmio_base, offset);
uint32_t ret = *((volatile uint32_t *)(reg_addr));
return rte_le_to_cpu_32(ret);
}
/* Basic Implementation of Log2 for exact 2^N */
static inline uint32_t
log2_basic(uint32_t value)
{
return (value == 0) ? 0 : rte_bsf32(value);
}
/* Calculate memory alignment offset assuming alignment is 2^N */
static inline uint32_t
calc_mem_alignment_offset(void *unaligned_virt_mem, uint32_t alignment)
{
rte_iova_t unaligned_phy_mem = rte_malloc_virt2iova(unaligned_virt_mem);
return (uint32_t)(alignment -
(unaligned_phy_mem & (alignment-1)));
}
/* Calculate the offset of the enqueue register */
static inline uint32_t
queue_offset(bool pf_device, uint8_t vf_id, uint8_t qgrp_id, uint16_t aq_id)
{
if (pf_device)
return ((vf_id << 12) + (qgrp_id << 7) + (aq_id << 3) +
HWPfQmgrIngressAq);
else
return ((qgrp_id << 7) + (aq_id << 3) +
HWVfQmgrIngressAq);
}
enum {UL_4G = 0, UL_5G, DL_4G, DL_5G, NUM_ACC};
/* Return the accelerator enum for a Queue Group Index */
static inline int
accFromQgid(int qg_idx, const struct rte_acc100_conf *acc100_conf)
{
int accQg[ACC100_NUM_QGRPS];
int NumQGroupsPerFn[NUM_ACC];
int acc, qgIdx, qgIndex = 0;
for (qgIdx = 0; qgIdx < ACC100_NUM_QGRPS; qgIdx++)
accQg[qgIdx] = 0;
NumQGroupsPerFn[UL_4G] = acc100_conf->q_ul_4g.num_qgroups;
NumQGroupsPerFn[UL_5G] = acc100_conf->q_ul_5g.num_qgroups;
NumQGroupsPerFn[DL_4G] = acc100_conf->q_dl_4g.num_qgroups;
NumQGroupsPerFn[DL_5G] = acc100_conf->q_dl_5g.num_qgroups;
for (acc = UL_4G; acc < NUM_ACC; acc++)
for (qgIdx = 0; qgIdx < NumQGroupsPerFn[acc]; qgIdx++)
accQg[qgIndex++] = acc;
acc = accQg[qg_idx];
return acc;
}
/* Return the queue topology for a Queue Group Index */
static inline void
qtopFromAcc(struct rte_acc100_queue_topology **qtop, int acc_enum,
struct rte_acc100_conf *acc100_conf)
{
struct rte_acc100_queue_topology *p_qtop;
p_qtop = NULL;
switch (acc_enum) {
case UL_4G:
p_qtop = &(acc100_conf->q_ul_4g);
break;
case UL_5G:
p_qtop = &(acc100_conf->q_ul_5g);
break;
case DL_4G:
p_qtop = &(acc100_conf->q_dl_4g);
break;
case DL_5G:
p_qtop = &(acc100_conf->q_dl_5g);
break;
default:
/* NOTREACHED */
rte_bbdev_log(ERR, "Unexpected error evaluating qtopFromAcc");
break;
}
*qtop = p_qtop;
}
/* Return the AQ depth for a Queue Group Index */
static inline int
aqDepth(int qg_idx, struct rte_acc100_conf *acc100_conf)
{
struct rte_acc100_queue_topology *q_top = NULL;
int acc_enum = accFromQgid(qg_idx, acc100_conf);
qtopFromAcc(&q_top, acc_enum, acc100_conf);
if (unlikely(q_top == NULL))
return 0;
return q_top->aq_depth_log2;
}
/* Return the AQ depth for a Queue Group Index */
static inline int
aqNum(int qg_idx, struct rte_acc100_conf *acc100_conf)
{
struct rte_acc100_queue_topology *q_top = NULL;
int acc_enum = accFromQgid(qg_idx, acc100_conf);
qtopFromAcc(&q_top, acc_enum, acc100_conf);
if (unlikely(q_top == NULL))
return 0;
return q_top->num_aqs_per_groups;
}
static void
initQTop(struct rte_acc100_conf *acc100_conf)
{
acc100_conf->q_ul_4g.num_aqs_per_groups = 0;
acc100_conf->q_ul_4g.num_qgroups = 0;
acc100_conf->q_ul_4g.first_qgroup_index = -1;
acc100_conf->q_ul_5g.num_aqs_per_groups = 0;
acc100_conf->q_ul_5g.num_qgroups = 0;
acc100_conf->q_ul_5g.first_qgroup_index = -1;
acc100_conf->q_dl_4g.num_aqs_per_groups = 0;
acc100_conf->q_dl_4g.num_qgroups = 0;
acc100_conf->q_dl_4g.first_qgroup_index = -1;
acc100_conf->q_dl_5g.num_aqs_per_groups = 0;
acc100_conf->q_dl_5g.num_qgroups = 0;
acc100_conf->q_dl_5g.first_qgroup_index = -1;
}
static inline void
updateQtop(uint8_t acc, uint8_t qg, struct rte_acc100_conf *acc100_conf,
struct acc100_device *d) {
uint32_t reg;
struct rte_acc100_queue_topology *q_top = NULL;
qtopFromAcc(&q_top, acc, acc100_conf);
if (unlikely(q_top == NULL))
return;
uint16_t aq;
q_top->num_qgroups++;
if (q_top->first_qgroup_index == -1) {
q_top->first_qgroup_index = qg;
/* Can be optimized to assume all are enabled by default */
reg = acc100_reg_read(d, queue_offset(d->pf_device,
0, qg, ACC100_NUM_AQS - 1));
if (reg & ACC100_QUEUE_ENABLE) {
q_top->num_aqs_per_groups = ACC100_NUM_AQS;
return;
}
q_top->num_aqs_per_groups = 0;
for (aq = 0; aq < ACC100_NUM_AQS; aq++) {
reg = acc100_reg_read(d, queue_offset(d->pf_device,
0, qg, aq));
if (reg & ACC100_QUEUE_ENABLE)
q_top->num_aqs_per_groups++;
}
}
}
/* Fetch configuration enabled for the PF/VF using MMIO Read (slow) */
static inline void
fetch_acc100_config(struct rte_bbdev *dev)
{
struct acc100_device *d = dev->data->dev_private;
struct rte_acc100_conf *acc100_conf = &d->acc100_conf;
const struct acc100_registry_addr *reg_addr;
uint8_t acc, qg;
uint32_t reg, reg_aq, reg_len0, reg_len1;
uint32_t reg_mode;
/* No need to retrieve the configuration is already done */
if (d->configured)
return;
/* Choose correct registry addresses for the device type */
if (d->pf_device)
reg_addr = &pf_reg_addr;
else
reg_addr = &vf_reg_addr;
d->ddr_size = (1 + acc100_reg_read(d, reg_addr->ddr_range)) << 10;
/* Single VF Bundle by VF */
acc100_conf->num_vf_bundles = 1;
initQTop(acc100_conf);
struct rte_acc100_queue_topology *q_top = NULL;
int qman_func_id[ACC100_NUM_ACCS] = {ACC100_ACCMAP_0, ACC100_ACCMAP_1,
ACC100_ACCMAP_2, ACC100_ACCMAP_3, ACC100_ACCMAP_4};
reg = acc100_reg_read(d, reg_addr->qman_group_func);
for (qg = 0; qg < ACC100_NUM_QGRPS_PER_WORD; qg++) {
reg_aq = acc100_reg_read(d,
queue_offset(d->pf_device, 0, qg, 0));
if (reg_aq & ACC100_QUEUE_ENABLE) {
uint32_t idx = (reg >> (qg * 4)) & 0x7;
if (idx < ACC100_NUM_ACCS) {
acc = qman_func_id[idx];
updateQtop(acc, qg, acc100_conf, d);
}
}
}
/* Check the depth of the AQs*/
reg_len0 = acc100_reg_read(d, reg_addr->depth_log0_offset);
reg_len1 = acc100_reg_read(d, reg_addr->depth_log1_offset);
for (acc = 0; acc < NUM_ACC; acc++) {
qtopFromAcc(&q_top, acc, acc100_conf);
if (q_top->first_qgroup_index < ACC100_NUM_QGRPS_PER_WORD)
q_top->aq_depth_log2 = (reg_len0 >>
(q_top->first_qgroup_index * 4))
& 0xF;
else
q_top->aq_depth_log2 = (reg_len1 >>
((q_top->first_qgroup_index -
ACC100_NUM_QGRPS_PER_WORD) * 4))
& 0xF;
}
/* Read PF mode */
if (d->pf_device) {
reg_mode = acc100_reg_read(d, HWPfHiPfMode);
acc100_conf->pf_mode_en = (reg_mode == ACC100_PF_VAL) ? 1 : 0;
}
rte_bbdev_log_debug(
"%s Config LLR SIGN IN/OUT %s %s QG %u %u %u %u AQ %u %u %u %u Len %u %u %u %u\n",
(d->pf_device) ? "PF" : "VF",
(acc100_conf->input_pos_llr_1_bit) ? "POS" : "NEG",
(acc100_conf->output_pos_llr_1_bit) ? "POS" : "NEG",
acc100_conf->q_ul_4g.num_qgroups,
acc100_conf->q_dl_4g.num_qgroups,
acc100_conf->q_ul_5g.num_qgroups,
acc100_conf->q_dl_5g.num_qgroups,
acc100_conf->q_ul_4g.num_aqs_per_groups,
acc100_conf->q_dl_4g.num_aqs_per_groups,
acc100_conf->q_ul_5g.num_aqs_per_groups,
acc100_conf->q_dl_5g.num_aqs_per_groups,
acc100_conf->q_ul_4g.aq_depth_log2,
acc100_conf->q_dl_4g.aq_depth_log2,
acc100_conf->q_ul_5g.aq_depth_log2,
acc100_conf->q_dl_5g.aq_depth_log2);
}
static void
free_base_addresses(void **base_addrs, int size)
{
int i;
for (i = 0; i < size; i++)
rte_free(base_addrs[i]);
}
static inline uint32_t
get_desc_len(void)
{
return sizeof(union acc100_dma_desc);
}
/* Allocate the 2 * 64MB block for the sw rings */
static int
alloc_2x64mb_sw_rings_mem(struct rte_bbdev *dev, struct acc100_device *d,
int socket)
{
uint32_t sw_ring_size = ACC100_SIZE_64MBYTE;
d->sw_rings_base = rte_zmalloc_socket(dev->device->driver->name,
2 * sw_ring_size, RTE_CACHE_LINE_SIZE, socket);
if (d->sw_rings_base == NULL) {
rte_bbdev_log(ERR, "Failed to allocate memory for %s:%u",
dev->device->driver->name,
dev->data->dev_id);
return -ENOMEM;
}
uint32_t next_64mb_align_offset = calc_mem_alignment_offset(
d->sw_rings_base, ACC100_SIZE_64MBYTE);
d->sw_rings = RTE_PTR_ADD(d->sw_rings_base, next_64mb_align_offset);
d->sw_rings_iova = rte_malloc_virt2iova(d->sw_rings_base) +
next_64mb_align_offset;
d->sw_ring_size = ACC100_MAX_QUEUE_DEPTH * get_desc_len();
d->sw_ring_max_depth = ACC100_MAX_QUEUE_DEPTH;
return 0;
}
/* Attempt to allocate minimised memory space for sw rings */
static void
alloc_sw_rings_min_mem(struct rte_bbdev *dev, struct acc100_device *d,
uint16_t num_queues, int socket)
{
rte_iova_t sw_rings_base_iova, next_64mb_align_addr_iova;
uint32_t next_64mb_align_offset;
rte_iova_t sw_ring_iova_end_addr;
void *base_addrs[ACC100_SW_RING_MEM_ALLOC_ATTEMPTS];
void *sw_rings_base;
int i = 0;
uint32_t q_sw_ring_size = ACC100_MAX_QUEUE_DEPTH * get_desc_len();
uint32_t dev_sw_ring_size = q_sw_ring_size * num_queues;
/* Find an aligned block of memory to store sw rings */
while (i < ACC100_SW_RING_MEM_ALLOC_ATTEMPTS) {
/*
* sw_ring allocated memory is guaranteed to be aligned to
* q_sw_ring_size at the condition that the requested size is
* less than the page size
*/
sw_rings_base = rte_zmalloc_socket(
dev->device->driver->name,
dev_sw_ring_size, q_sw_ring_size, socket);
if (sw_rings_base == NULL) {
rte_bbdev_log(ERR,
"Failed to allocate memory for %s:%u",
dev->device->driver->name,
dev->data->dev_id);
break;
}
sw_rings_base_iova = rte_malloc_virt2iova(sw_rings_base);
next_64mb_align_offset = calc_mem_alignment_offset(
sw_rings_base, ACC100_SIZE_64MBYTE);
next_64mb_align_addr_iova = sw_rings_base_iova +
next_64mb_align_offset;
sw_ring_iova_end_addr = sw_rings_base_iova + dev_sw_ring_size;
/* Check if the end of the sw ring memory block is before the
* start of next 64MB aligned mem address
*/
if (sw_ring_iova_end_addr < next_64mb_align_addr_iova) {
d->sw_rings_iova = sw_rings_base_iova;
d->sw_rings = sw_rings_base;
d->sw_rings_base = sw_rings_base;
d->sw_ring_size = q_sw_ring_size;
d->sw_ring_max_depth = ACC100_MAX_QUEUE_DEPTH;
break;
}
/* Store the address of the unaligned mem block */
base_addrs[i] = sw_rings_base;
i++;
}
/* Free all unaligned blocks of mem allocated in the loop */
free_base_addresses(base_addrs, i);
}
/*
* Find queue_id of a device queue based on details from the Info Ring.
* If a queue isn't found UINT16_MAX is returned.
*/
static inline uint16_t
get_queue_id_from_ring_info(struct rte_bbdev_data *data,
const union acc100_info_ring_data ring_data)
{
uint16_t queue_id;
for (queue_id = 0; queue_id < data->num_queues; ++queue_id) {
struct acc100_queue *acc100_q =
data->queues[queue_id].queue_private;
if (acc100_q != NULL && acc100_q->aq_id == ring_data.aq_id &&
acc100_q->qgrp_id == ring_data.qg_id &&
acc100_q->vf_id == ring_data.vf_id)
return queue_id;
}
return UINT16_MAX;
}
/* Checks PF Info Ring to find the interrupt cause and handles it accordingly */
static inline void
acc100_check_ir(struct acc100_device *acc100_dev)
{
volatile union acc100_info_ring_data *ring_data;
uint16_t info_ring_head = acc100_dev->info_ring_head;
if (acc100_dev->info_ring == NULL)
return;
ring_data = acc100_dev->info_ring + (acc100_dev->info_ring_head &
ACC100_INFO_RING_MASK);
while (ring_data->valid) {
if ((ring_data->int_nb < ACC100_PF_INT_DMA_DL_DESC_IRQ) || (
ring_data->int_nb >
ACC100_PF_INT_DMA_DL5G_DESC_IRQ))
rte_bbdev_log(WARNING, "InfoRing: ITR:%d Info:0x%x",
ring_data->int_nb, ring_data->detailed_info);
/* Initialize Info Ring entry and move forward */
ring_data->val = 0;
info_ring_head++;
ring_data = acc100_dev->info_ring +
(info_ring_head & ACC100_INFO_RING_MASK);
}
}
/* Checks PF Info Ring to find the interrupt cause and handles it accordingly */
static inline void
acc100_pf_interrupt_handler(struct rte_bbdev *dev)
{
struct acc100_device *acc100_dev = dev->data->dev_private;
volatile union acc100_info_ring_data *ring_data;
struct acc100_deq_intr_details deq_intr_det;
ring_data = acc100_dev->info_ring + (acc100_dev->info_ring_head &
ACC100_INFO_RING_MASK);
while (ring_data->valid) {
rte_bbdev_log_debug(
"ACC100 PF Interrupt received, Info Ring data: 0x%x",
ring_data->val);
switch (ring_data->int_nb) {
case ACC100_PF_INT_DMA_DL_DESC_IRQ:
case ACC100_PF_INT_DMA_UL_DESC_IRQ:
case ACC100_PF_INT_DMA_UL5G_DESC_IRQ:
case ACC100_PF_INT_DMA_DL5G_DESC_IRQ:
deq_intr_det.queue_id = get_queue_id_from_ring_info(
dev->data, *ring_data);
if (deq_intr_det.queue_id == UINT16_MAX) {
rte_bbdev_log(ERR,
"Couldn't find queue: aq_id: %u, qg_id: %u, vf_id: %u",
ring_data->aq_id,
ring_data->qg_id,
ring_data->vf_id);
return;
}
rte_bbdev_pmd_callback_process(dev,
RTE_BBDEV_EVENT_DEQUEUE, &deq_intr_det);
break;
default:
rte_bbdev_pmd_callback_process(dev,
RTE_BBDEV_EVENT_ERROR, NULL);
break;
}
/* Initialize Info Ring entry and move forward */
ring_data->val = 0;
++acc100_dev->info_ring_head;
ring_data = acc100_dev->info_ring +
(acc100_dev->info_ring_head &
ACC100_INFO_RING_MASK);
}
}
/* Checks VF Info Ring to find the interrupt cause and handles it accordingly */
static inline void
acc100_vf_interrupt_handler(struct rte_bbdev *dev)
{
struct acc100_device *acc100_dev = dev->data->dev_private;
volatile union acc100_info_ring_data *ring_data;
struct acc100_deq_intr_details deq_intr_det;
ring_data = acc100_dev->info_ring + (acc100_dev->info_ring_head &
ACC100_INFO_RING_MASK);
while (ring_data->valid) {
rte_bbdev_log_debug(
"ACC100 VF Interrupt received, Info Ring data: 0x%x",
ring_data->val);
switch (ring_data->int_nb) {
case ACC100_VF_INT_DMA_DL_DESC_IRQ:
case ACC100_VF_INT_DMA_UL_DESC_IRQ:
case ACC100_VF_INT_DMA_UL5G_DESC_IRQ:
case ACC100_VF_INT_DMA_DL5G_DESC_IRQ:
/* VFs are not aware of their vf_id - it's set to 0 in
* queue structures.
*/
ring_data->vf_id = 0;
deq_intr_det.queue_id = get_queue_id_from_ring_info(
dev->data, *ring_data);
if (deq_intr_det.queue_id == UINT16_MAX) {
rte_bbdev_log(ERR,
"Couldn't find queue: aq_id: %u, qg_id: %u",
ring_data->aq_id,
ring_data->qg_id);
return;
}
rte_bbdev_pmd_callback_process(dev,
RTE_BBDEV_EVENT_DEQUEUE, &deq_intr_det);
break;
default:
rte_bbdev_pmd_callback_process(dev,
RTE_BBDEV_EVENT_ERROR, NULL);
break;
}
/* Initialize Info Ring entry and move forward */
ring_data->valid = 0;
++acc100_dev->info_ring_head;
ring_data = acc100_dev->info_ring + (acc100_dev->info_ring_head
& ACC100_INFO_RING_MASK);
}
}
/* Interrupt handler triggered by ACC100 dev for handling specific interrupt */
static void
acc100_dev_interrupt_handler(void *cb_arg)
{
struct rte_bbdev *dev = cb_arg;
struct acc100_device *acc100_dev = dev->data->dev_private;
/* Read info ring */
if (acc100_dev->pf_device)
acc100_pf_interrupt_handler(dev);
else
acc100_vf_interrupt_handler(dev);
}
/* Allocate and setup inforing */
static int
allocate_info_ring(struct rte_bbdev *dev)
{
struct acc100_device *d = dev->data->dev_private;
const struct acc100_registry_addr *reg_addr;
rte_iova_t info_ring_iova;
uint32_t phys_low, phys_high;
if (d->info_ring != NULL)
return 0; /* Already configured */
/* Choose correct registry addresses for the device type */
if (d->pf_device)
reg_addr = &pf_reg_addr;
else
reg_addr = &vf_reg_addr;
/* Allocate InfoRing */
d->info_ring = rte_zmalloc_socket("Info Ring",
ACC100_INFO_RING_NUM_ENTRIES *
sizeof(*d->info_ring), RTE_CACHE_LINE_SIZE,
dev->data->socket_id);
if (d->info_ring == NULL) {
rte_bbdev_log(ERR,
"Failed to allocate Info Ring for %s:%u",
dev->device->driver->name,
dev->data->dev_id);
return -ENOMEM;
}
info_ring_iova = rte_malloc_virt2iova(d->info_ring);
/* Setup Info Ring */
phys_high = (uint32_t)(info_ring_iova >> 32);
phys_low = (uint32_t)(info_ring_iova);
acc100_reg_write(d, reg_addr->info_ring_hi, phys_high);
acc100_reg_write(d, reg_addr->info_ring_lo, phys_low);
acc100_reg_write(d, reg_addr->info_ring_en, ACC100_REG_IRQ_EN_ALL);
d->info_ring_head = (acc100_reg_read(d, reg_addr->info_ring_ptr) &
0xFFF) / sizeof(union acc100_info_ring_data);
return 0;
}
/* Allocate 64MB memory used for all software rings */
static int
acc100_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id)
{
uint32_t phys_low, phys_high, value;
struct acc100_device *d = dev->data->dev_private;
const struct acc100_registry_addr *reg_addr;
int ret;
if (d->pf_device && !d->acc100_conf.pf_mode_en) {
rte_bbdev_log(NOTICE,
"%s has PF mode disabled. This PF can't be used.",
dev->data->name);
return -ENODEV;
}
alloc_sw_rings_min_mem(dev, d, num_queues, socket_id);
/* If minimal memory space approach failed, then allocate
* the 2 * 64MB block for the sw rings
*/
if (d->sw_rings == NULL)
alloc_2x64mb_sw_rings_mem(dev, d, socket_id);
if (d->sw_rings == NULL) {
rte_bbdev_log(NOTICE,
"Failure allocating sw_rings memory");
return -ENODEV;
}
/* Configure ACC100 with the base address for DMA descriptor rings
* Same descriptor rings used for UL and DL DMA Engines
* Note : Assuming only VF0 bundle is used for PF mode
*/
phys_high = (uint32_t)(d->sw_rings_iova >> 32);
phys_low = (uint32_t)(d->sw_rings_iova & ~(ACC100_SIZE_64MBYTE-1));
/* Choose correct registry addresses for the device type */
if (d->pf_device)
reg_addr = &pf_reg_addr;
else
reg_addr = &vf_reg_addr;
/* Read the populated cfg from ACC100 registers */
fetch_acc100_config(dev);
/* Release AXI from PF */
if (d->pf_device)
acc100_reg_write(d, HWPfDmaAxiControl, 1);
acc100_reg_write(d, reg_addr->dma_ring_ul5g_hi, phys_high);
acc100_reg_write(d, reg_addr->dma_ring_ul5g_lo, phys_low);
acc100_reg_write(d, reg_addr->dma_ring_dl5g_hi, phys_high);
acc100_reg_write(d, reg_addr->dma_ring_dl5g_lo, phys_low);
acc100_reg_write(d, reg_addr->dma_ring_ul4g_hi, phys_high);
acc100_reg_write(d, reg_addr->dma_ring_ul4g_lo, phys_low);
acc100_reg_write(d, reg_addr->dma_ring_dl4g_hi, phys_high);
acc100_reg_write(d, reg_addr->dma_ring_dl4g_lo, phys_low);
/*
* Configure Ring Size to the max queue ring size
* (used for wrapping purpose)
*/
value = log2_basic(d->sw_ring_size / 64);
acc100_reg_write(d, reg_addr->ring_size, value);
/* Configure tail pointer for use when SDONE enabled */
d->tail_ptrs = rte_zmalloc_socket(
dev->device->driver->name,
ACC100_NUM_QGRPS * ACC100_NUM_AQS * sizeof(uint32_t),
RTE_CACHE_LINE_SIZE, socket_id);
if (d->tail_ptrs == NULL) {
rte_bbdev_log(ERR, "Failed to allocate tail ptr for %s:%u",
dev->device->driver->name,
dev->data->dev_id);
rte_free(d->sw_rings);
return -ENOMEM;
}
d->tail_ptr_iova = rte_malloc_virt2iova(d->tail_ptrs);
phys_high = (uint32_t)(d->tail_ptr_iova >> 32);
phys_low = (uint32_t)(d->tail_ptr_iova);
acc100_reg_write(d, reg_addr->tail_ptrs_ul5g_hi, phys_high);
acc100_reg_write(d, reg_addr->tail_ptrs_ul5g_lo, phys_low);
acc100_reg_write(d, reg_addr->tail_ptrs_dl5g_hi, phys_high);
acc100_reg_write(d, reg_addr->tail_ptrs_dl5g_lo, phys_low);
acc100_reg_write(d, reg_addr->tail_ptrs_ul4g_hi, phys_high);
acc100_reg_write(d, reg_addr->tail_ptrs_ul4g_lo, phys_low);
acc100_reg_write(d, reg_addr->tail_ptrs_dl4g_hi, phys_high);
acc100_reg_write(d, reg_addr->tail_ptrs_dl4g_lo, phys_low);
ret = allocate_info_ring(dev);
if (ret < 0) {
rte_bbdev_log(ERR, "Failed to allocate info_ring for %s:%u",
dev->device->driver->name,
dev->data->dev_id);
/* Continue */
}
d->harq_layout = rte_zmalloc_socket("HARQ Layout",
ACC100_HARQ_LAYOUT * sizeof(*d->harq_layout),
RTE_CACHE_LINE_SIZE, dev->data->socket_id);
if (d->harq_layout == NULL) {
rte_bbdev_log(ERR, "Failed to allocate harq_layout for %s:%u",
dev->device->driver->name,
dev->data->dev_id);
rte_free(d->sw_rings);
return -ENOMEM;
}
/* Mark as configured properly */
d->configured = true;
rte_bbdev_log_debug(
"ACC100 (%s) configured sw_rings = %p, sw_rings_iova = %#"
PRIx64, dev->data->name, d->sw_rings, d->sw_rings_iova);
return 0;
}
static int
acc100_intr_enable(struct rte_bbdev *dev)
{
int ret;
struct acc100_device *d = dev->data->dev_private;
/* Only MSI are currently supported */
if (dev->intr_handle->type == RTE_INTR_HANDLE_VFIO_MSI ||
dev->intr_handle->type == RTE_INTR_HANDLE_UIO) {
ret = allocate_info_ring(dev);
if (ret < 0) {
rte_bbdev_log(ERR,
"Couldn't allocate info ring for device: %s",
dev->data->name);
return ret;
}
ret = rte_intr_enable(dev->intr_handle);
if (ret < 0) {
rte_bbdev_log(ERR,
"Couldn't enable interrupts for device: %s",
dev->data->name);
rte_free(d->info_ring);
return ret;
}
ret = rte_intr_callback_register(dev->intr_handle,
acc100_dev_interrupt_handler, dev);
if (ret < 0) {
rte_bbdev_log(ERR,
"Couldn't register interrupt callback for device: %s",
dev->data->name);
rte_free(d->info_ring);
return ret;
}
return 0;
}
rte_bbdev_log(ERR, "ACC100 (%s) supports only VFIO MSI interrupts",
dev->data->name);
return -ENOTSUP;
}
/* Free memory used for software rings */
static int
acc100_dev_close(struct rte_bbdev *dev)
{
struct acc100_device *d = dev->data->dev_private;
acc100_check_ir(d);
if (d->sw_rings_base != NULL) {
rte_free(d->tail_ptrs);
rte_free(d->info_ring);
rte_free(d->sw_rings_base);
d->sw_rings_base = NULL;
}
/* Ensure all in flight HW transactions are completed */
usleep(ACC100_LONG_WAIT);
return 0;
}
/**
* Report a ACC100 queue index which is free
* Return 0 to 16k for a valid queue_idx or -1 when no queue is available
* Note : Only supporting VF0 Bundle for PF mode
*/
static int
acc100_find_free_queue_idx(struct rte_bbdev *dev,
const struct rte_bbdev_queue_conf *conf)
{
struct acc100_device *d = dev->data->dev_private;
int op_2_acc[5] = {0, UL_4G, DL_4G, UL_5G, DL_5G};
int acc = op_2_acc[conf->op_type];
struct rte_acc100_queue_topology *qtop = NULL;
qtopFromAcc(&qtop, acc, &(d->acc100_conf));
if (qtop == NULL)
return -1;
/* Identify matching QGroup Index which are sorted in priority order */
uint16_t group_idx = qtop->first_qgroup_index;
group_idx += conf->priority;
if (group_idx >= ACC100_NUM_QGRPS ||
conf->priority >= qtop->num_qgroups) {
rte_bbdev_log(INFO, "Invalid Priority on %s, priority %u",
dev->data->name, conf->priority);
return -1;
}
/* Find a free AQ_idx */
uint16_t aq_idx;
for (aq_idx = 0; aq_idx < qtop->num_aqs_per_groups; aq_idx++) {
if (((d->q_assigned_bit_map[group_idx] >> aq_idx) & 0x1) == 0) {
/* Mark the Queue as assigned */
d->q_assigned_bit_map[group_idx] |= (1 << aq_idx);
/* Report the AQ Index */
return (group_idx << ACC100_GRP_ID_SHIFT) + aq_idx;
}
}
rte_bbdev_log(INFO, "Failed to find free queue on %s, priority %u",
dev->data->name, conf->priority);
return -1;
}
/* Setup ACC100 queue */
static int
acc100_queue_setup(struct rte_bbdev *dev, uint16_t queue_id,
const struct rte_bbdev_queue_conf *conf)
{
struct acc100_device *d = dev->data->dev_private;
struct acc100_queue *q;
int16_t q_idx;
/* Allocate the queue data structure. */
q = rte_zmalloc_socket(dev->device->driver->name, sizeof(*q),
RTE_CACHE_LINE_SIZE, conf->socket);
if (q == NULL) {
rte_bbdev_log(ERR, "Failed to allocate queue memory");
return -ENOMEM;
}
if (d == NULL) {
rte_bbdev_log(ERR, "Undefined device");
return -ENODEV;
}
q->d = d;
q->ring_addr = RTE_PTR_ADD(d->sw_rings, (d->sw_ring_size * queue_id));
q->ring_addr_iova = d->sw_rings_iova + (d->sw_ring_size * queue_id);
/* Prepare the Ring with default descriptor format */
union acc100_dma_desc *desc = NULL;
unsigned int desc_idx, b_idx;
int fcw_len = (conf->op_type == RTE_BBDEV_OP_LDPC_ENC ?
ACC100_FCW_LE_BLEN : (conf->op_type == RTE_BBDEV_OP_TURBO_DEC ?
ACC100_FCW_TD_BLEN : ACC100_FCW_LD_BLEN));
for (desc_idx = 0; desc_idx < d->sw_ring_max_depth; desc_idx++) {
desc = q->ring_addr + desc_idx;
desc->req.word0 = ACC100_DMA_DESC_TYPE;
desc->req.word1 = 0; /**< Timestamp */
desc->req.word2 = 0;
desc->req.word3 = 0;
uint64_t fcw_offset = (desc_idx << 8) + ACC100_DESC_FCW_OFFSET;
desc->req.data_ptrs[0].address = q->ring_addr_iova + fcw_offset;
desc->req.data_ptrs[0].blen = fcw_len;
desc->req.data_ptrs[0].blkid = ACC100_DMA_BLKID_FCW;
desc->req.data_ptrs[0].last = 0;
desc->req.data_ptrs[0].dma_ext = 0;
for (b_idx = 1; b_idx < ACC100_DMA_MAX_NUM_POINTERS - 1;
b_idx++) {
desc->req.data_ptrs[b_idx].blkid = ACC100_DMA_BLKID_IN;
desc->req.data_ptrs[b_idx].last = 1;
desc->req.data_ptrs[b_idx].dma_ext = 0;
b_idx++;
desc->req.data_ptrs[b_idx].blkid =
ACC100_DMA_BLKID_OUT_ENC;
desc->req.data_ptrs[b_idx].last = 1;
desc->req.data_ptrs[b_idx].dma_ext = 0;
}
/* Preset some fields of LDPC FCW */
desc->req.fcw_ld.FCWversion = ACC100_FCW_VER;
desc->req.fcw_ld.gain_i = 1;
desc->req.fcw_ld.gain_h = 1;
}
q->lb_in = rte_zmalloc_socket(dev->device->driver->name,
RTE_CACHE_LINE_SIZE,
RTE_CACHE_LINE_SIZE, conf->socket);
if (q->lb_in == NULL) {
rte_bbdev_log(ERR, "Failed to allocate lb_in memory");
rte_free(q);
return -ENOMEM;
}
q->lb_in_addr_iova = rte_malloc_virt2iova(q->lb_in);
q->lb_out = rte_zmalloc_socket(dev->device->driver->name,
RTE_CACHE_LINE_SIZE,
RTE_CACHE_LINE_SIZE, conf->socket);
if (q->lb_out == NULL) {
rte_bbdev_log(ERR, "Failed to allocate lb_out memory");
rte_free(q->lb_in);
rte_free(q);
return -ENOMEM;
}
q->lb_out_addr_iova = rte_malloc_virt2iova(q->lb_out);
/*
* Software queue ring wraps synchronously with the HW when it reaches
* the boundary of the maximum allocated queue size, no matter what the
* sw queue size is. This wrapping is guarded by setting the wrap_mask
* to represent the maximum queue size as allocated at the time when
* the device has been setup (in configure()).
*
* The queue depth is set to the queue size value (conf->queue_size).
* This limits the occupancy of the queue at any point of time, so that
* the queue does not get swamped with enqueue requests.
*/
q->sw_ring_depth = conf->queue_size;
q->sw_ring_wrap_mask = d->sw_ring_max_depth - 1;
q->op_type = conf->op_type;
q_idx = acc100_find_free_queue_idx(dev, conf);
if (q_idx == -1) {
rte_free(q->lb_in);
rte_free(q->lb_out);
rte_free(q);
return -1;
}
q->qgrp_id = (q_idx >> ACC100_GRP_ID_SHIFT) & 0xF;
q->vf_id = (q_idx >> ACC100_VF_ID_SHIFT) & 0x3F;
q->aq_id = q_idx & 0xF;
q->aq_depth = (conf->op_type == RTE_BBDEV_OP_TURBO_DEC) ?
(1 << d->acc100_conf.q_ul_4g.aq_depth_log2) :
(1 << d->acc100_conf.q_dl_4g.aq_depth_log2);
q->mmio_reg_enqueue = RTE_PTR_ADD(d->mmio_base,
queue_offset(d->pf_device,
q->vf_id, q->qgrp_id, q->aq_id));
rte_bbdev_log_debug(
"Setup dev%u q%u: qgrp_id=%u, vf_id=%u, aq_id=%u, aq_depth=%u, mmio_reg_enqueue=%p",
dev->data->dev_id, queue_id, q->qgrp_id, q->vf_id,
q->aq_id, q->aq_depth, q->mmio_reg_enqueue);
dev->data->queues[queue_id].queue_private = q;
return 0;
}
/* Release ACC100 queue */
static int
acc100_queue_release(struct rte_bbdev *dev, uint16_t q_id)
{
struct acc100_device *d = dev->data->dev_private;
struct acc100_queue *q = dev->data->queues[q_id].queue_private;
if (q != NULL) {
/* Mark the Queue as un-assigned */
d->q_assigned_bit_map[q->qgrp_id] &= (0xFFFFFFFF -
(1 << q->aq_id));
rte_free(q->lb_in);
rte_free(q->lb_out);
rte_free(q);
dev->data->queues[q_id].queue_private = NULL;
}
return 0;
}
/* Get ACC100 device info */
static void
acc100_dev_info_get(struct rte_bbdev *dev,
struct rte_bbdev_driver_info *dev_info)
{
struct acc100_device *d = dev->data->dev_private;
static const struct rte_bbdev_op_cap bbdev_capabilities[] = {
{
.type = RTE_BBDEV_OP_TURBO_DEC,
.cap.turbo_dec = {
.capability_flags =
RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE |
RTE_BBDEV_TURBO_CRC_TYPE_24B |
RTE_BBDEV_TURBO_HALF_ITERATION_EVEN |
RTE_BBDEV_TURBO_EARLY_TERMINATION |
RTE_BBDEV_TURBO_DEC_INTERRUPTS |
RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN |
RTE_BBDEV_TURBO_MAP_DEC |
RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP |
RTE_BBDEV_TURBO_DEC_SCATTER_GATHER,
.max_llr_modulus = INT8_MAX,
.num_buffers_src =
RTE_BBDEV_TURBO_MAX_CODE_BLOCKS,
.num_buffers_hard_out =
RTE_BBDEV_TURBO_MAX_CODE_BLOCKS,
.num_buffers_soft_out =
RTE_BBDEV_TURBO_MAX_CODE_BLOCKS,
}
},
{
.type = RTE_BBDEV_OP_TURBO_ENC,
.cap.turbo_enc = {
.capability_flags =
RTE_BBDEV_TURBO_CRC_24B_ATTACH |
RTE_BBDEV_TURBO_RV_INDEX_BYPASS |
RTE_BBDEV_TURBO_RATE_MATCH |
RTE_BBDEV_TURBO_ENC_INTERRUPTS |