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tc-riscv.c
5618 lines (4917 loc) · 158 KB
/
tc-riscv.c
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/* tc-riscv.c -- RISC-V assembler
Copyright (C) 2011-2024 Free Software Foundation, Inc.
Contributed by Andrew Waterman (andrew@sifive.com).
Based on MIPS target.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
#include "as.h"
#include "config.h"
#include "subsegs.h"
#include "safe-ctype.h"
#include "itbl-ops.h"
#include "dwarf2dbg.h"
#include "dw2gencfi.h"
#include "bfd/elfxx-riscv.h"
#include "elf/riscv.h"
#include "opcode/riscv.h"
#include <stdint.h>
/* Information about an instruction, including its format, operands
and fixups. */
struct riscv_cl_insn
{
/* The opcode's entry in riscv_opcodes. */
const struct riscv_opcode *insn_mo;
/* The encoded instruction bits
(first bits enough to extract instruction length on a long opcode). */
insn_t insn_opcode;
/* The long encoded instruction bits ([0] is non-zero on a long opcode). */
char insn_long_opcode[RISCV_MAX_INSN_LEN];
/* The frag that contains the instruction. */
struct frag *frag;
/* The offset into FRAG of the first instruction byte. */
long where;
/* The relocs associated with the instruction, if any. */
fixS *fixp;
};
/* The identifier of the assembler macro we are expanding, if any. */
static int source_macro = -1;
/* All RISC-V CSR belong to one of these classes. */
enum riscv_csr_class
{
CSR_CLASS_NONE,
CSR_CLASS_I,
CSR_CLASS_I_32, /* rv32 only */
CSR_CLASS_F, /* f-ext only */
CSR_CLASS_ZKR, /* zkr only */
CSR_CLASS_V, /* rvv only */
CSR_CLASS_DEBUG, /* debug CSR */
CSR_CLASS_H, /* hypervisor */
CSR_CLASS_H_32, /* hypervisor, rv32 only */
CSR_CLASS_SMAIA, /* Smaia */
CSR_CLASS_SMAIA_32, /* Smaia, rv32 only */
CSR_CLASS_SMCNTRPMF, /* Smcntrpmf */
CSR_CLASS_SMCNTRPMF_32, /* Smcntrpmf, rv32 only */
CSR_CLASS_SMSTATEEN, /* Smstateen only */
CSR_CLASS_SMSTATEEN_32, /* Smstateen RV32 only */
CSR_CLASS_SSAIA, /* Ssaia */
CSR_CLASS_SSAIA_AND_H, /* Ssaia with H */
CSR_CLASS_SSAIA_32, /* Ssaia, rv32 only */
CSR_CLASS_SSAIA_AND_H_32, /* Ssaia with H, rv32 only */
CSR_CLASS_SSSTATEEN, /* S[ms]stateen only */
CSR_CLASS_SSSTATEEN_AND_H, /* S[ms]stateen only (with H) */
CSR_CLASS_SSSTATEEN_AND_H_32, /* S[ms]stateen RV32 only (with H) */
CSR_CLASS_SSCOFPMF, /* Sscofpmf only */
CSR_CLASS_SSCOFPMF_32, /* Sscofpmf RV32 only */
CSR_CLASS_SSTC, /* Sstc only */
CSR_CLASS_SSTC_AND_H, /* Sstc only (with H) */
CSR_CLASS_SSTC_32, /* Sstc RV32 only */
CSR_CLASS_SSTC_AND_H_32, /* Sstc RV32 only (with H) */
CSR_CLASS_XTHEADVECTOR, /* xtheadvector only */
};
/* This structure holds all restricted conditions for a CSR. */
struct riscv_csr_extra
{
/* Class to which this CSR belongs. Used to decide whether or
not this CSR is legal in the current -march context. */
enum riscv_csr_class csr_class;
/* CSR may have differnet numbers in the previous priv spec. */
unsigned address;
/* Record the CSR is defined/valid in which versions. */
enum riscv_spec_class define_version;
/* Record the CSR is aborted/invalid from which versions. If it isn't
aborted in the current version, then it should be PRIV_SPEC_CLASS_DRAFT. */
enum riscv_spec_class abort_version;
/* The CSR may have more than one setting. */
struct riscv_csr_extra *next;
};
/* This structure contains information about errors that occur within the
riscv_ip function */
struct riscv_ip_error
{
/* General error message */
const char* msg;
/* Statement that caused the error */
char* statement;
/* Missing extension that needs to be enabled */
const char* missing_ext;
};
#ifndef DEFAULT_ARCH
#define DEFAULT_ARCH "riscv64"
#endif
#ifndef DEFAULT_RISCV_ATTR
#define DEFAULT_RISCV_ATTR 0
#endif
/* Let riscv_after_parse_args set the default value according to xlen. */
#ifndef DEFAULT_RISCV_ARCH_WITH_EXT
#define DEFAULT_RISCV_ARCH_WITH_EXT NULL
#endif
/* Need to sync the version with RISC-V compiler. */
#ifndef DEFAULT_RISCV_ISA_SPEC
#define DEFAULT_RISCV_ISA_SPEC "20191213"
#endif
#ifndef DEFAULT_RISCV_PRIV_SPEC
#define DEFAULT_RISCV_PRIV_SPEC "1.11"
#endif
static const char default_arch[] = DEFAULT_ARCH;
static const char *default_arch_with_ext = DEFAULT_RISCV_ARCH_WITH_EXT;
static enum riscv_spec_class default_isa_spec = ISA_SPEC_CLASS_NONE;
static enum riscv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
static unsigned xlen = 0; /* The width of an x-register. */
static unsigned abi_xlen = 0; /* The width of a pointer in the ABI. */
static bool rve_abi = false;
enum float_abi
{
FLOAT_ABI_DEFAULT = -1,
FLOAT_ABI_SOFT,
FLOAT_ABI_SINGLE,
FLOAT_ABI_DOUBLE,
FLOAT_ABI_QUAD
};
static enum float_abi float_abi = FLOAT_ABI_DEFAULT;
#define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw")
#define ADD32_INSN (xlen == 64 ? "addiw" : "addi")
static unsigned elf_flags = 0;
static bool probing_insn_operands;
/* Set the default_isa_spec. Return 0 if the spec isn't supported.
Otherwise, return 1. */
static int
riscv_set_default_isa_spec (const char *s)
{
enum riscv_spec_class class = ISA_SPEC_CLASS_NONE;
RISCV_GET_ISA_SPEC_CLASS (s, class);
if (class == ISA_SPEC_CLASS_NONE)
{
as_bad ("unknown default ISA spec `%s' set by "
"-misa-spec or --with-isa-spec", s);
return 0;
}
else
default_isa_spec = class;
return 1;
}
/* Set the default_priv_spec. Find the privileged elf attributes when
the input string is NULL. Return 0 if the spec isn't supported.
Otherwise, return 1. */
static int
riscv_set_default_priv_spec (const char *s)
{
enum riscv_spec_class class = PRIV_SPEC_CLASS_NONE;
unsigned major, minor, revision;
obj_attribute *attr;
RISCV_GET_PRIV_SPEC_CLASS (s, class);
if (class != PRIV_SPEC_CLASS_NONE
&& class != PRIV_SPEC_CLASS_1P9P1)
{
default_priv_spec = class;
return 1;
}
if (s != NULL)
{
as_bad (_("unknown default privileged spec `%s' set by "
"-mpriv-spec or --with-priv-spec"), s);
return 0;
}
/* Set the default_priv_spec by the privileged elf attributes. */
attr = elf_known_obj_attributes_proc (stdoutput);
major = (unsigned) attr[Tag_RISCV_priv_spec].i;
minor = (unsigned) attr[Tag_RISCV_priv_spec_minor].i;
revision = (unsigned) attr[Tag_RISCV_priv_spec_revision].i;
/* Version 0.0.0 is the default value and meningless. */
if (major == 0 && minor == 0 && revision == 0)
return 1;
riscv_get_priv_spec_class_from_numbers (major, minor, revision, &class);
if (class != PRIV_SPEC_CLASS_NONE)
{
default_priv_spec = class;
return 1;
}
/* Still can not find the privileged spec class. */
as_bad (_("unknown default privileged spec `%d.%d.%d' set by "
"privileged elf attributes"), major, minor, revision);
return 0;
}
/* This is the set of options which the .option pseudo-op may modify. */
struct riscv_set_options
{
int pic; /* Generate position-independent code. */
int rvc; /* Generate RVC code. */
int relax; /* Emit relocs the linker is allowed to relax. */
int arch_attr; /* Emit architecture and privileged elf attributes. */
int csr_check; /* Enable the CSR checking. */
};
static struct riscv_set_options riscv_opts =
{
0, /* pic */
0, /* rvc */
1, /* relax */
DEFAULT_RISCV_ATTR, /* arch_attr */
0, /* csr_check */
};
/* Enable or disable the rvc flags for riscv_opts. Turn on the rvc flag
for elf_flags once we have enabled c extension. */
static void
riscv_set_rvc (bool rvc_value)
{
if (rvc_value)
elf_flags |= EF_RISCV_RVC;
riscv_opts.rvc = rvc_value;
}
/* Turn on the tso flag for elf_flags once we have enabled ztso extension. */
static void
riscv_set_tso (void)
{
elf_flags |= EF_RISCV_TSO;
}
/* The linked list hanging off of .subsets_list records all enabled extensions,
which are parsed from the architecture string. The architecture string can
be set by the -march option, the elf architecture attributes, and the
--with-arch configure option. */
static riscv_parse_subset_t riscv_rps_as =
{
NULL, /* subset_list, we will set it later once
riscv_opts_stack is created or updated. */
as_bad, /* error_handler. */
&xlen, /* xlen. */
&default_isa_spec, /* isa_spec. */
true, /* check_unknown_prefixed_ext. */
};
/* Update the architecture string in the subset_list. */
static void
riscv_reset_subsets_list_arch_str (void)
{
riscv_subset_list_t *subsets = riscv_rps_as.subset_list;
if (subsets->arch_str != NULL)
free ((void *) subsets->arch_str);
subsets->arch_str = riscv_arch_str (xlen, subsets);
}
/* This structure is used to hold a stack of .option values. */
struct riscv_option_stack
{
struct riscv_option_stack *next;
struct riscv_set_options options;
riscv_subset_list_t *subset_list;
};
static struct riscv_option_stack *riscv_opts_stack = NULL;
/* Set which ISA and extensions are available. */
static void
riscv_set_arch (const char *s)
{
if (s != NULL && strcmp (s, "") == 0)
{
as_bad (_("the architecture string of -march and elf architecture "
"attributes cannot be empty"));
return;
}
if (riscv_rps_as.subset_list == NULL)
{
riscv_rps_as.subset_list = XNEW (riscv_subset_list_t);
riscv_rps_as.subset_list->head = NULL;
riscv_rps_as.subset_list->tail = NULL;
riscv_rps_as.subset_list->arch_str = NULL;
}
riscv_release_subset_list (riscv_rps_as.subset_list);
riscv_parse_subset (&riscv_rps_as, s);
riscv_reset_subsets_list_arch_str ();
riscv_set_rvc (false);
if (riscv_subset_supports (&riscv_rps_as, "c")
|| riscv_subset_supports (&riscv_rps_as, "zca"))
riscv_set_rvc (true);
if (riscv_subset_supports (&riscv_rps_as, "ztso"))
riscv_set_tso ();
}
/* Indicate -mabi option is explictly set. */
static bool explicit_mabi = false;
/* Set the abi information. */
static void
riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bool rve)
{
abi_xlen = new_xlen;
float_abi = new_float_abi;
rve_abi = rve;
}
/* If the -mabi option isn't set, then set the abi according to the
ISA string. Otherwise, check if there is any conflict. */
static void
riscv_set_abi_by_arch (void)
{
if (!explicit_mabi)
{
if (riscv_subset_supports (&riscv_rps_as, "q"))
riscv_set_abi (xlen, FLOAT_ABI_QUAD, false);
else if (riscv_subset_supports (&riscv_rps_as, "d"))
riscv_set_abi (xlen, FLOAT_ABI_DOUBLE, false);
else if (riscv_subset_supports (&riscv_rps_as, "e"))
riscv_set_abi (xlen, FLOAT_ABI_SOFT, true);
else
riscv_set_abi (xlen, FLOAT_ABI_SOFT, false);
}
else
{
gas_assert (abi_xlen != 0 && xlen != 0 && float_abi != FLOAT_ABI_DEFAULT);
if (abi_xlen > xlen)
as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen, xlen);
else if (abi_xlen < xlen)
as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen);
if (riscv_subset_supports (&riscv_rps_as, "e") && !rve_abi)
as_bad ("only ilp32e/lp64e ABI are supported for e extension");
if (float_abi == FLOAT_ABI_SINGLE
&& !riscv_subset_supports (&riscv_rps_as, "f"))
as_bad ("ilp32f/lp64f ABI can't be used when f extension "
"isn't supported");
else if (float_abi == FLOAT_ABI_DOUBLE
&& !riscv_subset_supports (&riscv_rps_as, "d"))
as_bad ("ilp32d/lp64d ABI can't be used when d extension "
"isn't supported");
else if (float_abi == FLOAT_ABI_QUAD
&& !riscv_subset_supports (&riscv_rps_as, "q"))
as_bad ("ilp32q/lp64q ABI can't be used when q extension "
"isn't supported");
}
/* Update the EF_RISCV_FLOAT_ABI field of elf_flags. */
elf_flags &= ~EF_RISCV_FLOAT_ABI;
elf_flags |= float_abi << 1;
if (rve_abi)
elf_flags |= EF_RISCV_RVE;
}
/* Handle of the OPCODE hash table. */
static htab_t op_hash = NULL;
/* Handle of the type of .insn hash table. */
static htab_t insn_type_hash = NULL;
/* This array holds the chars that always start a comment. If the
pre-processor is disabled, these aren't very useful. */
const char comment_chars[] = "#";
/* This array holds the chars that only start a comment at the beginning of
a line. If the line seems to have the form '# 123 filename'
.line and .file directives will appear in the pre-processed output
Note that input_file.c hand checks for '#' at the beginning of the
first line of the input file. This is because the compiler outputs
#NO_APP at the beginning of its output.
Also note that C style comments are always supported. */
const char line_comment_chars[] = "#";
/* This array holds machine specific line separator characters. */
const char line_separator_chars[] = ";";
/* Chars that can be used to separate mant from exp in floating point nums. */
const char EXP_CHARS[] = "eE";
/* Chars that mean this number is a floating point constant.
As in 0f12.456 or 0d1.2345e12. */
const char FLT_CHARS[] = "rRsSfFdDxXpPhH";
/* Indicate we are already assemble any instructions or not. */
static bool start_assemble = false;
/* Indicate ELF attributes are explicitly set. */
static bool explicit_attr = false;
/* Indicate CSR or priv instructions are explicitly used. */
static bool explicit_priv_attr = false;
static char *expr_parse_end;
/* Macros for encoding relaxation state for RVC branches and far jumps. */
#define RELAX_BRANCH_ENCODE(uncond, rvc, length) \
((relax_substateT) \
(0xc0000000 \
| ((uncond) ? 1 : 0) \
| ((rvc) ? 2 : 0) \
| ((length) << 2)))
#define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000)
#define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF)
#define RELAX_BRANCH_RVC(i) (((i) & 2) != 0)
#define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0)
/* Is the given value a sign-extended 32-bit value? */
#define IS_SEXT_32BIT_NUM(x) \
(((x) &~ (offsetT) 0x7fffffff) == 0 \
|| (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
/* Is the given value a zero-extended 32-bit value? Or a negated one? */
#define IS_ZEXT_32BIT_NUM(x) \
(((x) &~ (offsetT) 0xffffffff) == 0 \
|| (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
/* Change INSN's opcode so that the operand given by FIELD has value VALUE.
INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */
#define INSERT_OPERAND(FIELD, INSN, VALUE) \
INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
#define INSERT_IMM(n, s, INSN, VALUE) \
INSERT_BITS ((INSN).insn_opcode, VALUE, (1ULL<<n) - 1, s)
/* Determine if an instruction matches an opcode. */
#define OPCODE_MATCHES(OPCODE, OP) \
(((OPCODE) & MASK_##OP) == MATCH_##OP)
/* Create a new mapping symbol for the transition to STATE. */
static void
make_mapping_symbol (enum riscv_seg_mstate state,
valueT value,
fragS *frag,
const char *arch_str,
bool odd_data_padding)
{
const char *name;
char *buff = NULL;
switch (state)
{
case MAP_DATA:
name = "$d";
break;
case MAP_INSN:
if (arch_str != NULL)
{
size_t size = strlen (arch_str) + 3; /* "$x" + '\0' */
buff = xmalloc (size);
snprintf (buff, size, "$x%s", arch_str);
name = buff;
}
else
name = "$x";
break;
default:
abort ();
}
symbolS *symbol = symbol_new (name, now_seg, frag, value);
symbol_get_bfdsym (symbol)->flags |= (BSF_NO_FLAGS | BSF_LOCAL);
if (arch_str != NULL)
{
/* Store current $x+arch into tc_segment_info. */
seg_info (now_seg)->tc_segment_info_data.arch_map_symbol = symbol;
xfree ((void *) buff);
}
/* If .fill or other data filling directive generates zero sized data,
then mapping symbol for the following code will have the same value.
Please see gas/testsuite/gas/riscv/mapping.s: .text.zero.fill.first
and .text.zero.fill.last. */
symbolS *first = frag->tc_frag_data.first_map_symbol;
symbolS *last = frag->tc_frag_data.last_map_symbol;
symbolS *removed = NULL;
if (value == 0)
{
if (first != NULL)
{
know (S_GET_VALUE (first) == S_GET_VALUE (symbol)
&& first == last);
/* Remove the old one. */
removed = first;
}
frag->tc_frag_data.first_map_symbol = symbol;
}
else if (last != NULL)
{
/* The mapping symbols should be added in offset order. */
know (S_GET_VALUE (last) <= S_GET_VALUE (symbol));
/* Remove the old one. */
if (S_GET_VALUE (last) == S_GET_VALUE (symbol))
removed = last;
}
frag->tc_frag_data.last_map_symbol = symbol;
if (removed == NULL)
return;
if (odd_data_padding)
{
/* If the removed mapping symbol is $x+arch, then add it back to
the next $x. */
const char *str = strncmp (S_GET_NAME (removed), "$xrv", 4) == 0
? S_GET_NAME (removed) + 2 : NULL;
make_mapping_symbol (MAP_INSN, frag->fr_fix + 1, frag, str,
false/* odd_data_padding */);
}
symbol_remove (removed, &symbol_rootP, &symbol_lastP);
}
/* Set the mapping state for frag_now. */
void
riscv_mapping_state (enum riscv_seg_mstate to_state,
int max_chars,
bool fr_align_code)
{
enum riscv_seg_mstate from_state =
seg_info (now_seg)->tc_segment_info_data.map_state;
bool reset_seg_arch_str = false;
if (!SEG_NORMAL (now_seg)
/* For now we only add the mapping symbols to text sections.
Therefore, the dis-assembler only show the actual contents
distribution for text. Other sections will be shown as
data without the details. */
|| !subseg_text_p (now_seg))
return;
/* The mapping symbol should be emitted if not in the right
mapping state. */
symbolS *seg_arch_symbol =
seg_info (now_seg)->tc_segment_info_data.arch_map_symbol;
if (to_state == MAP_INSN && seg_arch_symbol == 0)
{
/* Always add $x+arch at the first instruction of section. */
reset_seg_arch_str = true;
}
else if (seg_arch_symbol != 0
&& to_state == MAP_INSN
&& !fr_align_code
&& strcmp (riscv_rps_as.subset_list->arch_str,
S_GET_NAME (seg_arch_symbol) + 2) != 0)
{
reset_seg_arch_str = true;
}
else if (from_state == to_state)
return;
valueT value = (valueT) (frag_now_fix () - max_chars);
seg_info (now_seg)->tc_segment_info_data.map_state = to_state;
const char *arch_str = reset_seg_arch_str
? riscv_rps_as.subset_list->arch_str : NULL;
make_mapping_symbol (to_state, value, frag_now, arch_str,
false/* odd_data_padding */);
}
/* Add the odd bytes of paddings for riscv_handle_align. */
static void
riscv_add_odd_padding_symbol (fragS *frag)
{
/* If there was already a mapping symbol, it should be
removed in the make_mapping_symbol.
Please see gas/testsuite/gas/riscv/mapping.s: .text.odd.align.*. */
make_mapping_symbol (MAP_DATA, frag->fr_fix, frag,
NULL/* arch_str */, true/* odd_data_padding */);
}
/* Remove any excess mapping symbols generated for alignment frags in
SEC. We may have created a mapping symbol before a zero byte
alignment; remove it if there's a mapping symbol after the
alignment. */
static void
riscv_check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED,
asection *sec,
void *dummy ATTRIBUTE_UNUSED)
{
segment_info_type *seginfo = seg_info (sec);
fragS *fragp;
if (seginfo == NULL || seginfo->frchainP == NULL)
return;
for (fragp = seginfo->frchainP->frch_root;
fragp != NULL;
fragp = fragp->fr_next)
{
symbolS *last = fragp->tc_frag_data.last_map_symbol;
fragS *next = fragp->fr_next;
if (last == NULL || next == NULL)
continue;
/* Check the last mapping symbol if it is at the boundary of
fragment. */
if (S_GET_VALUE (last) < next->fr_address)
continue;
know (S_GET_VALUE (last) == next->fr_address);
do
{
symbolS *next_first = next->tc_frag_data.first_map_symbol;
if (next_first != NULL)
{
/* The last mapping symbol overlaps with another one
which at the start of the next frag.
Please see the gas/testsuite/gas/riscv/mapping.s:
.text.zero.fill.align.A and .text.zero.fill.align.B. */
know (S_GET_VALUE (last) == S_GET_VALUE (next_first));
symbolS *removed = last;
if (strncmp (S_GET_NAME (last), "$xrv", 4) == 0
&& strcmp (S_GET_NAME (next_first), "$x") == 0)
removed = next_first;
symbol_remove (removed, &symbol_rootP, &symbol_lastP);
break;
}
if (next->fr_next == NULL)
{
/* The last mapping symbol is at the end of the section.
Please see the gas/testsuite/gas/riscv/mapping.s:
.text.last.section. */
know (next->fr_fix == 0 && next->fr_var == 0);
symbol_remove (last, &symbol_rootP, &symbol_lastP);
break;
}
/* Since we may have empty frags without any mapping symbols,
keep looking until the non-empty frag. */
if (next->fr_address != next->fr_next->fr_address)
break;
next = next->fr_next;
}
while (next != NULL);
}
}
/* The default target format to use. */
const char *
riscv_target_format (void)
{
if (target_big_endian)
return xlen == 64 ? "elf64-bigriscv" : "elf32-bigriscv";
else
return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv";
}
/* Return the length of instruction INSN. */
static inline unsigned int
insn_length (const struct riscv_cl_insn *insn)
{
return riscv_insn_length (insn->insn_opcode);
}
/* Initialise INSN from opcode entry MO. Leave its position unspecified. */
static void
create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo)
{
insn->insn_mo = mo;
insn->insn_opcode = mo->match;
insn->insn_long_opcode[0] = 0;
insn->frag = NULL;
insn->where = 0;
insn->fixp = NULL;
}
/* Install INSN at the location specified by its "frag" and "where" fields. */
static void
install_insn (const struct riscv_cl_insn *insn)
{
char *f = insn->frag->fr_literal + insn->where;
if (insn->insn_long_opcode[0] != 0)
memcpy (f, insn->insn_long_opcode, insn_length (insn));
else
number_to_chars_littleendian (f, insn->insn_opcode, insn_length (insn));
}
/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
and install the opcode in the new location. */
static void
move_insn (struct riscv_cl_insn *insn, fragS *frag, long where)
{
insn->frag = frag;
insn->where = where;
if (insn->fixp != NULL)
{
insn->fixp->fx_frag = frag;
insn->fixp->fx_where = where;
}
install_insn (insn);
}
/* Add INSN to the end of the output. */
static void
add_fixed_insn (struct riscv_cl_insn *insn)
{
char *f = frag_more (insn_length (insn));
move_insn (insn, frag_now, f - frag_now->fr_literal);
}
static void
add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var,
relax_substateT subtype, symbolS *symbol, offsetT offset)
{
frag_grow (max_chars);
move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
frag_var (rs_machine_dependent, max_chars, var,
subtype, symbol, offset, NULL);
}
/* Compute the length of a branch sequence, and adjust the stored length
accordingly. If FRAGP is NULL, the worst-case length is returned. */
static unsigned
relaxed_branch_length (fragS *fragp, asection *sec, int update)
{
int jump, rvc, length = 8;
if (!fragp)
return length;
jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype);
rvc = RELAX_BRANCH_RVC (fragp->fr_subtype);
length = RELAX_BRANCH_LENGTH (fragp->fr_subtype);
/* Assume jumps are in range; the linker will catch any that aren't. */
length = jump ? 4 : 8;
if (fragp->fr_symbol != NULL
&& S_IS_DEFINED (fragp->fr_symbol)
&& !S_IS_WEAK (fragp->fr_symbol)
&& sec == S_GET_SEGMENT (fragp->fr_symbol))
{
offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset;
bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH;
val -= fragp->fr_address + fragp->fr_fix;
if (rvc && (bfd_vma)(val + rvc_range/2) < rvc_range)
length = 2;
else if ((bfd_vma)(val + RISCV_BRANCH_REACH/2) < RISCV_BRANCH_REACH)
length = 4;
else if (!jump && rvc)
length = 6;
}
if (update)
fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length);
return length;
}
/* Information about an opcode name, mnemonics and its value. */
struct opcode_name_t
{
const char *name;
unsigned int val;
};
/* List for all supported opcode name. */
static const struct opcode_name_t opcode_name_list[] =
{
{"C0", 0x0},
{"C1", 0x1},
{"C2", 0x2},
{"LOAD", 0x03},
{"LOAD_FP", 0x07},
{"CUSTOM_0", 0x0b},
{"MISC_MEM", 0x0f},
{"OP_IMM", 0x13},
{"AUIPC", 0x17},
{"OP_IMM_32", 0x1b},
/* 48b 0x1f. */
{"STORE", 0x23},
{"STORE_FP", 0x27},
{"CUSTOM_1", 0x2b},
{"AMO", 0x2f},
{"OP", 0x33},
{"LUI", 0x37},
{"OP_32", 0x3b},
/* 64b 0x3f. */
{"MADD", 0x43},
{"MSUB", 0x47},
{"NMADD", 0x4f},
{"NMSUB", 0x4b},
{"OP_FP", 0x53},
{"OP_V", 0x57},
{"CUSTOM_2", 0x5b},
/* 48b 0x5f. */
{"BRANCH", 0x63},
{"JALR", 0x67},
/*reserved 0x5b. */
{"JAL", 0x6f},
{"SYSTEM", 0x73},
/*reserved 0x77. */
{"CUSTOM_3", 0x7b},
/* >80b 0x7f. */
{NULL, 0}
};
/* Hash table for lookup opcode name. */
static htab_t opcode_names_hash = NULL;
/* Initialization for hash table of opcode name. */
static void
init_opcode_names_hash (void)
{
const struct opcode_name_t *opcode;
for (opcode = &opcode_name_list[0]; opcode->name != NULL; ++opcode)
if (str_hash_insert (opcode_names_hash, opcode->name, opcode, 0) != NULL)
as_fatal (_("internal: duplicate %s"), opcode->name);
}
/* Find `s` is a valid opcode name or not, return the opcode name info
if found. */
static const struct opcode_name_t *
opcode_name_lookup (char **s)
{
char *e;
char save_c;
struct opcode_name_t *o;
/* Find end of name. */
e = *s;
if (is_name_beginner (*e))
++e;
while (is_part_of_name (*e))
++e;
/* Terminate name. */
save_c = *e;
*e = '\0';
o = (struct opcode_name_t *) str_hash_find (opcode_names_hash, *s);
/* Advance to next token if one was recognized. */
if (o)
*s = e;
*e = save_c;
expr_parse_end = e;
return o;
}
/* All RISC-V registers belong to one of these classes. */
enum reg_class
{
RCLASS_GPR,
RCLASS_FPR,
RCLASS_VECR,
RCLASS_VECM,
RCLASS_MAX,
RCLASS_CSR
};
static htab_t reg_names_hash = NULL;
static htab_t csr_extra_hash = NULL;
#define ENCODE_REG_HASH(cls, n) \
((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1))
#define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX)
#define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX)
static void
hash_reg_name (enum reg_class class, const char *name, unsigned n)
{
void *hash = ENCODE_REG_HASH (class, n);
if (str_hash_insert (reg_names_hash, name, hash, 0) != NULL)
as_fatal (_("internal: duplicate %s"), name);
}
static void
hash_reg_names (enum reg_class class, const char names[][NRC], unsigned n)
{
unsigned i;
for (i = 0; i < n; i++)
hash_reg_name (class, names[i], i);
}
/* Init hash table csr_extra_hash to handle CSR. */
static void
riscv_init_csr_hash (const char *name,
unsigned address,
enum riscv_csr_class class,
enum riscv_spec_class define_version,
enum riscv_spec_class abort_version)
{
struct riscv_csr_extra *entry, *pre_entry;
bool need_enrty = true;
pre_entry = NULL;
entry = (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, name);
while (need_enrty && entry != NULL)
{
if (entry->csr_class == class
&& entry->address == address
&& entry->define_version == define_version
&& entry->abort_version == abort_version)
need_enrty = false;
pre_entry = entry;
entry = entry->next;
}
/* Duplicate CSR. */
if (!need_enrty)
return;
entry = notes_alloc (sizeof (*entry));
entry->csr_class = class;
entry->address = address;