Error in PERIPHERAL_CLOCK_I2S_ENABLE() for BL70x.

[pvvx]

I2S is not working.

PERIPHERAL_CLOCK_I2S_ENABLE()

#define PERIPHERAL_CLOCK_I2S_ENABLE()                             \
    do {                                                          \
        volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
        regval |= (1 << 27);                                      \
        putreg32(regval, BFLB_GLB_CGEN1_BASE);                    \
    } while (0)

BL702/704/706 Reference Manual:
3.3.9 cgen_cfg1
Address：0x40000024
i2s and qdec2 clock ungate enable - bit 26

If corrected, then I2S will work.

[sakumisu]

I2S lhal driver only works for bl616 and bl808 now.

[sakumisu]

No test in bl702.

[pvvx]

I connected PCM1802 for tests and got it working on all CLK variants.

Stereo 96 kHz 24 bit is successfully transmitted from PCM1802 and BL702 via USB.
The PDS_Set_Audio_PLL_Freq() function has only 5 fixed frequencies, which is inconvenient.
For the project, I needed to change the MCLK frequency, but there is no documentation on setting up the AUDIO PLL.
I had to make research to generate any frequency from 0.5 to 80 MHz with a small step to output from the chip (GLB_Set_I2S_CLK(ENABLE, GLB_I2S_OUT_REF_CLK_SRC)) ; (with acceptable jitter)

When DC filtering is disabled on the PCM1802, the RV-Debugger-BL702 receives a 24-bit, 2-channel ADC in USB with smooth sampling from 1 to 100 kHz.

SNR

100 ksps.

PS: As a result, I2S in BL702 works well in Slave and Master modes. But a lot is missing from the SDK and documentation...

[sakumisu]

Thank you for such a detailed explanation. This will be completed later