Strange scheme of clock dividers for i2s and audio dac/adc

[dbnnrmn]

I think that information about clocks for Bl616/618 for i2s is not full. And examples in sdk are not understandable and contain some mistakes.
According to scheme i2s and audio must have same input frequency,but frequencies are different, why? And what value of divider have "aupll_other" got?

In examples code set divider after 24.576, but how to set divider before?

GLB_Config_AUDIO_PLL_To_491P52M();
    GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_AUDIO);

    /*!< output MCLK,
        Will change the clock source of i2s,
        It needs to be called before i2s is initialized
        clock source 24.576M */

    /*!< MCLK = 24.576 / (5+1) = 4.096MHz */
    GLB_Set_I2S_CLK(ENABLE, 5, GLB_I2S_DI_SEL_I2S_DI_INPUT, GLB_I2S_DO_SEL_I2S_DO_OUTPT);
    GLB_Set_Chip_Clock_Out3_Sel(GLB_CHIP_CLK_OUT_3_I2S_REF_CLK);

there is no information about that and api .What does "DI_INPUT" mean?

In ref manual I see values 24.576/24 Mhz
In other examples in some places I see value 25 Mhz.
Where do these values come from?

 /* output MCLK,
    Will change the clock source of i2s,
    It needs to be called before i2s is initialized
    clock source 25M
    */
    GLB_Set_I2S_CLK(ENABLE, 2, GLB_I2S_DI_SEL_I2S_DI_INPUT, GLB_I2S_DO_SEL_I2S_DO_OUTPT);
    GLB_Set_Chip_Clock_Out3_Sel(GLB_CHIP_CLK_OUT_3_I2S_REF_CLK);

[O2C14]

An example for setting up auclk

void seti2sclock(uint32_t sample_rate, uint32_t bit_width)
{
    uint8_t div = 0;
    uint32_t base_freq = 48000;
    if ((sample_rate % 44100) == 0) {
        GLB_Config_AUDIO_PLL_To_451P58M();
        base_freq = 44100;
    } else if ((sample_rate % 48000) == 0) {
        GLB_Config_AUDIO_PLL_To_491P52M();
        base_freq = 48000;
    } else {
        printf("sample_rate error:%d\r\n", sample_rate);
    }
    if (bit_width != 24) {
        div = (8 / (((sample_rate) / base_freq) * ((bit_width) / 16))) - 1;
    } else {
        printf("bit_width error:%d\r\n", bit_width);
    }
    GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_AUDIO);
    GLB_Set_I2S_CLK(ENABLE, div, GLB_I2S_DI_SEL_I2S_DI_INPUT, GLB_I2S_DO_SEL_I2S_DO_OUTPT);
    GLB_Set_Chip_Clock_Out3_Sel(GLB_CHIP_CLK_OUT_3_I2S_REF_CLK);
}

[dbnnrmn]

Thanks, but it is not answer to my question. What frequency does i2s module have after setting of audio pll?