/
prog.go
165 lines (147 loc) · 6.73 KB
/
prog.go
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// Copyright 2013 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
package arm
import (
"cmd/compile/internal/gc"
"cmd/internal/obj"
"cmd/internal/obj/arm"
)
const (
RightRdwr = gc.RightRead | gc.RightWrite
)
// This table gives the basic information about instruction
// generated by the compiler and processed in the optimizer.
// See opt.h for bit definitions.
//
// Instructions not generated need not be listed.
// As an exception to that rule, we typically write down all the
// size variants of an operation even if we just use a subset.
//
// The table is formatted for 8-space tabs.
var progtable = [arm.ALAST]obj.ProgInfo{
obj.ATYPE: {gc.Pseudo | gc.Skip, 0, 0, 0},
obj.ATEXT: {gc.Pseudo, 0, 0, 0},
obj.AFUNCDATA: {gc.Pseudo, 0, 0, 0},
obj.APCDATA: {gc.Pseudo, 0, 0, 0},
obj.AUNDEF: {gc.Break, 0, 0, 0},
obj.AUSEFIELD: {gc.OK, 0, 0, 0},
obj.ACHECKNIL: {gc.LeftRead, 0, 0, 0},
obj.AVARDEF: {gc.Pseudo | gc.RightWrite, 0, 0, 0},
obj.AVARKILL: {gc.Pseudo | gc.RightWrite, 0, 0, 0},
// NOP is an internal no-op that also stands
// for USED and SET annotations, not the Intel opcode.
obj.ANOP: {gc.LeftRead | gc.RightWrite, 0, 0, 0},
// Integer.
arm.AADC: {gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0},
arm.AADD: {gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0},
arm.AAND: {gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0},
arm.ABIC: {gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0},
arm.ACMN: {gc.SizeL | gc.LeftRead | gc.RightRead, 0, 0, 0},
arm.ACMP: {gc.SizeL | gc.LeftRead | gc.RightRead, 0, 0, 0},
arm.ADIVU: {gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0},
arm.ADIV: {gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0},
arm.AEOR: {gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0},
arm.AMODU: {gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0},
arm.AMOD: {gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0},
arm.AMULALU: {gc.SizeL | gc.LeftRead | gc.RegRead | RightRdwr, 0, 0, 0},
arm.AMULAL: {gc.SizeL | gc.LeftRead | gc.RegRead | RightRdwr, 0, 0, 0},
arm.AMULA: {gc.SizeL | gc.LeftRead | gc.RegRead | RightRdwr, 0, 0, 0},
arm.AMULU: {gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0},
arm.AMUL: {gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0},
arm.AMULL: {gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0},
arm.AMULLU: {gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0},
arm.AMVN: {gc.SizeL | gc.LeftRead | gc.RightWrite, 0, 0, 0},
arm.AORR: {gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0},
arm.ARSB: {gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0},
arm.ARSC: {gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0},
arm.ASBC: {gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0},
arm.ASLL: {gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0},
arm.ASRA: {gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0},
arm.ASRL: {gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0},
arm.ASUB: {gc.SizeL | gc.LeftRead | gc.RegRead | gc.RightWrite, 0, 0, 0},
arm.ATEQ: {gc.SizeL | gc.LeftRead | gc.RightRead, 0, 0, 0},
arm.ATST: {gc.SizeL | gc.LeftRead | gc.RightRead, 0, 0, 0},
// Floating point.
arm.AADDD: {gc.SizeD | gc.LeftRead | RightRdwr, 0, 0, 0},
arm.AADDF: {gc.SizeF | gc.LeftRead | RightRdwr, 0, 0, 0},
arm.ACMPD: {gc.SizeD | gc.LeftRead | gc.RightRead, 0, 0, 0},
arm.ACMPF: {gc.SizeF | gc.LeftRead | gc.RightRead, 0, 0, 0},
arm.ADIVD: {gc.SizeD | gc.LeftRead | RightRdwr, 0, 0, 0},
arm.ADIVF: {gc.SizeF | gc.LeftRead | RightRdwr, 0, 0, 0},
arm.AMULD: {gc.SizeD | gc.LeftRead | RightRdwr, 0, 0, 0},
arm.AMULF: {gc.SizeF | gc.LeftRead | RightRdwr, 0, 0, 0},
arm.ASUBD: {gc.SizeD | gc.LeftRead | RightRdwr, 0, 0, 0},
arm.ASUBF: {gc.SizeF | gc.LeftRead | RightRdwr, 0, 0, 0},
arm.ASQRTD: {gc.SizeD | gc.LeftRead | RightRdwr, 0, 0, 0},
// Conversions.
arm.AMOVWD: {gc.SizeD | gc.LeftRead | gc.RightWrite | gc.Conv, 0, 0, 0},
arm.AMOVWF: {gc.SizeF | gc.LeftRead | gc.RightWrite | gc.Conv, 0, 0, 0},
arm.AMOVDF: {gc.SizeF | gc.LeftRead | gc.RightWrite | gc.Conv, 0, 0, 0},
arm.AMOVDW: {gc.SizeL | gc.LeftRead | gc.RightWrite | gc.Conv, 0, 0, 0},
arm.AMOVFD: {gc.SizeD | gc.LeftRead | gc.RightWrite | gc.Conv, 0, 0, 0},
arm.AMOVFW: {gc.SizeL | gc.LeftRead | gc.RightWrite | gc.Conv, 0, 0, 0},
// Moves.
arm.AMOVB: {gc.SizeB | gc.LeftRead | gc.RightWrite | gc.Move, 0, 0, 0},
arm.AMOVD: {gc.SizeD | gc.LeftRead | gc.RightWrite | gc.Move, 0, 0, 0},
arm.AMOVF: {gc.SizeF | gc.LeftRead | gc.RightWrite | gc.Move, 0, 0, 0},
arm.AMOVH: {gc.SizeW | gc.LeftRead | gc.RightWrite | gc.Move, 0, 0, 0},
arm.AMOVW: {gc.SizeL | gc.LeftRead | gc.RightWrite | gc.Move, 0, 0, 0},
// In addtion, duffzero reads R0,R1 and writes R1. This fact is
// encoded in peep.c
obj.ADUFFZERO: {gc.Call, 0, 0, 0},
// In addtion, duffcopy reads R1,R2 and writes R0,R1,R2. This fact is
// encoded in peep.c
obj.ADUFFCOPY: {gc.Call, 0, 0, 0},
// These should be split into the two different conversions instead
// of overloading the one.
arm.AMOVBS: {gc.SizeB | gc.LeftRead | gc.RightWrite | gc.Conv, 0, 0, 0},
arm.AMOVBU: {gc.SizeB | gc.LeftRead | gc.RightWrite | gc.Conv, 0, 0, 0},
arm.AMOVHS: {gc.SizeW | gc.LeftRead | gc.RightWrite | gc.Conv, 0, 0, 0},
arm.AMOVHU: {gc.SizeW | gc.LeftRead | gc.RightWrite | gc.Conv, 0, 0, 0},
// Jumps.
arm.AB: {gc.Jump | gc.Break, 0, 0, 0},
arm.ABL: {gc.Call, 0, 0, 0},
arm.ABEQ: {gc.Cjmp, 0, 0, 0},
arm.ABNE: {gc.Cjmp, 0, 0, 0},
arm.ABCS: {gc.Cjmp, 0, 0, 0},
arm.ABHS: {gc.Cjmp, 0, 0, 0},
arm.ABCC: {gc.Cjmp, 0, 0, 0},
arm.ABLO: {gc.Cjmp, 0, 0, 0},
arm.ABMI: {gc.Cjmp, 0, 0, 0},
arm.ABPL: {gc.Cjmp, 0, 0, 0},
arm.ABVS: {gc.Cjmp, 0, 0, 0},
arm.ABVC: {gc.Cjmp, 0, 0, 0},
arm.ABHI: {gc.Cjmp, 0, 0, 0},
arm.ABLS: {gc.Cjmp, 0, 0, 0},
arm.ABGE: {gc.Cjmp, 0, 0, 0},
arm.ABLT: {gc.Cjmp, 0, 0, 0},
arm.ABGT: {gc.Cjmp, 0, 0, 0},
arm.ABLE: {gc.Cjmp, 0, 0, 0},
obj.ARET: {gc.Break, 0, 0, 0},
}
func proginfo(p *obj.Prog) {
info := &p.Info
*info = progtable[p.As]
if info.Flags == 0 {
gc.Fatal("unknown instruction %v", p)
}
if p.From.Type == obj.TYPE_ADDR && p.From.Sym != nil && (info.Flags&gc.LeftRead != 0) {
info.Flags &^= gc.LeftRead
info.Flags |= gc.LeftAddr
}
if (info.Flags&gc.RegRead != 0) && p.Reg == 0 {
info.Flags &^= gc.RegRead
info.Flags |= gc.CanRegRead | gc.RightRead
}
if (p.Scond&arm.C_SCOND != arm.C_SCOND_NONE) && (info.Flags&gc.RightWrite != 0) {
info.Flags |= gc.RightRead
}
switch p.As {
case arm.ADIV,
arm.ADIVU,
arm.AMOD,
arm.AMODU:
info.Regset |= RtoB(arm.REG_R12)
}
}