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Cpu.cpp
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Cpu.cpp
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#include <stdio.h>
#include <stdlib.h>
#include <memory.h>
#include "Cpu.h"
#include "Tedmem.h"
//#define CPU_STATS
#ifdef CPU_STATS
#include "Cpu7501asm.h"
#endif
// this one is much quicker
#define push(VALUE) (stack[SP--]=(VALUE))
#define pull() (stack[SP])
bool CPU::bp_active = false;
bool CPU::bp_reached = false;
const unsigned int CPU::nr_of_bps = 11;
static unsigned int stats[255];
CPU::CPU( MemoryHandler *memhandler, unsigned char *irqreg, unsigned char *cpustack ) : mem(memhandler), irq_register(irqreg), stack(cpustack)
{
irq_sequence = 0;
IRQcount = 0;
cpu_jammed = false;
PC = 0xFFFF;
for( int i=0; i<nr_of_bps; i++) {
bp[i].address = 0x10000;
bp[i].enabled = false;
bp[i].slot_free = true;
}
nr_activebps = 0;
memset( stats, 0, sizeof(stats));
}
unsigned int CPU::getcins()
{
// currins is set to 0x00 when in IRQ so we have to re-fetch the opcode
// this is only used for debugging & co.
return (currins==0) ? mem->Read((PC-1)&0xFFFF) : currins&0xFF;
};
bool CPU::saveshot(void *CPUdump)
{
FILE *img = (FILE *) CPUdump;
fwrite(&currins,sizeof(currins),1,img);
fwrite(&nextins,sizeof(nextins),1,img);
fwrite(&ptr,sizeof(ptr),1,img);
fwrite(&PC,sizeof(PC),1,img);
fwrite(&cycle,sizeof(cycle),1,img);
fwrite(&SP,sizeof(SP),1,img);
fwrite(&ST,sizeof(ST),1,img);
fwrite(&AC,sizeof(AC),1,img);
fwrite(&X,sizeof(X),1,img);
fwrite(&Y,sizeof(Y),1,img);
return true;
}
bool CPU::loadshot(void *CPUdump)
{
FILE *img = (FILE *) CPUdump;
fread(&currins,sizeof(currins),1,img);
fread(&nextins,sizeof(nextins),1,img);
fread(&ptr,sizeof(ptr),1,img);
fread(&PC,sizeof(PC),1,img);
PC &= 0xFFFF;
fread(&cycle,sizeof(cycle),1,img);
fread(&SP,sizeof(SP),1,img);
fread(&ST,sizeof(ST),1,img);
fread(&AC,sizeof(AC),1,img);
fread(&X,sizeof(X),1,img);
fread(&Y,sizeof(Y),1,img);
return true;
}
// reset keeps all except for PC
void CPU::Reset()
{
ST=0x24;
softreset();
IRQcount = cycle = 0;
irq_sequence = 0;
}
void CPU::softreset()
{
// clear the BRK flag
ST&=0xEF;
setPC(mem->Read(0xFFFC)|(mem->Read(0xFFFD)<<8));
}
void CPU::setPC(unsigned int addr)
{
PC=addr;
cycle=0;
}
inline void CPU::DoCompare(unsigned char reg, unsigned char value)
{
ST = (ST & 0xFE) | ( value<=reg);
SETFLAGS_ZN( reg - value);
}
void CPU::process()
{
if (IRQcount || ((*irq_register)&0x80 ) && !irq_sequence && !(ST&0x04))
IRQcount++;
if (!cycle) { // in the first cycle the CPU fetches the opcode
if (IRQcount>=3 && currins != 0x58) {
IRQcount = 0;
if (!(ST&0x04) || currins == 0x78) { //
irq_sequence = 0x10; // this is 0x10 to match the B flag later
currins = 0x00; // we could use BRK for the IRQ routine!
cycle = 1;
return;
}
}
currins=mem->Read(PC); // fetch opcode
nextins=mem->Read(PC+1); // prefetch next opcode/operand
cycle = 1; // increment the CPU cycle counter
#ifdef CPU_STATS
stats[currins]++;
static FILE *f = fopen("disasm.txt", "a");
//unsigned char t = mem->Read(PC+1);
if (f)
fprintf(f, ". %04X %s", PC, ins[currins].name);
int i = 1;
while (i < typlen[ins[currins].type] && f) {
fprintf(f, " %02X", mem->Read(PC+i++));
}
fprintf(f, "\n");
fflush(f);
#endif
PC=(PC+1)&0xFFFF;
}
else
switch (currins){
case 0xea : // NOP
cycle=0;
break;
case 0x18 : // CLC
ST&=0xFE;
cycle=0;
break;
case 0x38 : // SEC
ST|=0x01;
cycle=0;
break;
case 0x58 : // CLI
ST&=0xFB;
cycle=0;
break;
case 0x78 : // SEI
ST|=0x04;
cycle=0;
// actually, IRQ can still occur right after the SEI instruction
// some programs (like Castle Master) rely on it.
// Therefore startIRQ is not set to 0 here.
//IRQcount = 0;
break;
case 0xb8 : // CLV
// This has to be more generic because the drive byte ready
// line is connected to the V flag pin on the disk drive CPU
ClearVFlag();
cycle=0;
break;
case 0xD8 : // CLD
ST&=0xF7;
cycle=0;
break;
case 0xF8 : // SED
ST|=0x08;
cycle=0;
break;
// branch functions (conditional jumps )
case 0x10 : // BPL
switch(cycle++) {
case 1: PC++;
if ((ST&0x80))
cycle=0;
break;
case 2: if (!(((PC&0xFF)+(signed char) nextins)&0xFF00)) {
PC+=(signed char) nextins;
cycle=0;
};
break;
case 3: PC+=(signed char) nextins;
cycle=0;
break;
};
break;
case 0x30 : // BMI
switch(cycle++) {
case 1: PC++;
if (!(ST&0x80))
cycle=0;
break;
case 2: if (!(((PC&0xFF)+(signed char) nextins)&0xFF00)) {
PC+=(signed char) nextins;
cycle=0;
};
break;
case 3: PC+=(signed char) nextins;
cycle=0;
break;
};
break;
case 0x50 : // BVC
switch(cycle++) {
// This has to be more generic because the drive byte ready
// line is connected to the V flag pin on the disk drive CPU
case 1: PC++;
if (CheckVFlag())
cycle=0;
break;
case 2: if (!(((PC&0xFF)+(signed char) nextins)&0xFF00)) {
PC+=(signed char) nextins;
cycle=0;
};
break;
case 3: PC+=(signed char) nextins;
cycle=0;
break;
};
break;
case 0x70 : // BVS
switch(cycle++) {
// This has to be more generic because the drive byte ready
// line is connected to the V flag pin on the disk drive CPU
case 1: PC++;
if (!(CheckVFlag()))
cycle=0;
break;
case 2: if (!(((PC&0xFF)+(signed char) nextins)&0xFF00)) {
PC+=(signed char) nextins;
cycle=0;
};
break;
case 3: PC+=(signed char) nextins;
cycle=0;
break;
};
break;
case 0x90 : // BCC
switch(cycle++) {
case 1: PC++;
if (ST&0x01)
cycle=0;
break;
case 2: if (!(((PC&0xFF)+(signed char) nextins)&0xFF00)) {
PC+=(signed char) nextins;
cycle=0;
};
break;
case 3: PC+=(signed char) nextins;
cycle=0;
break;
};
break;
case 0xB0 : // BCS
switch(cycle++) {
case 1: PC++;
if (!(ST&0x01))
cycle=0;
break;
case 2: if (!(((PC&0xFF)+(signed char) nextins)&0xFF00)) {
PC+=(signed char) nextins;
cycle=0;
};
break;
case 3: PC+=(signed char) nextins;
cycle=0;
break;
};
break;
case 0xD0 : // BNE
switch(cycle++) {
case 1: PC++;
if (ST&0x02)
cycle=0;
break;
case 2: if (!(((PC&0xFF)+(signed char) nextins)&0xFF00)) {
PC+=(signed char) nextins;
cycle=0;
};
break;
case 3: PC+=(signed char) nextins;
cycle=0;
break;
};
break;
case 0xF0 : // BEQ
switch(cycle++) {
case 1: PC++;
if (!(ST&0x02))
cycle=0;
break;
case 2: if (!(((PC&0xFF)+(signed char) nextins)&0xFF00)) {
PC+=(signed char) nextins;
cycle=0;
};
break;
case 3: PC+=(signed char) nextins;
cycle=0;
break;
};
break;
// manipulating index registers
case 0x88 : // DEY
--Y;
SETFLAGS_ZN(Y);
cycle=0;
break;
case 0xC8 : // INY
++Y;
SETFLAGS_ZN(Y);
cycle=0;
break;
case 0xCA : // DEX
--X;
SETFLAGS_ZN(X);
cycle=0;
break;
case 0xE8 : // INX
++X;
SETFLAGS_ZN(X);
cycle=0;
break;
case 0x00 : // BRK
switch (cycle++) {
case 1: if (!irq_sequence)
PC++;
break;
case 2: push(PC>>8);
break;
case 3: push(PC&0xFF);
break;
case 4: // BRK pushes the status register to the stack with the B bit set
// IRQ can still occur on BRK before saving the flags
// if (!(ST&0x04)) irq_sequence = 0x10;
push((ST|0x30)&~irq_sequence);
// and then masks the interrupt bit
ST|=0x04;
break;
case 5: break;
case 6: PC=mem->Read(0xFFFE)|(mem->Read(0xFFFF)<<8);
irq_sequence = 0x0;
cycle=0;
break;
};
break;
/*case 0x00 : // BRK
switch (cycle++) {
case 1: PC++;
break;
case 2: push(PC>>8);
break;
case 3: push(PC&0xFF);
break;
case 4: // BRK pushes the status register to the stack with the B bit set
// IRQ can still occur on BRK before saving the flags
// if (!(ST&0x04)) irq_sequence = 0x10;
push((ST|0x30));
// and then masks the interrupt bit
ST|=0x04;
break;
case 5: break;
case 6: PC=mem->Read(0xFFFE)|(mem->Read(0xFFFF)<<8);
cycle=0;
break;
};
break;
case 0x100 : // IRQ - pseudo opcode
switch (cycle++) {
case 1: break;
case 2: push(PC>>8);
break;
case 3: push(PC&0xFF);
break;
case 4: push((ST|0x20)&0xEF);
// and then masks the interrupt bit
ST|=0x04;
break;
case 5: break;
case 6: PC=mem->Read(0xFFFE)|(mem->Read(0xFFFF)<<8);
//irq_sequence = 0x0;
cycle=0;
break;
};
break;*/
case 0x40 : // RTI
switch (cycle++) {
case 1: //PC++;
break;
case 2: //PC++;
SP++;
break;
case 3: // the B flag is already always cleared
ST=pull();//&0xEF;
SP++;
break;
case 4: PC=pull();
SP++;
break;
case 5: PC|=pull()<<8;
//ST&=0xFB;
cycle=0;
break;
};
break;
case 0x60 : // RTS
switch (cycle++) {
case 1: //PC++;
break;
case 2: //PC++;
SP++;
break;
case 3: PC=pull();
SP++;
break;
case 4: PC|=pull()<<8;
break;
case 5: PC++;
cycle=0;
break;
};
break;
// stack operations
case 0x08 : // PHP
if (cycle++==2) {
// the PHP always pushes the status with the B flag set...
//ST = (ST&0xBF)|CheckVFlag();
push(ST|0x30);
cycle=0;
};
break;
case 0x28 : // PLP
if (cycle++==3) {
SP++;
ST=(pull() /*&0xEF*/);//|(0x20);
cycle=0;
};
break;
case 0x48 : // PHA
if (cycle++==2) {
push(AC);
cycle=0;
};
break;
case 0x68 : // PLA
if (cycle++==3) {
SP++;
AC=pull();
SETFLAGS_ZN(AC);
cycle=0;
};
break;
// inter-register operations
case 0x8A : // TXA
AC=X;
SETFLAGS_ZN(AC);
cycle=0;
break;
case 0xAA : // TAX
X=AC;
SETFLAGS_ZN(X);
cycle=0;
break;
case 0x98 : // TYA
AC=Y;
SETFLAGS_ZN(AC);
cycle=0;
break;
case 0xA8 : // TAY
Y=AC;
SETFLAGS_ZN(Y);
cycle=0;
break;
case 0x9A : // TXS
SP=X;
cycle=0;
break;
case 0xBA : // TSX
X=SP;
SETFLAGS_ZN(X);
cycle=0;
break;
// subroutine & unconditional jump
case 0x20 : // JSR
switch (cycle++) {
case 1: PC++;
break;
case 2: // unknown
break;
case 3: push(PC>>8);
break;
case 4: push(PC&0xFF);
break;
case 5: PC=ptr=nextins|(mem->Read(PC)<<8);
cycle=0;
break;
};
break;
case 0x4C : // JMP $0000
if (cycle++==2) {
PC=nextins|(mem->Read(PC+1)<<8);
cycle=0;
};
break;
case 0x6C : // JMP ($0000)
if (cycle++==4) {
ptr=nextins|(mem->Read(PC+1)<<8);
// instruction does not handle page crossing
PC=mem->Read(ptr)|(mem->Read( ptr&0xFF00 | (ptr+1)&0xFF) << 8);
cycle=0;
};
break;
// Accumulator operations with immediate addressing
case 0x09 : // ORA #$00
PC++;
AC|=nextins;
SETFLAGS_ZN(AC);
cycle=0;
break;
case 0x29 : // AND #$00
PC++;
AC&=nextins;
SETFLAGS_ZN(AC);
cycle=0;
break;
case 0x49 : // EOR #$00
PC++;
AC^=nextins;
SETFLAGS_ZN(AC);
cycle=0;
break;
case 0x69 : // ADC #$00
PC++;
ADC(nextins);
cycle=0;
break;
case 0xC9 : // CMP #$00
PC++;
DoCompare(AC,nextins);
cycle=0;
break;
case 0xE9 : // SBC #$00
PC++;
SBC(nextins);
cycle=0;
break;
// rotations
case 0x0A : // ASL
AC&0x80 ? ST|=0x01 : ST&=0xFE; // the Carry flag
AC<<=1;
SETFLAGS_ZN(AC);
cycle=0;
break;
case 0x2A : // ROL
nextins=(AC<<1)|(ST&0x01);
AC&0x80 ? ST|=0x01 : ST&=0xFE; // the Carry flag
AC=nextins;
SETFLAGS_ZN(AC);
cycle=0;
break;
case 0x4A : // LSR
AC&0x01 ? ST|=0x01 : ST&=0xFE; // the Carry flag
AC=AC>>1;
SETFLAGS_ZN(AC);
cycle=0;
break;
case 0x6A : // ROR
nextins=(AC>>1)|((ST&0x01)<<7);
AC&0x01 ? ST|=0x01 : ST&=0xFE; // the Carry flag
AC=nextins;
SETFLAGS_ZN(AC);
cycle=0;
break;
// loads
case 0xA0 : // LDY
PC++;
Y=nextins;
SETFLAGS_ZN(Y);
cycle=0;
break;
case 0xA2 : // LDX
PC++;
X=nextins;
SETFLAGS_ZN(X);
cycle=0;
break;
case 0xA9 : // LDA
PC++;
AC=nextins;
SETFLAGS_ZN(AC);
cycle=0;
break;
// comparisons with immediate addressing
case 0xC0 : // CPY
PC++;
DoCompare(Y,nextins);
cycle=0;
break;
case 0xE0 : // CPX
PC++;
DoCompare(X,nextins);
cycle=0;
break;
// BIT tests with accumulator
case 0x24 : // BIT $00
switch (cycle++) {
case 1: PC++;
break;
case 2: nextins=mem->Read(nextins);
ST = (ST&0x3D)
| (nextins&0xC0)
| (((AC&nextins)==0)<<1);
/*if (!(ST&0x40))
ClearVFlag();*/
cycle=0;
break;
};
break;
case 0x2C : // BIT $0000
switch (cycle++) {
case 1: PC++;
ptr=nextins|(mem->Read(PC)<<8);
break;
case 2: PC++;
break;
case 3: nextins=mem->Read(ptr);
ST = (ST&0x3D)
| (nextins&0xC0)
| (((AC&nextins)==0)<<1);
/*if (!(ST&0x40))
ClearVFlag();*/
cycle=0;
break;
};
break;
// Read instructions with absolute addressing
case 0x0D : // ORA $0000
switch (cycle++) {
case 1: PC++;
ptr=nextins|(mem->Read(PC)<<8);
break;
case 2: PC++;
break;
case 3: AC|=mem->Read(ptr);
SETFLAGS_ZN(AC);
cycle=0;
break;
};
break;
case 0x2D : // AND $0000
switch (cycle++) {
case 1: PC++;
ptr=nextins|(mem->Read(PC)<<8);
break;
case 2: PC++;
break;
case 3: AC&=mem->Read(ptr);
SETFLAGS_ZN(AC);
cycle=0;
};
break;
case 0x4D : // EOR $0000
switch (cycle++) {
case 1: PC++;
ptr=nextins|(mem->Read(PC)<<8);
break;
case 2: PC++;
break;
case 3: AC^=mem->Read(ptr);
SETFLAGS_ZN(AC);
cycle=0;
break;
};
break;
case 0x6D : // ADC $0000
switch (cycle++) {
case 1: PC++;
ptr=nextins|(mem->Read(PC)<<8);
break;
case 2: PC++;
break;
case 3: ADC(mem->Read(ptr));
cycle=0;
break;
};
break;
case 0x99 : // STA $0000,Y
switch (cycle++) {
case 1: PC++;
ptr=nextins|(mem->Read(PC)<<8);
break;
case 2: PC++;
break;
case 3: break;
case 4: mem->Write(ptr+Y,AC);
cycle=0;
break;
};
break;
case 0xAC : // LDY $0000
switch (cycle++) {
case 1: PC++;
ptr=nextins|(mem->Read(PC)<<8);
break;
case 2: PC++;
break;
case 3: Y=mem->Read(ptr);
SETFLAGS_ZN(Y);
cycle=0;
break;
};
break;
case 0xCC : // CPY $0000
switch (cycle++) {
case 1: PC++;
ptr=nextins|(mem->Read(PC)<<8);
break;
case 2: PC++;
break;
case 3: DoCompare(Y,mem->Read(ptr));
cycle=0;
break;
};
break;
case 0xEC : // CPX $0000
switch (cycle++) {
case 1: PC++;
ptr=nextins|(mem->Read(PC)<<8);
break;
case 2: PC++;
break;
case 3: DoCompare(X,mem->Read(ptr));
cycle=0;
break;
};
break;
case 0xAD : // LDA $0000
switch (cycle++) {
case 1: PC++;
ptr=nextins|(mem->Read(PC)<<8);
break;
case 2: PC++;
break;
case 3: AC=mem->Read(ptr);
SETFLAGS_ZN(AC);
cycle=0;
break;
};
break;
case 0xCD : // CMP $0000
switch (cycle++) {
case 1: PC++;
ptr=nextins|(mem->Read(PC)<<8);
break;
case 2: PC++;
break;
case 3: DoCompare(AC,mem->Read(ptr));
cycle=0;
break;
};
break;
case 0xED : // SBC $0000
switch (cycle++) {
case 1: PC++;
ptr=nextins|(mem->Read(PC)<<8);
break;
case 2: PC++;
break;
case 3: SBC(mem->Read(ptr));
cycle=0;
break;
};
break;
case 0x0E : // ASL $0000
switch (cycle++) {
case 1: PC++;
ptr=nextins|(mem->Read(PC)<<8);
break;
case 2: PC++;
break;
case 3: nextins=mem->Read(ptr);
break;
case 4: mem->Write(ptr,nextins);
(nextins&0x80) ? ST|=0x01 : ST&=0xFE; // the Carry flag
nextins<<=1;
break;
case 5: mem->Write(ptr,nextins);
SETFLAGS_ZN(nextins);
cycle=0;
break;
};
break;
case 0x1E : // ASL $0000,X
switch (cycle++) {
case 1: PC++;
ptr=nextins|(mem->Read(PC)<<8);
break;
case 2: PC++;
break;
case 3: ptr+=X;
break;
case 4: nextins=mem->Read(ptr);
break;
case 5: mem->Write(ptr,nextins);
(nextins&0x80) ? ST|=0x01 : ST&=0xFE; // the Carry flag
nextins<<=1;
break;
case 6: mem->Write(ptr,nextins);
SETFLAGS_ZN(nextins);
cycle=0;
break;
};
break;
case 0x2E : // ROL $0000
switch (cycle++) {
case 1: PC++;
ptr=nextins|(mem->Read(PC)<<8);
break;
case 2: PC++;
break;
case 3: farins=mem->Read(ptr);
nextins=(farins<<1)|(ST&0x01);
break;
case 4: mem->Write(ptr,farins);
(farins&0x80) ? ST|=0x01 : ST&=0xFE; // the Carry flag
break;
case 5: mem->Write(ptr,nextins);
SETFLAGS_ZN(nextins);
cycle=0;
break;
};
break;
case 0x3E : // ROL $0000,X
switch (cycle++) {
case 1: PC++;
ptr=nextins|(mem->Read(PC)<<8);
break;
case 2: PC++;
break;
case 3: ptr+=X;
break;
case 4: farins=mem->Read(ptr);
nextins=(farins<<1)|(ST&0x01);
(farins&0x80) ? ST|=0x01 : ST&=0xFE; // the Carry flag
break;
case 5: mem->Write(ptr,farins);
break;
case 6: mem->Write(ptr,nextins);
SETFLAGS_ZN(nextins);
cycle=0;
break;
};
break;
case 0x4E : // LSR $0000
switch (cycle++) {
case 1: PC++;
ptr=nextins|(mem->Read(PC)<<8);
break;
case 2: PC++;
break;
case 3: nextins=mem->Read(ptr);
(nextins&0x01) ? ST|=0x01 : ST&=0xFE;; // the Carry flag
break;
case 4: mem->Write(ptr,nextins);
nextins=nextins>>1;
break;
case 5: mem->Write(ptr,nextins);
SETFLAGS_ZN(nextins);
cycle=0;
break;
};
break;
case 0x5E : // LSR $0000,X
switch (cycle++) {
case 1: PC++;
ptr=nextins|(mem->Read(PC)<<8);
break;
case 2: PC++;
break;
case 3: ptr+=X;
break;
case 4: nextins=mem->Read(ptr);
(nextins&0x01) ? ST|=0x01 : ST&=0xFE; // the Carry flag
break;
case 5: mem->Write(ptr,nextins);
nextins>>=1;
break;
case 6: mem->Write(ptr,nextins);
SETFLAGS_ZN(nextins);
cycle=0;
break;
};
break;
case 0x6E : // ROR $0000
switch (cycle++) {
case 1: PC++;
ptr=nextins|(mem->Read(PC)<<8);
break;
case 2: PC++;
break;
case 3: farins=mem->Read(ptr);
break;
case 4: mem->Write(ptr,farins);
nextins=(farins>>1)|((ST&0x01)<<7);
(farins&0x01) ? ST|=0x01 : ST&=0xFE; // the Carry flag
break;
case 5: mem->Write(ptr,nextins);
SETFLAGS_ZN(nextins);