Add IDX_SIZE information to .yxi outputs.

[nathanielnrn]

Currently yxi outputs only names, data width of the memory, and size of the memory in cells.
We should add IDX_SIZE information to this as well, as this is required when defining Calyx stdlib memories and we shouldn't be inferring idx sizes when such a value is explicitly defined.

[sampsyo]

It's a tricky question, I think… the weird thing is that, in an ideal world, Calyx memories would have their index size inferred (as ceil(log2(count-1)), I believe). We can't do that easily in real Calyx right now because there's no way to compute one width based on another; the only way to have any port width be parameterized is to have it be exactly equal to a parameter. So we're forced to have the user provide two parameters (element count & index width) when one "should" be enough.

So it might actually just be simpler to say that we only support memories with "typical" index sizes, and you shouldn't use an artificially large/small one that's not what you'd expect from the element count?