Extending the RISC-V ISA for exploring advanced reconfigurable SIMD instructions

[schirice]

Authors: Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk (Imperial College London)

[paulhjkelly]

You comment that your approach makes chaining of vector computations less necessary. Can you explain what you mean?

[pphilippos]

Thank you for the question. Since this approach allows instruction implementations of arbitrary pipeline length, a single custom instruction can replace multiple pre-defined Vector instructions, that would collectively implement the same task. This enables efficient task pipelining, since the user has the freedom to describe the custom instruction in low-level HDL/Verilog. This makes vector instruction chaining less necessary, though advanced pipelining of instructions in general, such as for loads and stores is still desirable.