/
dma.c
1693 lines (1483 loc) · 43.5 KB
/
dma.c
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/*
Broadcom B43legacy wireless driver
DMA ringbuffer and descriptor allocation/management
Copyright (c) 2005, 2006 Michael Buesch <m@bues.ch>
Some code in this file is derived from the b44.c driver
Copyright (C) 2002 David S. Miller
Copyright (C) Pekka Pietikainen
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING. If not, write to
the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
Boston, MA 02110-1301, USA.
*/
#include "b43legacy.h"
#include "dma.h"
#include "main.h"
#include "debugfs.h"
#include "xmit.h"
#include <linux/dma-mapping.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/skbuff.h>
#include <linux/slab.h>
#include <net/dst.h>
/* 32bit DMA ops. */
static
struct b43legacy_dmadesc_generic *op32_idx2desc(
struct b43legacy_dmaring *ring,
int slot,
struct b43legacy_dmadesc_meta **meta)
{
struct b43legacy_dmadesc32 *desc;
*meta = &(ring->meta[slot]);
desc = ring->descbase;
desc = &(desc[slot]);
return (struct b43legacy_dmadesc_generic *)desc;
}
static void op32_fill_descriptor(struct b43legacy_dmaring *ring,
struct b43legacy_dmadesc_generic *desc,
dma_addr_t dmaaddr, u16 bufsize,
int start, int end, int irq)
{
struct b43legacy_dmadesc32 *descbase = ring->descbase;
int slot;
u32 ctl;
u32 addr;
u32 addrext;
slot = (int)(&(desc->dma32) - descbase);
B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
addr = (u32)(dmaaddr & ~SSB_DMA_TRANSLATION_MASK);
addrext = (u32)(dmaaddr & SSB_DMA_TRANSLATION_MASK)
>> SSB_DMA_TRANSLATION_SHIFT;
addr |= ssb_dma_translation(ring->dev->dev);
ctl = (bufsize - ring->frameoffset)
& B43legacy_DMA32_DCTL_BYTECNT;
if (slot == ring->nr_slots - 1)
ctl |= B43legacy_DMA32_DCTL_DTABLEEND;
if (start)
ctl |= B43legacy_DMA32_DCTL_FRAMESTART;
if (end)
ctl |= B43legacy_DMA32_DCTL_FRAMEEND;
if (irq)
ctl |= B43legacy_DMA32_DCTL_IRQ;
ctl |= (addrext << B43legacy_DMA32_DCTL_ADDREXT_SHIFT)
& B43legacy_DMA32_DCTL_ADDREXT_MASK;
desc->dma32.control = cpu_to_le32(ctl);
desc->dma32.address = cpu_to_le32(addr);
}
static void op32_poke_tx(struct b43legacy_dmaring *ring, int slot)
{
b43legacy_dma_write(ring, B43legacy_DMA32_TXINDEX,
(u32)(slot * sizeof(struct b43legacy_dmadesc32)));
}
static void op32_tx_suspend(struct b43legacy_dmaring *ring)
{
b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL,
b43legacy_dma_read(ring, B43legacy_DMA32_TXCTL)
| B43legacy_DMA32_TXSUSPEND);
}
static void op32_tx_resume(struct b43legacy_dmaring *ring)
{
b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL,
b43legacy_dma_read(ring, B43legacy_DMA32_TXCTL)
& ~B43legacy_DMA32_TXSUSPEND);
}
static int op32_get_current_rxslot(struct b43legacy_dmaring *ring)
{
u32 val;
val = b43legacy_dma_read(ring, B43legacy_DMA32_RXSTATUS);
val &= B43legacy_DMA32_RXDPTR;
return (val / sizeof(struct b43legacy_dmadesc32));
}
static void op32_set_current_rxslot(struct b43legacy_dmaring *ring,
int slot)
{
b43legacy_dma_write(ring, B43legacy_DMA32_RXINDEX,
(u32)(slot * sizeof(struct b43legacy_dmadesc32)));
}
static const struct b43legacy_dma_ops dma32_ops = {
.idx2desc = op32_idx2desc,
.fill_descriptor = op32_fill_descriptor,
.poke_tx = op32_poke_tx,
.tx_suspend = op32_tx_suspend,
.tx_resume = op32_tx_resume,
.get_current_rxslot = op32_get_current_rxslot,
.set_current_rxslot = op32_set_current_rxslot,
};
/* 64bit DMA ops. */
static
struct b43legacy_dmadesc_generic *op64_idx2desc(
struct b43legacy_dmaring *ring,
int slot,
struct b43legacy_dmadesc_meta
**meta)
{
struct b43legacy_dmadesc64 *desc;
*meta = &(ring->meta[slot]);
desc = ring->descbase;
desc = &(desc[slot]);
return (struct b43legacy_dmadesc_generic *)desc;
}
static void op64_fill_descriptor(struct b43legacy_dmaring *ring,
struct b43legacy_dmadesc_generic *desc,
dma_addr_t dmaaddr, u16 bufsize,
int start, int end, int irq)
{
struct b43legacy_dmadesc64 *descbase = ring->descbase;
int slot;
u32 ctl0 = 0;
u32 ctl1 = 0;
u32 addrlo;
u32 addrhi;
u32 addrext;
slot = (int)(&(desc->dma64) - descbase);
B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
addrlo = (u32)(dmaaddr & 0xFFFFFFFF);
addrhi = (((u64)dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK);
addrext = (((u64)dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK)
>> SSB_DMA_TRANSLATION_SHIFT;
addrhi |= ssb_dma_translation(ring->dev->dev);
if (slot == ring->nr_slots - 1)
ctl0 |= B43legacy_DMA64_DCTL0_DTABLEEND;
if (start)
ctl0 |= B43legacy_DMA64_DCTL0_FRAMESTART;
if (end)
ctl0 |= B43legacy_DMA64_DCTL0_FRAMEEND;
if (irq)
ctl0 |= B43legacy_DMA64_DCTL0_IRQ;
ctl1 |= (bufsize - ring->frameoffset)
& B43legacy_DMA64_DCTL1_BYTECNT;
ctl1 |= (addrext << B43legacy_DMA64_DCTL1_ADDREXT_SHIFT)
& B43legacy_DMA64_DCTL1_ADDREXT_MASK;
desc->dma64.control0 = cpu_to_le32(ctl0);
desc->dma64.control1 = cpu_to_le32(ctl1);
desc->dma64.address_low = cpu_to_le32(addrlo);
desc->dma64.address_high = cpu_to_le32(addrhi);
}
static void op64_poke_tx(struct b43legacy_dmaring *ring, int slot)
{
b43legacy_dma_write(ring, B43legacy_DMA64_TXINDEX,
(u32)(slot * sizeof(struct b43legacy_dmadesc64)));
}
static void op64_tx_suspend(struct b43legacy_dmaring *ring)
{
b43legacy_dma_write(ring, B43legacy_DMA64_TXCTL,
b43legacy_dma_read(ring, B43legacy_DMA64_TXCTL)
| B43legacy_DMA64_TXSUSPEND);
}
static void op64_tx_resume(struct b43legacy_dmaring *ring)
{
b43legacy_dma_write(ring, B43legacy_DMA64_TXCTL,
b43legacy_dma_read(ring, B43legacy_DMA64_TXCTL)
& ~B43legacy_DMA64_TXSUSPEND);
}
static int op64_get_current_rxslot(struct b43legacy_dmaring *ring)
{
u32 val;
val = b43legacy_dma_read(ring, B43legacy_DMA64_RXSTATUS);
val &= B43legacy_DMA64_RXSTATDPTR;
return (val / sizeof(struct b43legacy_dmadesc64));
}
static void op64_set_current_rxslot(struct b43legacy_dmaring *ring,
int slot)
{
b43legacy_dma_write(ring, B43legacy_DMA64_RXINDEX,
(u32)(slot * sizeof(struct b43legacy_dmadesc64)));
}
static const struct b43legacy_dma_ops dma64_ops = {
.idx2desc = op64_idx2desc,
.fill_descriptor = op64_fill_descriptor,
.poke_tx = op64_poke_tx,
.tx_suspend = op64_tx_suspend,
.tx_resume = op64_tx_resume,
.get_current_rxslot = op64_get_current_rxslot,
.set_current_rxslot = op64_set_current_rxslot,
};
static inline int free_slots(struct b43legacy_dmaring *ring)
{
return (ring->nr_slots - ring->used_slots);
}
static inline int next_slot(struct b43legacy_dmaring *ring, int slot)
{
B43legacy_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));
if (slot == ring->nr_slots - 1)
return 0;
return slot + 1;
}
static inline int prev_slot(struct b43legacy_dmaring *ring, int slot)
{
B43legacy_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));
if (slot == 0)
return ring->nr_slots - 1;
return slot - 1;
}
#ifdef CONFIG_B43LEGACY_DEBUG
static void update_max_used_slots(struct b43legacy_dmaring *ring,
int current_used_slots)
{
if (current_used_slots <= ring->max_used_slots)
return;
ring->max_used_slots = current_used_slots;
if (b43legacy_debug(ring->dev, B43legacy_DBG_DMAVERBOSE))
b43legacydbg(ring->dev->wl,
"max_used_slots increased to %d on %s ring %d\n",
ring->max_used_slots,
ring->tx ? "TX" : "RX",
ring->index);
}
#else
static inline
void update_max_used_slots(struct b43legacy_dmaring *ring,
int current_used_slots)
{ }
#endif /* DEBUG */
/* Request a slot for usage. */
static inline
int request_slot(struct b43legacy_dmaring *ring)
{
int slot;
B43legacy_WARN_ON(!ring->tx);
B43legacy_WARN_ON(ring->stopped);
B43legacy_WARN_ON(free_slots(ring) == 0);
slot = next_slot(ring, ring->current_slot);
ring->current_slot = slot;
ring->used_slots++;
update_max_used_slots(ring, ring->used_slots);
return slot;
}
/* Mac80211-queue to b43legacy-ring mapping */
static struct b43legacy_dmaring *priority_to_txring(
struct b43legacy_wldev *dev,
int queue_priority)
{
struct b43legacy_dmaring *ring;
/*FIXME: For now we always run on TX-ring-1 */
return dev->dma.tx_ring1;
/* 0 = highest priority */
switch (queue_priority) {
default:
B43legacy_WARN_ON(1);
/* fallthrough */
case 0:
ring = dev->dma.tx_ring3;
break;
case 1:
ring = dev->dma.tx_ring2;
break;
case 2:
ring = dev->dma.tx_ring1;
break;
case 3:
ring = dev->dma.tx_ring0;
break;
case 4:
ring = dev->dma.tx_ring4;
break;
case 5:
ring = dev->dma.tx_ring5;
break;
}
return ring;
}
/* Bcm4301-ring to mac80211-queue mapping */
static inline int txring_to_priority(struct b43legacy_dmaring *ring)
{
static const u8 idx_to_prio[] =
{ 3, 2, 1, 0, 4, 5, };
/*FIXME: have only one queue, for now */
return 0;
return idx_to_prio[ring->index];
}
static u16 b43legacy_dmacontroller_base(enum b43legacy_dmatype type,
int controller_idx)
{
static const u16 map64[] = {
B43legacy_MMIO_DMA64_BASE0,
B43legacy_MMIO_DMA64_BASE1,
B43legacy_MMIO_DMA64_BASE2,
B43legacy_MMIO_DMA64_BASE3,
B43legacy_MMIO_DMA64_BASE4,
B43legacy_MMIO_DMA64_BASE5,
};
static const u16 map32[] = {
B43legacy_MMIO_DMA32_BASE0,
B43legacy_MMIO_DMA32_BASE1,
B43legacy_MMIO_DMA32_BASE2,
B43legacy_MMIO_DMA32_BASE3,
B43legacy_MMIO_DMA32_BASE4,
B43legacy_MMIO_DMA32_BASE5,
};
if (type == B43legacy_DMA_64BIT) {
B43legacy_WARN_ON(!(controller_idx >= 0 &&
controller_idx < ARRAY_SIZE(map64)));
return map64[controller_idx];
}
B43legacy_WARN_ON(!(controller_idx >= 0 &&
controller_idx < ARRAY_SIZE(map32)));
return map32[controller_idx];
}
static inline
dma_addr_t map_descbuffer(struct b43legacy_dmaring *ring,
unsigned char *buf,
size_t len,
int tx)
{
dma_addr_t dmaaddr;
if (tx)
dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
buf, len,
DMA_TO_DEVICE);
else
dmaaddr = dma_map_single(ring->dev->dev->dma_dev,
buf, len,
DMA_FROM_DEVICE);
return dmaaddr;
}
static inline
void unmap_descbuffer(struct b43legacy_dmaring *ring,
dma_addr_t addr,
size_t len,
int tx)
{
if (tx)
dma_unmap_single(ring->dev->dev->dma_dev,
addr, len,
DMA_TO_DEVICE);
else
dma_unmap_single(ring->dev->dev->dma_dev,
addr, len,
DMA_FROM_DEVICE);
}
static inline
void sync_descbuffer_for_cpu(struct b43legacy_dmaring *ring,
dma_addr_t addr,
size_t len)
{
B43legacy_WARN_ON(ring->tx);
dma_sync_single_for_cpu(ring->dev->dev->dma_dev,
addr, len, DMA_FROM_DEVICE);
}
static inline
void sync_descbuffer_for_device(struct b43legacy_dmaring *ring,
dma_addr_t addr,
size_t len)
{
B43legacy_WARN_ON(ring->tx);
dma_sync_single_for_device(ring->dev->dev->dma_dev,
addr, len, DMA_FROM_DEVICE);
}
static inline
void free_descriptor_buffer(struct b43legacy_dmaring *ring,
struct b43legacy_dmadesc_meta *meta,
int irq_context)
{
if (meta->skb) {
if (irq_context)
dev_kfree_skb_irq(meta->skb);
else
dev_kfree_skb(meta->skb);
meta->skb = NULL;
}
}
static int alloc_ringmemory(struct b43legacy_dmaring *ring)
{
/* GFP flags must match the flags in free_ringmemory()! */
ring->descbase = dma_alloc_coherent(ring->dev->dev->dma_dev,
B43legacy_DMA_RINGMEMSIZE,
&(ring->dmabase),
GFP_KERNEL);
if (!ring->descbase) {
b43legacyerr(ring->dev->wl, "DMA ringmemory allocation"
" failed\n");
return -ENOMEM;
}
memset(ring->descbase, 0, B43legacy_DMA_RINGMEMSIZE);
return 0;
}
static void free_ringmemory(struct b43legacy_dmaring *ring)
{
dma_free_coherent(ring->dev->dev->dma_dev, B43legacy_DMA_RINGMEMSIZE,
ring->descbase, ring->dmabase);
}
/* Reset the RX DMA channel */
static int b43legacy_dmacontroller_rx_reset(struct b43legacy_wldev *dev,
u16 mmio_base,
enum b43legacy_dmatype type)
{
int i;
u32 value;
u16 offset;
might_sleep();
offset = (type == B43legacy_DMA_64BIT) ?
B43legacy_DMA64_RXCTL : B43legacy_DMA32_RXCTL;
b43legacy_write32(dev, mmio_base + offset, 0);
for (i = 0; i < 10; i++) {
offset = (type == B43legacy_DMA_64BIT) ?
B43legacy_DMA64_RXSTATUS : B43legacy_DMA32_RXSTATUS;
value = b43legacy_read32(dev, mmio_base + offset);
if (type == B43legacy_DMA_64BIT) {
value &= B43legacy_DMA64_RXSTAT;
if (value == B43legacy_DMA64_RXSTAT_DISABLED) {
i = -1;
break;
}
} else {
value &= B43legacy_DMA32_RXSTATE;
if (value == B43legacy_DMA32_RXSTAT_DISABLED) {
i = -1;
break;
}
}
msleep(1);
}
if (i != -1) {
b43legacyerr(dev->wl, "DMA RX reset timed out\n");
return -ENODEV;
}
return 0;
}
/* Reset the RX DMA channel */
static int b43legacy_dmacontroller_tx_reset(struct b43legacy_wldev *dev,
u16 mmio_base,
enum b43legacy_dmatype type)
{
int i;
u32 value;
u16 offset;
might_sleep();
for (i = 0; i < 10; i++) {
offset = (type == B43legacy_DMA_64BIT) ?
B43legacy_DMA64_TXSTATUS : B43legacy_DMA32_TXSTATUS;
value = b43legacy_read32(dev, mmio_base + offset);
if (type == B43legacy_DMA_64BIT) {
value &= B43legacy_DMA64_TXSTAT;
if (value == B43legacy_DMA64_TXSTAT_DISABLED ||
value == B43legacy_DMA64_TXSTAT_IDLEWAIT ||
value == B43legacy_DMA64_TXSTAT_STOPPED)
break;
} else {
value &= B43legacy_DMA32_TXSTATE;
if (value == B43legacy_DMA32_TXSTAT_DISABLED ||
value == B43legacy_DMA32_TXSTAT_IDLEWAIT ||
value == B43legacy_DMA32_TXSTAT_STOPPED)
break;
}
msleep(1);
}
offset = (type == B43legacy_DMA_64BIT) ? B43legacy_DMA64_TXCTL :
B43legacy_DMA32_TXCTL;
b43legacy_write32(dev, mmio_base + offset, 0);
for (i = 0; i < 10; i++) {
offset = (type == B43legacy_DMA_64BIT) ?
B43legacy_DMA64_TXSTATUS : B43legacy_DMA32_TXSTATUS;
value = b43legacy_read32(dev, mmio_base + offset);
if (type == B43legacy_DMA_64BIT) {
value &= B43legacy_DMA64_TXSTAT;
if (value == B43legacy_DMA64_TXSTAT_DISABLED) {
i = -1;
break;
}
} else {
value &= B43legacy_DMA32_TXSTATE;
if (value == B43legacy_DMA32_TXSTAT_DISABLED) {
i = -1;
break;
}
}
msleep(1);
}
if (i != -1) {
b43legacyerr(dev->wl, "DMA TX reset timed out\n");
return -ENODEV;
}
/* ensure the reset is completed. */
msleep(1);
return 0;
}
/* Check if a DMA mapping address is invalid. */
static bool b43legacy_dma_mapping_error(struct b43legacy_dmaring *ring,
dma_addr_t addr,
size_t buffersize,
bool dma_to_device)
{
if (unlikely(dma_mapping_error(ring->dev->dev->dma_dev, addr)))
return 1;
switch (ring->type) {
case B43legacy_DMA_30BIT:
if ((u64)addr + buffersize > (1ULL << 30))
goto address_error;
break;
case B43legacy_DMA_32BIT:
if ((u64)addr + buffersize > (1ULL << 32))
goto address_error;
break;
case B43legacy_DMA_64BIT:
/* Currently we can't have addresses beyond 64 bits in the kernel. */
break;
}
/* The address is OK. */
return 0;
address_error:
/* We can't support this address. Unmap it again. */
unmap_descbuffer(ring, addr, buffersize, dma_to_device);
return 1;
}
static int setup_rx_descbuffer(struct b43legacy_dmaring *ring,
struct b43legacy_dmadesc_generic *desc,
struct b43legacy_dmadesc_meta *meta,
gfp_t gfp_flags)
{
struct b43legacy_rxhdr_fw3 *rxhdr;
struct b43legacy_hwtxstatus *txstat;
dma_addr_t dmaaddr;
struct sk_buff *skb;
B43legacy_WARN_ON(ring->tx);
skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
if (unlikely(!skb))
return -ENOMEM;
dmaaddr = map_descbuffer(ring, skb->data,
ring->rx_buffersize, 0);
if (b43legacy_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
/* ugh. try to realloc in zone_dma */
gfp_flags |= GFP_DMA;
dev_kfree_skb_any(skb);
skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
if (unlikely(!skb))
return -ENOMEM;
dmaaddr = map_descbuffer(ring, skb->data,
ring->rx_buffersize, 0);
}
if (b43legacy_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
dev_kfree_skb_any(skb);
return -EIO;
}
meta->skb = skb;
meta->dmaaddr = dmaaddr;
ring->ops->fill_descriptor(ring, desc, dmaaddr,
ring->rx_buffersize, 0, 0, 0);
rxhdr = (struct b43legacy_rxhdr_fw3 *)(skb->data);
rxhdr->frame_len = 0;
txstat = (struct b43legacy_hwtxstatus *)(skb->data);
txstat->cookie = 0;
return 0;
}
/* Allocate the initial descbuffers.
* This is used for an RX ring only.
*/
static int alloc_initial_descbuffers(struct b43legacy_dmaring *ring)
{
int i;
int err = -ENOMEM;
struct b43legacy_dmadesc_generic *desc;
struct b43legacy_dmadesc_meta *meta;
for (i = 0; i < ring->nr_slots; i++) {
desc = ring->ops->idx2desc(ring, i, &meta);
err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
if (err) {
b43legacyerr(ring->dev->wl,
"Failed to allocate initial descbuffers\n");
goto err_unwind;
}
}
mb(); /* all descbuffer setup before next line */
ring->used_slots = ring->nr_slots;
err = 0;
out:
return err;
err_unwind:
for (i--; i >= 0; i--) {
desc = ring->ops->idx2desc(ring, i, &meta);
unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
dev_kfree_skb(meta->skb);
}
goto out;
}
/* Do initial setup of the DMA controller.
* Reset the controller, write the ring busaddress
* and switch the "enable" bit on.
*/
static int dmacontroller_setup(struct b43legacy_dmaring *ring)
{
int err = 0;
u32 value;
u32 addrext;
u32 trans = ssb_dma_translation(ring->dev->dev);
if (ring->tx) {
if (ring->type == B43legacy_DMA_64BIT) {
u64 ringbase = (u64)(ring->dmabase);
addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
>> SSB_DMA_TRANSLATION_SHIFT;
value = B43legacy_DMA64_TXENABLE;
value |= (addrext << B43legacy_DMA64_TXADDREXT_SHIFT)
& B43legacy_DMA64_TXADDREXT_MASK;
b43legacy_dma_write(ring, B43legacy_DMA64_TXCTL,
value);
b43legacy_dma_write(ring, B43legacy_DMA64_TXRINGLO,
(ringbase & 0xFFFFFFFF));
b43legacy_dma_write(ring, B43legacy_DMA64_TXRINGHI,
((ringbase >> 32)
& ~SSB_DMA_TRANSLATION_MASK)
| trans);
} else {
u32 ringbase = (u32)(ring->dmabase);
addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
>> SSB_DMA_TRANSLATION_SHIFT;
value = B43legacy_DMA32_TXENABLE;
value |= (addrext << B43legacy_DMA32_TXADDREXT_SHIFT)
& B43legacy_DMA32_TXADDREXT_MASK;
b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL,
value);
b43legacy_dma_write(ring, B43legacy_DMA32_TXRING,
(ringbase &
~SSB_DMA_TRANSLATION_MASK)
| trans);
}
} else {
err = alloc_initial_descbuffers(ring);
if (err)
goto out;
if (ring->type == B43legacy_DMA_64BIT) {
u64 ringbase = (u64)(ring->dmabase);
addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
>> SSB_DMA_TRANSLATION_SHIFT;
value = (ring->frameoffset <<
B43legacy_DMA64_RXFROFF_SHIFT);
value |= B43legacy_DMA64_RXENABLE;
value |= (addrext << B43legacy_DMA64_RXADDREXT_SHIFT)
& B43legacy_DMA64_RXADDREXT_MASK;
b43legacy_dma_write(ring, B43legacy_DMA64_RXCTL,
value);
b43legacy_dma_write(ring, B43legacy_DMA64_RXRINGLO,
(ringbase & 0xFFFFFFFF));
b43legacy_dma_write(ring, B43legacy_DMA64_RXRINGHI,
((ringbase >> 32) &
~SSB_DMA_TRANSLATION_MASK) |
trans);
b43legacy_dma_write(ring, B43legacy_DMA64_RXINDEX,
200);
} else {
u32 ringbase = (u32)(ring->dmabase);
addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
>> SSB_DMA_TRANSLATION_SHIFT;
value = (ring->frameoffset <<
B43legacy_DMA32_RXFROFF_SHIFT);
value |= B43legacy_DMA32_RXENABLE;
value |= (addrext <<
B43legacy_DMA32_RXADDREXT_SHIFT)
& B43legacy_DMA32_RXADDREXT_MASK;
b43legacy_dma_write(ring, B43legacy_DMA32_RXCTL,
value);
b43legacy_dma_write(ring, B43legacy_DMA32_RXRING,
(ringbase &
~SSB_DMA_TRANSLATION_MASK)
| trans);
b43legacy_dma_write(ring, B43legacy_DMA32_RXINDEX,
200);
}
}
out:
return err;
}
/* Shutdown the DMA controller. */
static void dmacontroller_cleanup(struct b43legacy_dmaring *ring)
{
if (ring->tx) {
b43legacy_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
ring->type);
if (ring->type == B43legacy_DMA_64BIT) {
b43legacy_dma_write(ring, B43legacy_DMA64_TXRINGLO, 0);
b43legacy_dma_write(ring, B43legacy_DMA64_TXRINGHI, 0);
} else
b43legacy_dma_write(ring, B43legacy_DMA32_TXRING, 0);
} else {
b43legacy_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
ring->type);
if (ring->type == B43legacy_DMA_64BIT) {
b43legacy_dma_write(ring, B43legacy_DMA64_RXRINGLO, 0);
b43legacy_dma_write(ring, B43legacy_DMA64_RXRINGHI, 0);
} else
b43legacy_dma_write(ring, B43legacy_DMA32_RXRING, 0);
}
}
static void free_all_descbuffers(struct b43legacy_dmaring *ring)
{
struct b43legacy_dmadesc_generic *desc;
struct b43legacy_dmadesc_meta *meta;
int i;
if (!ring->used_slots)
return;
for (i = 0; i < ring->nr_slots; i++) {
desc = ring->ops->idx2desc(ring, i, &meta);
if (!meta->skb) {
B43legacy_WARN_ON(!ring->tx);
continue;
}
if (ring->tx)
unmap_descbuffer(ring, meta->dmaaddr,
meta->skb->len, 1);
else
unmap_descbuffer(ring, meta->dmaaddr,
ring->rx_buffersize, 0);
free_descriptor_buffer(ring, meta, 0);
}
}
static u64 supported_dma_mask(struct b43legacy_wldev *dev)
{
u32 tmp;
u16 mmio_base;
tmp = b43legacy_read32(dev, SSB_TMSHIGH);
if (tmp & SSB_TMSHIGH_DMA64)
return DMA_BIT_MASK(64);
mmio_base = b43legacy_dmacontroller_base(0, 0);
b43legacy_write32(dev,
mmio_base + B43legacy_DMA32_TXCTL,
B43legacy_DMA32_TXADDREXT_MASK);
tmp = b43legacy_read32(dev, mmio_base +
B43legacy_DMA32_TXCTL);
if (tmp & B43legacy_DMA32_TXADDREXT_MASK)
return DMA_BIT_MASK(32);
return DMA_BIT_MASK(30);
}
static enum b43legacy_dmatype dma_mask_to_engine_type(u64 dmamask)
{
if (dmamask == DMA_BIT_MASK(30))
return B43legacy_DMA_30BIT;
if (dmamask == DMA_BIT_MASK(32))
return B43legacy_DMA_32BIT;
if (dmamask == DMA_BIT_MASK(64))
return B43legacy_DMA_64BIT;
B43legacy_WARN_ON(1);
return B43legacy_DMA_30BIT;
}
/* Main initialization function. */
static
struct b43legacy_dmaring *b43legacy_setup_dmaring(struct b43legacy_wldev *dev,
int controller_index,
int for_tx,
enum b43legacy_dmatype type)
{
struct b43legacy_dmaring *ring;
int err;
int nr_slots;
dma_addr_t dma_test;
ring = kzalloc(sizeof(*ring), GFP_KERNEL);
if (!ring)
goto out;
ring->type = type;
ring->dev = dev;
nr_slots = B43legacy_RXRING_SLOTS;
if (for_tx)
nr_slots = B43legacy_TXRING_SLOTS;
ring->meta = kcalloc(nr_slots, sizeof(struct b43legacy_dmadesc_meta),
GFP_KERNEL);
if (!ring->meta)
goto err_kfree_ring;
if (for_tx) {
ring->txhdr_cache = kcalloc(nr_slots,
sizeof(struct b43legacy_txhdr_fw3),
GFP_KERNEL);
if (!ring->txhdr_cache)
goto err_kfree_meta;
/* test for ability to dma to txhdr_cache */
dma_test = dma_map_single(dev->dev->dma_dev, ring->txhdr_cache,
sizeof(struct b43legacy_txhdr_fw3),
DMA_TO_DEVICE);
if (b43legacy_dma_mapping_error(ring, dma_test,
sizeof(struct b43legacy_txhdr_fw3), 1)) {
/* ugh realloc */
kfree(ring->txhdr_cache);
ring->txhdr_cache = kcalloc(nr_slots,
sizeof(struct b43legacy_txhdr_fw3),
GFP_KERNEL | GFP_DMA);
if (!ring->txhdr_cache)
goto err_kfree_meta;
dma_test = dma_map_single(dev->dev->dma_dev,
ring->txhdr_cache,
sizeof(struct b43legacy_txhdr_fw3),
DMA_TO_DEVICE);
if (b43legacy_dma_mapping_error(ring, dma_test,
sizeof(struct b43legacy_txhdr_fw3), 1))
goto err_kfree_txhdr_cache;
}
dma_unmap_single(dev->dev->dma_dev, dma_test,
sizeof(struct b43legacy_txhdr_fw3),
DMA_TO_DEVICE);
}
ring->nr_slots = nr_slots;
ring->mmio_base = b43legacy_dmacontroller_base(type, controller_index);
ring->index = controller_index;
if (type == B43legacy_DMA_64BIT)
ring->ops = &dma64_ops;
else
ring->ops = &dma32_ops;
if (for_tx) {
ring->tx = 1;
ring->current_slot = -1;
} else {
if (ring->index == 0) {
ring->rx_buffersize = B43legacy_DMA0_RX_BUFFERSIZE;
ring->frameoffset = B43legacy_DMA0_RX_FRAMEOFFSET;
} else if (ring->index == 3) {
ring->rx_buffersize = B43legacy_DMA3_RX_BUFFERSIZE;
ring->frameoffset = B43legacy_DMA3_RX_FRAMEOFFSET;
} else
B43legacy_WARN_ON(1);
}
spin_lock_init(&ring->lock);
#ifdef CONFIG_B43LEGACY_DEBUG
ring->last_injected_overflow = jiffies;
#endif
err = alloc_ringmemory(ring);
if (err)
goto err_kfree_txhdr_cache;
err = dmacontroller_setup(ring);
if (err)
goto err_free_ringmemory;
out:
return ring;
err_free_ringmemory:
free_ringmemory(ring);
err_kfree_txhdr_cache:
kfree(ring->txhdr_cache);
err_kfree_meta:
kfree(ring->meta);
err_kfree_ring:
kfree(ring);
ring = NULL;
goto out;
}
/* Main cleanup function. */
static void b43legacy_destroy_dmaring(struct b43legacy_dmaring *ring)
{
if (!ring)
return;
b43legacydbg(ring->dev->wl, "DMA-%u 0x%04X (%s) max used slots:"
" %d/%d\n", (unsigned int)(ring->type), ring->mmio_base,
(ring->tx) ? "TX" : "RX", ring->max_used_slots,
ring->nr_slots);
/* Device IRQs are disabled prior entering this function,
* so no need to take care of concurrency with rx handler stuff.
*/
dmacontroller_cleanup(ring);
free_all_descbuffers(ring);
free_ringmemory(ring);