Unicycle-Processor-RISC-V-RV32I

This is a SystemVerilog implementation of the Unicycle RISC-V RV32I processor and this was the final project for Computer Architecture class.

Graphic:

Algorithm used to test the processor (C++)

Algorithm used to test the processor (Assembly)

Algorithm used to test the processor (Hexadecimal)

You can view and run this design in EDAplayground: https://www.edaplayground.com/x/MjrJ

Arquitectura de Computadores, Profesor: Jose Jaramillo, Universidad Tecnológica de Pereira

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
ALU.sv		ALU.sv
BranchUnit.sv		BranchUnit.sv
ControlUnit.sv		ControlUnit.sv
DataMemory.sv		DataMemory.sv
ImmGen.sv		ImmGen.sv
InstructionMemory.sv		InstructionMemory.sv
Instructions.txt		Instructions.txt
LICENSE		LICENSE
Memory.txt		Memory.txt
MuxALUASrc.sv		MuxALUASrc.sv
MuxALUBSrc.sv		MuxALUBSrc.sv
MuxNextPCSrc.sv		MuxNextPCSrc.sv
MuxRUDataWrSrc.sv		MuxRUDataWrSrc.sv
ProgramCounter.sv		ProgramCounter.sv
README.md		README.md
Registers.txt		Registers.txt
RegistersUnit.sv		RegistersUnit.sv
Sum4.sv		Sum4.sv
design.sv		design.sv
testbench.sv		testbench.sv

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