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rrae.sch
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rrae.sch
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EESchema Schematic File Version 2 date 10/16/2011 9:20:50 PM
LIBS:power
LIBS:device
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:74xx
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:special
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:rrae
LIBS:rrae-cache
EELAYER 25 0
EELAYER END
$Descr A4 11700 8267
encoding utf-8
Sheet 1 9
Title ""
Date "16 oct 2011"
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Sheet
S 1850 4450 3400 2550
U 4E98DB6D
F0 "devBoardPinout.sch" 60
F1 "Dev Board.sch" 60
$EndSheet
Wire Wire Line
3150 3500 3050 3500
Wire Wire Line
3050 3500 3050 1100
Wire Wire Line
3050 1100 1650 1100
Wire Wire Line
5500 3400 4200 3400
Wire Wire Line
4200 3400 4200 3600
Wire Wire Line
4200 3600 4050 3600
Wire Wire Line
5500 3200 3150 3200
Wire Wire Line
3150 3200 3150 2350
Wire Wire Line
3150 2350 1650 2350
Wire Wire Line
5500 3000 3350 3000
Wire Wire Line
3350 3000 3350 2150
Wire Wire Line
3350 2150 1650 2150
Wire Wire Line
5500 2800 3550 2800
Wire Wire Line
3550 2800 3550 1900
Wire Wire Line
3550 1900 1650 1900
Wire Wire Line
1650 1500 3850 1500
Wire Wire Line
3850 1500 3850 2500
Wire Wire Line
3850 2500 5500 2500
Wire Wire Line
1650 1400 3950 1400
Wire Wire Line
3950 1400 3950 2400
Wire Wire Line
3950 2400 5500 2400
Wire Wire Line
1650 1600 3750 1600
Wire Wire Line
3750 1600 3750 2600
Wire Wire Line
3750 2600 5500 2600
Wire Wire Line
1650 1700 3650 1700
Wire Wire Line
3650 1700 3650 2700
Wire Wire Line
3650 2700 5500 2700
Wire Wire Line
5500 2900 3450 2900
Wire Wire Line
3450 2900 3450 2000
Wire Wire Line
3450 2000 1650 2000
Wire Wire Line
5500 3100 3250 3100
Wire Wire Line
3250 3100 3250 2250
Wire Wire Line
3250 2250 1650 2250
Wire Wire Line
4050 3700 4300 3700
Wire Wire Line
4300 3700 4300 3500
Wire Wire Line
4300 3500 5500 3500
$Sheet
S 3150 3350 900 450
U 4E815C62
F0 "Reset Circuit" 60
F1 "reset.sch" 60
F2 "ResetInput" I R 4050 3600 60
F3 "SoftResetOutput" I L 3150 3500 60
F4 "MasterReset" I R 4050 3700 60
$EndSheet
$Sheet
S 750 850 900 1550
U 4E7A8C23
F0 "Phy Trans" 60
F1 "phyTrans.sch" 60
F2 "CRS_DV" I R 1650 1700 60
F3 "RXD1" I R 1650 2000 60
F4 "RXD0" I R 1650 1900 60
F5 "TXD1" I R 1650 2350 60
F6 "TXD0" I R 1650 2250 60
F7 "TXEN" I R 1650 2150 60
F8 "RST" I R 1650 1100 60
F9 "RMII_CLK" I R 1650 1400 60
F10 "MDC" I R 1650 1500 60
F11 "MDIO" B R 1650 1600 60
F12 "INTRP" O R 1650 1300 60
$EndSheet
$Sheet
S 5500 2300 3050 2950
U 4E7DF058
F0 "STM32F207" 60
F1 "processor.sch" 60
F2 "PHY_REF_CLK" I L 5500 2400 60
F3 "PHY_MDIO" I L 5500 2600 60
F4 "PHY_MDC" I L 5500 2500 60
F5 "PHY_CRS_DV" I L 5500 2700 60
F6 "PHY_TxEn" I L 5500 3000 60
F7 "PHY_RXD1" I L 5500 2900 60
F8 "PHY_RXD0" I L 5500 2800 60
F9 "PHY_TXD1" I L 5500 3200 60
F10 "PHY_TXD0" I L 5500 3100 60
F11 "SoftReset" I L 5500 3400 60
F12 "Reset" I L 5500 3500 60
$EndSheet
$EndSCHEMATC