OPL3 FM Synthesizer Synthesis and Simulation Issues

[TarikHamedovic]

Verilator Simulation Warnings

While running the synthesis for the OPL3 FM Synthesizer, I encountered several warnings related to the RTL code. Although the synthesis completes successfully due to the Makefile being configured to ignore these warnings, it's crucial to address these warnings for cleaner code and synthesis. Other tools like yosys might treat these warnings as errors, potentially causing issues in the future. To run the Makefile go to 2.sim/ folder and run make. The following flags are currently set to ignore warnings in the Makefile:

VERILATOR_FLAGS += -Wno-TIMESCALEMOD
VERILATOR_FLAGS += -Wno-LITENDIAN
VERILATOR_FLAGS += -Wno-WIDTH
VERILATOR_FLAGS += -Wno-UNOPTFLAT
VERILATOR_FLAGS += -Wno-CASEINCOMPLETE
VERILATOR_FLAGS += -Wno-UNDRIVEN
VERILATOR_FLAGS += -Wno-VARHIDDEN
VERILATOR_FLAGS += -Wno-IMPORTSTAR
VERILATOR_FLAGS += -Wno-REALCVT
VERILATOR_FLAGS += -Wno-UNUSED

By removing the flags one by one you can see for your self the warnings that Verilator has such as:

%Warning-WIDTH: /home/user/openCologne/4.Advanced--4--Yamaha-OPL3-FM-Synth/3.build/../1.hw/modules/channels/src/channels.sv:212:71: Bit extraction of var[5:0] requires 3 bit index, not 4 bits.
                                                                                                                                  : ... In instance opl3.channels
  212 |                     signals.add_c = !is_new || (chc && !connection_sel[self.channel_num]);
      |                                                                       ^
%Warning-WIDTH: /home/user/openCologne/4.Advanced--4--Yamaha-OPL3-FM-Synth/3.build/../1.hw/modules/channels/src/channels.sv:213:71: Bit extraction of var[5:0] requires 3 bit index, not 4 bits.
                                                                                                                                  : ... In instance opl3.channels
  213 |                     signals.add_d = !is_new || (chd && !connection_sel[self.channel_num]);
      |                                                                       ^
%Warning-WIDTH: /home/user/openCologne/4.Advanced--4--Yamaha-OPL3-FM-Synth/3.build/../1.hw/modules/channels/src/channels.sv:230:90: Operator ADD expects 20 bits on the RHS, but RHS's SEL generates 14 bits.
                                                                                                                                  : ... In instance opl3.channels
  230 |             'b01, 'b10: next_self.channel_l_acc_pre_clamp = self.channel_l_acc_pre_clamp + signals.channel_2_op;
      |                                                                                          ^
%Warning-WIDTH: /home/user/openCologne/4.Advanced--4--Yamaha-OPL3-FM-Synth/3.build/../1.hw/modules/channels/src/channels.sv:236:90: Operator ADD expects 20 bits on the RHS, but RHS's SEL generates 14 bits.
                                                                                                                                  : ... In instance opl3.channels
  236 |             'b01, 'b10: next_self.channel_r_acc_pre_clamp = self.channel_r_acc_pre_clamp + signals.channel_2_op;
      |                                                                                          ^

I won't list all the warnings here due to readabilty but there are 108 WIDTH warnings, 37 UNUSED warnings, and several minor warnings.

Cocotb Simulation Warnings

Running make in the 2.sim/cocoTB folder also results in warnings related to the RTL code:

/home/user/openCologne/4.Advanced--4--Yamaha-OPL3-FM-Synth/2.sim/cocotb/../../1.hw/modules/misc/src/mem_multi_bank.sv:73: warning: Port 3 (out) of pipeline_sr expects 3 bits, got 2.
/home/user/openCologne/4.Advanced--4--Yamaha-OPL3-FM-Synth/2.sim/cocotb/../../1.hw/modules/misc/src/mem_multi_bank.sv:73:        : Padding 1 high bits of the port.
/home/user/openCologne/4.Advanced--4--Yamaha-OPL3-FM-Synth/2.sim/cocotb/../../1.hw/modules/misc/src/mem_multi_bank.sv:123: error: Index bankb_p[2] is out of range.
/home/user/openCologne/4.Advanced--4--Yamaha-OPL3-FM-Synth/2.sim/cocotb/../../1.hw/modules/misc/src/mem_multi_bank.sv:73: warning: Port 3 (out) of pipeline_sr expects 3 bits, got 2.
/home/user/openCologne/4.Advanced--4--Yamaha-OPL3-FM-Synth/2.sim/cocotb/../../1.hw/modules/misc/src/mem_multi_bank.sv:73:        : Padding 1 high bits of the port.
/home/user/openCologne/4.Advanced--4--Yamaha-OPL3-FM-Synth/2.sim/cocotb/../../1.hw/modules/operator/src/phase_generator.sv:282: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
/home/user/openCologne/4.Advanced--4--Yamaha-OPL3-FM-Synth/2.sim/cocotb/../../1.hw/modules/operator/src/phase_generator.sv:302: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
/home/user/openCologne/4.Advanced--4--Yamaha-OPL3-FM-Synth/2.sim/cocotb/../../1.hw/modules/operator/src/phase_generator.sv:302: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
/home/user/openCologne/4.Advanced--4--Yamaha-OPL3-FM-Synth/2.sim/cocotb/../../1.hw/modules/operator/src/phase_generator.sv:314: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
/home/user/openCologne/4.Advanced--4--Yamaha-OPL3-FM-Synth/2.sim/cocotb/../../1.hw/modules/operator/src/phase_generator.sv:314: sorry: constant selects in always_* processes are not currently supported (all bits will be included).
/home/user/openCologne/4.Advanced--4--Yamaha-OPL3-FM-Synth/2.sim/cocotb/../../1.hw/modules/misc/src/mem_multi_bank.sv:73: warning: Port 3 (out) of pipeline_sr expects 3 bits, got 2.
/home/user/openCologne/4.Advanced--4--Yamaha-OPL3-FM-Synth/2.sim/cocotb/../../1.hw/modules/misc/src/mem_multi_bank.sv:73:        : Padding 1 high bits of the port.

And so on... As said I won't list all the listed warnings and errors.

[chili-chips-ba]

Hi @gtaylormb. This is essentially:

• standalone Verilator-based Linter for opl3_fpga RTL
• Icarus-based Linter for opl3_fpga RTL (within cocotb environment)

In a follow up to @hzeller recommendation, we are also planning to bring up Verible-based Linter for opl3_fpga RTL.

Please consider using these flows to make the opl3_fpga RTL even better than it already is.