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test1-2021-09-15.log
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test1-2021-09-15.log
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===-------------------------------------------------------------------------===
... Execution time report ...
===-------------------------------------------------------------------------===
Total Execution Time: 1.5595 seconds
----User Time---- ----Wall Time---- ----Name----
0.3382 ( 16.8%) 0.3382 ( 21.7%) FIR Parser
1.3434 ( 66.9%) 0.8944 ( 57.3%) 'firrtl.circuit' Pipeline
0.1655 ( 8.2%) 0.0914 ( 5.9%) 'firrtl.module' Pipeline
0.1358 ( 6.8%) 0.0705 ( 4.5%) CSE
0.0000 ( 0.0%) 0.0000 ( 0.0%) (A) DominanceInfo
0.0297 ( 1.5%) 0.0209 ( 1.3%) LowerCHIRRTL
0.0144 ( 0.7%) 0.0144 ( 0.9%) InferWidths
0.0595 ( 3.0%) 0.0595 ( 3.8%) InferResets
0.0028 ( 0.1%) 0.0028 ( 0.2%) (A) circt::firrtl::InstanceGraph
0.1354 ( 6.7%) 0.1354 ( 8.7%) LowerFIRRTLTypes
0.7658 ( 38.1%) 0.3909 ( 25.1%) 'firrtl.module' Pipeline
0.0990 ( 4.9%) 0.0534 ( 3.4%) ExpandWhens
0.6668 ( 33.2%) 0.3375 ( 21.6%) Canonicalizer
0.0264 ( 1.3%) 0.0264 ( 1.7%) Inliner
0.0359 ( 1.8%) 0.0359 ( 2.3%) IMConstProp
0.0004 ( 0.0%) 0.0004 ( 0.0%) (A) circt::firrtl::InstanceGraph
0.0000 ( 0.0%) 0.0000 ( 0.0%) BlackBoxReader
0.1400 ( 7.0%) 0.1400 ( 9.0%) 'firrtl.module' Pipeline
0.1400 ( 7.0%) 0.1400 ( 9.0%) Canonicalizer
0.1069 ( 5.3%) 0.1069 ( 6.9%) LowerFIRRTLToHW
0.0000 ( 0.0%) 0.0000 ( 0.0%) HWMemSimImpl
0.1251 ( 6.2%) 0.1251 ( 8.0%) 'hw.module' Pipeline
0.0013 ( 0.1%) 0.0013 ( 0.1%) HWCleanup
0.0337 ( 1.7%) 0.0337 ( 2.2%) CSE
0.0000 ( 0.0%) 0.0000 ( 0.0%) (A) DominanceInfo
0.0891 ( 4.4%) 0.0891 ( 5.7%) Canonicalizer
0.0010 ( 0.1%) 0.0010 ( 0.1%) HWLegalizeModules
0.0093 ( 0.5%) 0.0093 ( 0.6%) HWLegalizeNames
0.0193 ( 1.0%) 0.0193 ( 1.2%) 'hw.module' Pipeline
0.0193 ( 1.0%) 0.0193 ( 1.2%) PrettifyVerilog
0.0652 ( 3.2%) 0.0652 ( 4.2%) ExportVerilog emission
0.0010 ( 0.1%) 0.0010 ( 0.1%) Rest
2.0086 (100.0%) 1.5595 (100.0%) Total
{
totalTime: 1.57,
maxMemory: 68186112
}