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BlockRam write logic is clumsy to say the least #42
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The Of course, the limitations of existing HDLs shouldn't restrict the CLaSH prelude :-) |
Cool thing, I can wait :-) |
Yeah, me neither. Too bad GHC 8 is riddled with bugs introduced by both the type-in-kind and visible type applications patches. I think it'll be at least a month before GHC 8 can be released. |
If your changing blockRAM's, is there any reason their isn't a true dual ported version? I know Xilinx supports this, and I thought Altera did as well. |
Indeed, both Altera and Xilinx support true dual ported blockRam's. However, I seem to remember that they have different recommended HDL coding styles for true dual ported blockRam inference. @polygonhell: are you working with Xilinx or Altera? if you're working with Xilinx could you give me the primitive you created? I'll test it on altera then. |
I'm working with a couple of different Xilinx parts, I don't have an altera part to test, but I'm pretty sure I more or less copied the pattern from a Blog that claimed BlockRAM would be inferred on both. |
@polygonhell I'm confused by your Haskell model and the corresponding VHDL. If I read your Haskell model, it seems that, when Am I missing something? |
Your correct that's an error, in my case I actually don't care what dout is when wrE is true, but both models ought to at least agree. I can take a look once I get back from my current business trip. |
I apologize for this taking as long as it has. I think I've fixed the semantics issue in the blockRAM, the semantics are now write first, which is what the haskell was doing. This is the synthesis report I get from ISE, I'll check it on Vivado later. Synthesizing (advanced) Unit <Main_dpRamFilezm_3>. |
It appears to be correctly inferred in Vivado, I'd need to build a more thorough test to be sure, unfortunately the reports it produces are a lot harder to decode, it's certainly adding BlockRAM to the design and it's generating a Bit file, and it appears to have correctly inferred write first. |
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(Block)Ram write logic involves 3 distinct signals which are semantically coupled. Why not also represent them together? I came up with this adapter that consolidates the write logic to a
Maybe (addr, dta)
:This invites the whole zoo of utilities dealing with
Maybe
. Which is a good thing.What do you think? Would a pull request be accepted for inclusion? Maybe even make this the default interface to (block)Rams?
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