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ShadersD2D.h
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ShadersD2D.h
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#if 0
//
// FX Version: fx_4_0
// Child effect (requires effect pool): false
//
// 3 local buffer(s)
//
cbuffer cb0
{
float4 QuadDesc; // Offset: 0, size: 16
float4 TexCoords; // Offset: 16, size: 16
float4 MaskTexCoords; // Offset: 32, size: 16
}
cbuffer cb1
{
float4 BlurOffsetsH[3]; // Offset: 0, size: 48
float4 BlurOffsetsV[3]; // Offset: 48, size: 48
float4 BlurWeights[3]; // Offset: 96, size: 48
float4 ShadowColor; // Offset: 144, size: 16
}
cbuffer cb2
{
float3x3 DeviceSpaceToUserSpace; // Offset: 0, size: 44
float2 dimensions; // Offset: 48, size: 8
float3 diff; // Offset: 64, size: 12
float2 center1; // Offset: 80, size: 8
float A; // Offset: 88, size: 4
float radius1; // Offset: 92, size: 4
float sq_radius1; // Offset: 96, size: 4
}
//
// 10 local object(s)
//
Texture2D tex;
Texture2D mask;
SamplerState sSampler
{
Filter = uint(MIN_MAG_MIP_LINEAR /* 21 */);
Texture = tex;
AddressU = uint(CLAMP /* 3 */);
AddressV = uint(CLAMP /* 3 */);
};
SamplerState sWrapSampler
{
Filter = uint(MIN_MAG_MIP_LINEAR /* 21 */);
Texture = tex;
AddressU = uint(WRAP /* 1 */);
AddressV = uint(WRAP /* 1 */);
};
SamplerState sMirrorSampler
{
Filter = uint(MIN_MAG_MIP_LINEAR /* 21 */);
Texture = tex;
AddressU = uint(MIRROR /* 2 */);
AddressV = uint(MIRROR /* 2 */);
};
SamplerState sMaskSampler
{
Filter = uint(MIN_MAG_MIP_LINEAR /* 21 */);
Texture = mask;
AddressU = uint(CLAMP /* 3 */);
AddressV = uint(CLAMP /* 3 */);
};
SamplerState sShadowSampler
{
Filter = uint(MIN_MAG_MIP_LINEAR /* 21 */);
Texture = tex;
AddressU = uint(BORDER /* 4 */);
AddressV = uint(BORDER /* 4 */);
BorderColor = float4(0, 0, 0, 0);
};
RasterizerState TextureRast
{
ScissorEnable = bool(FALSE /* 0 */);
CullMode = uint(NONE /* 1 */);
};
BlendState ShadowBlendH
{
BlendEnable[0] = bool(FALSE /* 0 */);
RenderTargetWriteMask[0] = byte(0x0f);
};
BlendState ShadowBlendV
{
BlendEnable[0] = bool(TRUE /* 1 */);
SrcBlend[0] = uint(ONE /* 2 */);
DestBlend[0] = uint(INV_SRC_ALPHA /* 6 */);
BlendOp[0] = uint(ADD /* 1 */);
SrcBlendAlpha[0] = uint(ONE /* 2 */);
DestBlendAlpha[0] = uint(INV_SRC_ALPHA /* 6 */);
BlendOpAlpha[0] = uint(ADD /* 1 */);
RenderTargetWriteMask[0] = byte(0x0f);
};
//
// 4 technique(s)
//
technique10 SampleTexture
{
pass P0
{
RasterizerState = TextureRast;
VertexShader = asm {
//
// Generated by Microsoft (R) HLSL Shader Compiler 9.29.952.3111
//
//
// Buffer Definitions:
//
// cbuffer cb0
// {
//
// float4 QuadDesc; // Offset: 0 Size: 16
// float4 TexCoords; // Offset: 16 Size: 16
// float4 MaskTexCoords; // Offset: 32 Size: 16
//
// }
//
//
// Resource Bindings:
//
// Name Type Format Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// cb0 cbuffer NA NA 0 1
//
//
//
// Input signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------ ------
// POSITION 0 xyz 0 NONE float xy
//
//
// Output signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------ ------
// SV_Position 0 xyzw 0 POS float xyzw
// TEXCOORD 0 xy 1 NONE float xy
// TEXCOORD 1 zw 1 NONE float zw
//
//
// Constant buffer to DX9 shader constant mappings:
//
// Target Reg Buffer Start Reg # of Regs Data Conversion
// ---------- ------- --------- --------- ----------------------
// c1 cb0 0 3 ( FLT, FLT, FLT, FLT)
//
//
// Runtime generated constant mappings:
//
// Target Reg Constant Description
// ---------- --------------------------------------------------
// c0 Vertex Shader position offset
//
//
// Level9 shader bytecode:
//
vs_2_x
def c4, 0, 1, 0, 0
dcl_texcoord v0
mad oT0.xy, v0, c2.zwzw, c2
mad oT0.zw, v0.xyyx, c3.xywz, c3.xyyx
mad r0.xy, v0, c1.zwzw, c1
add oPos.xy, r0, c0
mov oPos.zw, c4.xyxy
// approximately 5 instruction slots used
vs_4_0
dcl_constantbuffer cb0[3], immediateIndexed
dcl_input v0.xy
dcl_output_siv o0.xyzw, position
dcl_output o1.xy
dcl_output o1.zw
mad o0.xy, v0.xyxx, cb0[0].zwzz, cb0[0].xyxx
mov o0.zw, l(0,0,0,1.000000)
mad o1.xy, v0.xyxx, cb0[1].zwzz, cb0[1].xyxx
mad o1.zw, v0.xxxy, cb0[2].zzzw, cb0[2].xxxy
ret
// Approximately 5 instruction slots used
};
GeometryShader = NULL;
PixelShader = asm {
//
// Generated by Microsoft (R) HLSL Shader Compiler 9.29.952.3111
//
//
// Resource Bindings:
//
// Name Type Format Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// sSampler sampler NA NA 0 1
// tex texture float4 2d 0 1
//
//
//
// Input signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------ ------
// SV_Position 0 xyzw 0 POS float
// TEXCOORD 0 xy 1 NONE float xy
// TEXCOORD 1 zw 1 NONE float
//
//
// Output signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------ ------
// SV_Target 0 xyzw 0 TARGET float xyzw
//
//
// Sampler/Resource to DX9 shader sampler mappings:
//
// Target Sampler Source Sampler Source Resource
// -------------- --------------- ----------------
// s0 s0 t0
//
//
// Level9 shader bytecode:
//
ps_2_x
dcl t0
dcl_2d s0
texld r0, t0, s0
mov oC0, r0
// approximately 2 instruction slots used (1 texture, 1 arithmetic)
ps_4_0
dcl_sampler s0, mode_default
dcl_resource_texture2d (float,float,float,float) t0
dcl_input_ps linear v1.xy
dcl_output o0.xyzw
sample o0.xyzw, v1.xyxx, t0.xyzw, s0
ret
// Approximately 2 instruction slots used
};
}
}
technique10 SampleRadialGradient
{
pass APos
{
RasterizerState = TextureRast;
VertexShader = asm {
//
// Generated by Microsoft (R) HLSL Shader Compiler 9.29.952.3111
//
//
// Buffer Definitions:
//
// cbuffer cb0
// {
//
// float4 QuadDesc; // Offset: 0 Size: 16
// float4 TexCoords; // Offset: 16 Size: 16 [unused]
// float4 MaskTexCoords; // Offset: 32 Size: 16
//
// }
//
// cbuffer cb2
// {
//
// float3x3 DeviceSpaceToUserSpace; // Offset: 0 Size: 44
// float2 dimensions; // Offset: 48 Size: 8
// float3 diff; // Offset: 64 Size: 12 [unused]
// float2 center1; // Offset: 80 Size: 8 [unused]
// float A; // Offset: 88 Size: 4 [unused]
// float radius1; // Offset: 92 Size: 4 [unused]
// float sq_radius1; // Offset: 96 Size: 4 [unused]
//
// }
//
//
// Resource Bindings:
//
// Name Type Format Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// cb0 cbuffer NA NA 0 1
// cb2 cbuffer NA NA 1 1
//
//
//
// Input signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------ ------
// POSITION 0 xyz 0 NONE float xy
//
//
// Output signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------ ------
// SV_Position 0 xyzw 0 POS float xyzw
// TEXCOORD 0 xy 1 NONE float xy
// TEXCOORD 1 zw 1 NONE float zw
//
//
// Constant buffer to DX9 shader constant mappings:
//
// Target Reg Buffer Start Reg # of Regs Data Conversion
// ---------- ------- --------- --------- ----------------------
// c1 cb0 0 1 ( FLT, FLT, FLT, FLT)
// c2 cb0 2 1 ( FLT, FLT, FLT, FLT)
// c3 cb1 0 2 ( FLT, FLT, FLT, FLT)
// c5 cb1 3 1 ( FLT, FLT, FLT, FLT)
//
//
// Runtime generated constant mappings:
//
// Target Reg Constant Description
// ---------- --------------------------------------------------
// c0 Vertex Shader position offset
//
//
// Level9 shader bytecode:
//
vs_2_x
def c6, 1, 0.5, 0, 0
dcl_texcoord v0
mad oT0.xy, v0, c2.zwzw, c2
mad r0.xy, v0, c1.zwzw, c1
add r0.z, r0.x, c6.x
mul r0.z, r0.z, c5.x
mul r1.x, r0.z, c6.y
add r0.z, -r0.y, c6.x
add oPos.xy, r0, c0
mul r0.x, r0.z, c5.y
mul r1.y, r0.x, c6.y
mov r1.z, c6.x
dp3 oT0.w, r1, c3
dp3 oT0.z, r1, c4
mov oPos.zw, c6.xyzx
// approximately 13 instruction slots used
vs_4_0
dcl_constantbuffer cb0[3], immediateIndexed
dcl_constantbuffer cb1[4], immediateIndexed
dcl_input v0.xy
dcl_output_siv o0.xyzw, position
dcl_output o1.xy
dcl_output o1.zw
dcl_temps 2
mov o0.zw, l(0,0,0,1.000000)
mad r0.xy, v0.xyxx, cb0[0].zwzz, cb0[0].xyxx
mov o0.xy, r0.xyxx
add r0.x, r0.x, l(1.000000)
add r0.y, -r0.y, l(1.000000)
mul r0.xy, r0.xyxx, cb1[3].xyxx
mul r1.xy, r0.xyxx, l(0.500000, 0.500000, 0.000000, 0.000000)
mov r1.z, l(1.000000)
dp3 o1.z, r1.xyzx, cb1[0].xyzx
dp3 o1.w, r1.xyzx, cb1[1].xyzx
mad o1.xy, v0.xyxx, cb0[2].zwzz, cb0[2].xyxx
ret
// Approximately 12 instruction slots used
};
GeometryShader = NULL;
PixelShader = asm {
//
// Generated by Microsoft (R) HLSL Shader Compiler 9.29.952.3111
//
//
// Buffer Definitions:
//
// cbuffer cb2
// {
//
// float3x3 DeviceSpaceToUserSpace; // Offset: 0 Size: 44 [unused]
// float2 dimensions; // Offset: 48 Size: 8 [unused]
// float3 diff; // Offset: 64 Size: 12
// float2 center1; // Offset: 80 Size: 8
// float A; // Offset: 88 Size: 4
// float radius1; // Offset: 92 Size: 4
// float sq_radius1; // Offset: 96 Size: 4
//
// }
//
//
// Resource Bindings:
//
// Name Type Format Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// sSampler sampler NA NA 0 1
// sMaskSampler sampler NA NA 1 1
// tex texture float4 2d 0 1
// mask texture float4 2d 1 1
// cb2 cbuffer NA NA 0 1
//
//
//
// Input signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------ ------
// SV_Position 0 xyzw 0 POS float
// TEXCOORD 0 xy 1 NONE float xy
// TEXCOORD 1 zw 1 NONE float zw
//
//
// Output signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------ ------
// SV_Target 0 xyzw 0 TARGET float xyzw
//
//
// Constant buffer to DX9 shader constant mappings:
//
// Target Reg Buffer Start Reg # of Regs Data Conversion
// ---------- ------- --------- --------- ----------------------
// c0 cb0 4 3 ( FLT, FLT, FLT, FLT)
//
//
// Sampler/Resource to DX9 shader sampler mappings:
//
// Target Sampler Source Sampler Source Resource
// -------------- --------------- ----------------
// s0 s0 t0
// s1 s1 t1
//
//
// Level9 shader bytecode:
//
ps_2_x
def c3, 0.5, 0, 0, 0
def c4, 1, -1, 0, -0
dcl t0
dcl_2d s0
dcl_2d s1
add r0.xy, t0.wzzw, -c1
dp2add r0.w, r0, r0, -c2.x
mul r0.w, r0.w, c1.z
mov r0.z, c1.w
dp3 r0.x, r0, c0
mad r0.y, r0.x, r0.x, -r0.w
abs r0.z, r0.y
rsq r0.z, r0.z
rcp r1.x, r0.z
mov r1.yz, -r1.x
add r0.xzw, r0.x, r1.xyyz
rcp r1.x, c1.z
mul r0.xzw, r0, r1.x
mov r1.w, c1.w
mad r1.xyz, r0.xzww, c0.z, r1.w
cmp r2.x, r1.x, r0.x, r0.w
cmp r0.xzw, r1.xyyz, c4.xyxy, c4.zyzw
mov r2.y, c3.x
texld r1, t0, s1
texld r2, r2, s0
mul r2.xyz, r2.w, r2
mul r1, r1.w, r2
add r0.w, r0.w, r0.x
cmp r0.x, r0.w, r0.x, r0.z
cmp r1, -r0.x, c4.z, r1
cmp r0, r0.y, r1, c4.z
mov oC0, r0
// approximately 28 instruction slots used (2 texture, 26 arithmetic)
ps_4_0
dcl_constantbuffer cb0[7], immediateIndexed
dcl_sampler s0, mode_default
dcl_sampler s1, mode_default
dcl_resource_texture2d (float,float,float,float) t0
dcl_resource_texture2d (float,float,float,float) t1
dcl_input_ps linear v1.xy
dcl_input_ps linear v1.zw
dcl_output o0.xyzw
dcl_temps 3
add r0.xy, v1.zwzz, -cb0[5].xyxx
mov r0.z, cb0[5].w
dp3 r0.z, r0.xyzx, cb0[4].xyzx
dp2 r0.x, r0.xyxx, r0.xyxx
add r0.x, r0.x, -cb0[6].x
mul r0.x, r0.x, cb0[5].z
mad r0.x, r0.z, r0.z, -r0.x
lt r0.y, r0.x, l(0.000000)
sqrt r1.x, |r0.x|
mov r1.y, -r1.x
add r0.xz, r0.zzzz, r1.xxyx
div r0.xz, r0.xxzx, cb0[5].zzzz
mul r1.xy, r0.xzxx, cb0[4].zzzz
ge r1.xy, r1.xyxx, -cb0[5].wwww
and r1.xy, r1.xyxx, l(0x3f800000, 0x3f800000, 0, 0)
add r0.x, -r0.z, r0.x
mad r2.x, r1.x, r0.x, r0.z
mov r2.y, l(0.500000)
sample r2.xyzw, r2.xyxx, t0.xyzw, s0
if_nz r0.y
mov o0.xyzw, l(0,0,0,0)
ret
endif
max r0.x, r1.y, r1.x
ge r0.x, l(0.000000), r0.x
if_nz r0.x
mov o0.xyzw, l(0,0,0,0)
ret
endif
mul r2.xyz, r2.wwww, r2.xyzx
sample r0.xyzw, v1.xyxx, t1.xyzw, s1
mul o0.xyzw, r0.wwww, r2.xyzw
ret
// Approximately 33 instruction slots used
};
}
pass A0
{
RasterizerState = TextureRast;
VertexShader = asm {
//
// Generated by Microsoft (R) HLSL Shader Compiler 9.29.952.3111
//
//
// Buffer Definitions:
//
// cbuffer cb0
// {
//
// float4 QuadDesc; // Offset: 0 Size: 16
// float4 TexCoords; // Offset: 16 Size: 16 [unused]
// float4 MaskTexCoords; // Offset: 32 Size: 16
//
// }
//
// cbuffer cb2
// {
//
// float3x3 DeviceSpaceToUserSpace; // Offset: 0 Size: 44
// float2 dimensions; // Offset: 48 Size: 8
// float3 diff; // Offset: 64 Size: 12 [unused]
// float2 center1; // Offset: 80 Size: 8 [unused]
// float A; // Offset: 88 Size: 4 [unused]
// float radius1; // Offset: 92 Size: 4 [unused]
// float sq_radius1; // Offset: 96 Size: 4 [unused]
//
// }
//
//
// Resource Bindings:
//
// Name Type Format Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// cb0 cbuffer NA NA 0 1
// cb2 cbuffer NA NA 1 1
//
//
//
// Input signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------ ------
// POSITION 0 xyz 0 NONE float xy
//
//
// Output signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------ ------
// SV_Position 0 xyzw 0 POS float xyzw
// TEXCOORD 0 xy 1 NONE float xy
// TEXCOORD 1 zw 1 NONE float zw
//
//
// Constant buffer to DX9 shader constant mappings:
//
// Target Reg Buffer Start Reg # of Regs Data Conversion
// ---------- ------- --------- --------- ----------------------
// c1 cb0 0 1 ( FLT, FLT, FLT, FLT)
// c2 cb0 2 1 ( FLT, FLT, FLT, FLT)
// c3 cb1 0 2 ( FLT, FLT, FLT, FLT)
// c5 cb1 3 1 ( FLT, FLT, FLT, FLT)
//
//
// Runtime generated constant mappings:
//
// Target Reg Constant Description
// ---------- --------------------------------------------------
// c0 Vertex Shader position offset
//
//
// Level9 shader bytecode:
//
vs_2_x
def c6, 1, 0.5, 0, 0
dcl_texcoord v0
mad oT0.xy, v0, c2.zwzw, c2
mad r0.xy, v0, c1.zwzw, c1
add r0.z, r0.x, c6.x
mul r0.z, r0.z, c5.x
mul r1.x, r0.z, c6.y
add r0.z, -r0.y, c6.x
add oPos.xy, r0, c0
mul r0.x, r0.z, c5.y
mul r1.y, r0.x, c6.y
mov r1.z, c6.x
dp3 oT0.w, r1, c3
dp3 oT0.z, r1, c4
mov oPos.zw, c6.xyzx
// approximately 13 instruction slots used
vs_4_0
dcl_constantbuffer cb0[3], immediateIndexed
dcl_constantbuffer cb1[4], immediateIndexed
dcl_input v0.xy
dcl_output_siv o0.xyzw, position
dcl_output o1.xy
dcl_output o1.zw
dcl_temps 2
mov o0.zw, l(0,0,0,1.000000)
mad r0.xy, v0.xyxx, cb0[0].zwzz, cb0[0].xyxx
mov o0.xy, r0.xyxx
add r0.x, r0.x, l(1.000000)
add r0.y, -r0.y, l(1.000000)
mul r0.xy, r0.xyxx, cb1[3].xyxx
mul r1.xy, r0.xyxx, l(0.500000, 0.500000, 0.000000, 0.000000)
mov r1.z, l(1.000000)
dp3 o1.z, r1.xyzx, cb1[0].xyzx
dp3 o1.w, r1.xyzx, cb1[1].xyzx
mad o1.xy, v0.xyxx, cb0[2].zwzz, cb0[2].xyxx
ret
// Approximately 12 instruction slots used
};
GeometryShader = NULL;
PixelShader = asm {
//
// Generated by Microsoft (R) HLSL Shader Compiler 9.29.952.3111
//
//
// Buffer Definitions:
//
// cbuffer cb2
// {
//
// float3x3 DeviceSpaceToUserSpace; // Offset: 0 Size: 44 [unused]
// float2 dimensions; // Offset: 48 Size: 8 [unused]
// float3 diff; // Offset: 64 Size: 12
// float2 center1; // Offset: 80 Size: 8
// float A; // Offset: 88 Size: 4 [unused]
// float radius1; // Offset: 92 Size: 4
// float sq_radius1; // Offset: 96 Size: 4 [unused]
//
// }
//
//
// Resource Bindings:
//
// Name Type Format Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// sSampler sampler NA NA 0 1
// sMaskSampler sampler NA NA 1 1
// tex texture float4 2d 0 1
// mask texture float4 2d 1 1
// cb2 cbuffer NA NA 0 1
//
//
//
// Input signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------ ------
// SV_Position 0 xyzw 0 POS float
// TEXCOORD 0 xy 1 NONE float xy
// TEXCOORD 1 zw 1 NONE float zw
//
//
// Output signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------ ------
// SV_Target 0 xyzw 0 TARGET float xyzw
//
//
// Constant buffer to DX9 shader constant mappings:
//
// Target Reg Buffer Start Reg # of Regs Data Conversion
// ---------- ------- --------- --------- ----------------------
// c0 cb0 4 2 ( FLT, FLT, FLT, FLT)
//
//
// Sampler/Resource to DX9 shader sampler mappings:
//
// Target Sampler Source Sampler Source Resource
// -------------- --------------- ----------------
// s0 s0 t0
// s1 s1 t1
//
//
// Level9 shader bytecode:
//
ps_2_x
def c2, 0.5, 0, 0, 0
dcl t0
dcl_2d s0
dcl_2d s1
mul r0.w, c1.w, c1.w
add r0.xy, t0.wzzw, -c1
dp2add r0.w, r0, r0, -r0.w
mul r0.w, r0.w, c2.x
mov r0.z, c1.w
dp3 r0.x, r0, c0
rcp r0.x, r0.x
mul r0.x, r0.x, r0.w
mov r0.y, c2.x
texld r1, t0, s1
texld r2, r0, s0
mov r0.w, c1.w
mad r0.x, r0.x, -c0.z, -r0.w
mul r2.xyz, r2.w, r2
mul r1, r1.w, r2
cmp r0, r0.x, c2.y, r1
mov oC0, r0
// approximately 18 instruction slots used (2 texture, 16 arithmetic)
ps_4_0
dcl_constantbuffer cb0[6], immediateIndexed
dcl_sampler s0, mode_default
dcl_sampler s1, mode_default
dcl_resource_texture2d (float,float,float,float) t0
dcl_resource_texture2d (float,float,float,float) t1
dcl_input_ps linear v1.xy
dcl_input_ps linear v1.zw
dcl_output o0.xyzw
dcl_temps 2
add r0.xy, v1.zwzz, -cb0[5].xyxx
mov r0.z, cb0[5].w
dp3 r0.z, r0.xyzx, cb0[4].xyzx
dp2 r0.x, r0.xyxx, r0.xyxx
mad r0.x, -cb0[5].w, cb0[5].w, r0.x
mul r0.x, r0.x, l(0.500000)
div r0.x, r0.x, r0.z
mul r0.z, r0.x, cb0[4].z
ge r0.z, -cb0[5].w, r0.z
mov r0.y, l(0.500000)
sample r1.xyzw, r0.xyxx, t0.xyzw, s0
if_nz r0.z
mov o0.xyzw, l(0,0,0,0)
ret
endif
mul r1.xyz, r1.wwww, r1.xyzx
sample r0.xyzw, v1.xyxx, t1.xyzw, s1
mul o0.xyzw, r0.wwww, r1.xyzw
ret
// Approximately 19 instruction slots used
};
}
pass APosWrap
{
RasterizerState = TextureRast;
VertexShader = asm {
//
// Generated by Microsoft (R) HLSL Shader Compiler 9.29.952.3111
//
//
// Buffer Definitions:
//
// cbuffer cb0
// {
//
// float4 QuadDesc; // Offset: 0 Size: 16
// float4 TexCoords; // Offset: 16 Size: 16 [unused]
// float4 MaskTexCoords; // Offset: 32 Size: 16
//
// }
//
// cbuffer cb2
// {
//
// float3x3 DeviceSpaceToUserSpace; // Offset: 0 Size: 44
// float2 dimensions; // Offset: 48 Size: 8
// float3 diff; // Offset: 64 Size: 12 [unused]
// float2 center1; // Offset: 80 Size: 8 [unused]
// float A; // Offset: 88 Size: 4 [unused]
// float radius1; // Offset: 92 Size: 4 [unused]
// float sq_radius1; // Offset: 96 Size: 4 [unused]
//
// }
//
//
// Resource Bindings:
//
// Name Type Format Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// cb0 cbuffer NA NA 0 1
// cb2 cbuffer NA NA 1 1
//
//
//
// Input signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------ ------
// POSITION 0 xyz 0 NONE float xy
//
//
// Output signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------ ------
// SV_Position 0 xyzw 0 POS float xyzw
// TEXCOORD 0 xy 1 NONE float xy
// TEXCOORD 1 zw 1 NONE float zw
//
//
// Constant buffer to DX9 shader constant mappings:
//
// Target Reg Buffer Start Reg # of Regs Data Conversion
// ---------- ------- --------- --------- ----------------------
// c1 cb0 0 1 ( FLT, FLT, FLT, FLT)
// c2 cb0 2 1 ( FLT, FLT, FLT, FLT)
// c3 cb1 0 2 ( FLT, FLT, FLT, FLT)
// c5 cb1 3 1 ( FLT, FLT, FLT, FLT)
//
//
// Runtime generated constant mappings:
//
// Target Reg Constant Description
// ---------- --------------------------------------------------
// c0 Vertex Shader position offset
//
//
// Level9 shader bytecode:
//
vs_2_x
def c6, 1, 0.5, 0, 0
dcl_texcoord v0
mad oT0.xy, v0, c2.zwzw, c2
mad r0.xy, v0, c1.zwzw, c1
add r0.z, r0.x, c6.x
mul r0.z, r0.z, c5.x
mul r1.x, r0.z, c6.y
add r0.z, -r0.y, c6.x
add oPos.xy, r0, c0
mul r0.x, r0.z, c5.y
mul r1.y, r0.x, c6.y
mov r1.z, c6.x
dp3 oT0.w, r1, c3
dp3 oT0.z, r1, c4
mov oPos.zw, c6.xyzx
// approximately 13 instruction slots used
vs_4_0
dcl_constantbuffer cb0[3], immediateIndexed
dcl_constantbuffer cb1[4], immediateIndexed
dcl_input v0.xy
dcl_output_siv o0.xyzw, position
dcl_output o1.xy
dcl_output o1.zw
dcl_temps 2
mov o0.zw, l(0,0,0,1.000000)
mad r0.xy, v0.xyxx, cb0[0].zwzz, cb0[0].xyxx
mov o0.xy, r0.xyxx
add r0.x, r0.x, l(1.000000)
add r0.y, -r0.y, l(1.000000)
mul r0.xy, r0.xyxx, cb1[3].xyxx
mul r1.xy, r0.xyxx, l(0.500000, 0.500000, 0.000000, 0.000000)
mov r1.z, l(1.000000)
dp3 o1.z, r1.xyzx, cb1[0].xyzx
dp3 o1.w, r1.xyzx, cb1[1].xyzx
mad o1.xy, v0.xyxx, cb0[2].zwzz, cb0[2].xyxx
ret
// Approximately 12 instruction slots used
};
GeometryShader = NULL;
PixelShader = asm {
//
// Generated by Microsoft (R) HLSL Shader Compiler 9.29.952.3111
//
//
// Buffer Definitions:
//
// cbuffer cb2
// {
//
// float3x3 DeviceSpaceToUserSpace; // Offset: 0 Size: 44 [unused]
// float2 dimensions; // Offset: 48 Size: 8 [unused]
// float3 diff; // Offset: 64 Size: 12
// float2 center1; // Offset: 80 Size: 8
// float A; // Offset: 88 Size: 4
// float radius1; // Offset: 92 Size: 4
// float sq_radius1; // Offset: 96 Size: 4
//
// }
//
//
// Resource Bindings:
//
// Name Type Format Dim Slot Elements
// ------------------------------ ---------- ------- ----------- ---- --------
// sWrapSampler sampler NA NA 0 1
// sMaskSampler sampler NA NA 1 1
// tex texture float4 2d 0 1
// mask texture float4 2d 1 1
// cb2 cbuffer NA NA 0 1
//
//
//
// Input signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------ ------
// SV_Position 0 xyzw 0 POS float
// TEXCOORD 0 xy 1 NONE float xy
// TEXCOORD 1 zw 1 NONE float zw
//
//
// Output signature:
//
// Name Index Mask Register SysValue Format Used
// -------------------- ----- ------ -------- -------- ------ ------
// SV_Target 0 xyzw 0 TARGET float xyzw
//
//
// Constant buffer to DX9 shader constant mappings:
//
// Target Reg Buffer Start Reg # of Regs Data Conversion
// ---------- ------- --------- --------- ----------------------
// c0 cb0 4 3 ( FLT, FLT, FLT, FLT)
//
//
// Sampler/Resource to DX9 shader sampler mappings:
//
// Target Sampler Source Sampler Source Resource
// -------------- --------------- ----------------
// s0 s0 t0
// s1 s1 t1
//
//
// Level9 shader bytecode:
//
ps_2_x
def c3, 0.5, 0, 0, 0
def c4, 1, -1, 0, -0
dcl t0
dcl_2d s0
dcl_2d s1
add r0.xy, t0.wzzw, -c1
dp2add r0.w, r0, r0, -c2.x
mul r0.w, r0.w, c1.z
mov r0.z, c1.w
dp3 r0.x, r0, c0
mad r0.y, r0.x, r0.x, -r0.w
abs r0.z, r0.y
rsq r0.z, r0.z
rcp r1.x, r0.z
mov r1.yz, -r1.x
add r0.xzw, r0.x, r1.xyyz
rcp r1.x, c1.z
mul r0.xzw, r0, r1.x
mov r1.w, c1.w
mad r1.xyz, r0.xzww, c0.z, r1.w
cmp r2.x, r1.x, r0.x, r0.w
cmp r0.xzw, r1.xyyz, c4.xyxy, c4.zyzw
mov r2.y, c3.x
texld r1, t0, s1
texld r2, r2, s0
mul r2.xyz, r2.w, r2
mul r1, r1.w, r2
add r0.w, r0.w, r0.x
cmp r0.x, r0.w, r0.x, r0.z
cmp r1, -r0.x, c4.z, r1
cmp r0, r0.y, r1, c4.z
mov oC0, r0
// approximately 28 instruction slots used (2 texture, 26 arithmetic)
ps_4_0
dcl_constantbuffer cb0[7], immediateIndexed
dcl_sampler s0, mode_default
dcl_sampler s1, mode_default
dcl_resource_texture2d (float,float,float,float) t0
dcl_resource_texture2d (float,float,float,float) t1
dcl_input_ps linear v1.xy
dcl_input_ps linear v1.zw
dcl_output o0.xyzw
dcl_temps 3
add r0.xy, v1.zwzz, -cb0[5].xyxx
mov r0.z, cb0[5].w
dp3 r0.z, r0.xyzx, cb0[4].xyzx
dp2 r0.x, r0.xyxx, r0.xyxx
add r0.x, r0.x, -cb0[6].x
mul r0.x, r0.x, cb0[5].z
mad r0.x, r0.z, r0.z, -r0.x
lt r0.y, r0.x, l(0.000000)
sqrt r1.x, |r0.x|
mov r1.y, -r1.x
add r0.xz, r0.zzzz, r1.xxyx