-
Notifications
You must be signed in to change notification settings - Fork 22
/
pass_operandalloc_amd64.go
101 lines (89 loc) · 3.44 KB
/
pass_operandalloc_amd64.go
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
/*
* Copyright 2022 ByteDance Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package ssa
// OperandAlloc for AMD64 converts 3-operand or 2-operand pseudo-instructions
// to 2-operand or one-operand real instructions.
type OperandAlloc struct{}
func (OperandAlloc) Apply(cfg *CFG) {
cfg.PostOrder().ForEach(func(bb *BasicBlock) {
ins := bb.Ins
bb.Ins = make([]IrNode, 0, len(ins))
/* check for every instruction */
for _, v := range ins {
switch p := v.(type) {
default: {
bb.Ins = append(bb.Ins, v)
}
/* negation */
case *IrAMD64_NEG: {
if p.R == p.V {
bb.Ins = append(bb.Ins, v)
} else {
bb.Ins, p.V = append(bb.Ins, IrArchCopy(p.R, p.V), v), p.R
}
}
/* byte swap */
case *IrAMD64_BSWAP: {
if p.R == p.V {
bb.Ins = append(bb.Ins, v)
} else {
bb.Ins, p.V = append(bb.Ins, IrArchCopy(p.R, p.V), v), p.R
}
}
/* binary operations, register to register */
case *IrAMD64_BinOp_rr: {
if p.R == p.X {
bb.Ins = append(bb.Ins, v)
} else {
bb.Ins, p.X = append(bb.Ins, IrArchCopy(p.R, p.X), v), p.R
}
}
/* binary operations, register to immediate */
case *IrAMD64_BinOp_ri: {
if p.R == p.X || p.Op == IrAMD64_BinMul {
bb.Ins = append(bb.Ins, v)
} else {
bb.Ins, p.X = append(bb.Ins, IrArchCopy(p.R, p.X), v), p.R
}
}
/* binary operations, register to memory */
case *IrAMD64_BinOp_rm: {
if p.R == p.X {
bb.Ins = append(bb.Ins, v)
} else {
bb.Ins, p.X = append(bb.Ins, IrArchCopy(p.R, p.X), v), p.R
}
}
/* bit test and set, register to register */
case *IrAMD64_BTSQ_rr: {
if p.S == p.X {
bb.Ins = append(bb.Ins, v)
} else {
bb.Ins, p.X = append(bb.Ins, IrArchCopy(p.S, p.X), v), p.S
}
}
/* bit test and set, register to immediate */
case *IrAMD64_BTSQ_ri: {
if p.S == p.X {
bb.Ins = append(bb.Ins, v)
} else {
bb.Ins, p.X = append(bb.Ins, IrArchCopy(p.S, p.X), v), p.S
}
}
}
}
})
}