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  (paper "B")

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    (title "ULPI USB Transceiver and Hub")
    (date "2020-07-09")
    (rev "1.0")
    (comment 1 "Drawn by: Cameron McQuinn")
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  (text "Clocking note: USB3343 is configured for ULPI Clock Output Mode.\nREFCLK is driven by oscillator and ULPI Clock is generated by\nPLL internal to USB3343 and exposed on CLKOUT pin. Zynq ULPI\ncontroller requires that the PHY generate the 60MHz reference\nclock used to synchronize the controller logic. See section\n15.15.1 \"Clocks\" of Zynq 7000 Technical Reference Manual and\nSection 5.5.1.2 \"ULPI Clock Output Mode\" of USB3343 datasheet."
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  (text "USB2514 is clocked at 24MHz. See section\n7.2 \"External Clock\" of USB2514 datasheet."
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  (text "CLK source series termination\nresistor. See Section 3.1\n\"Physical Interconnect\"\nof Microchip AN 19.17."
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  (text "Layout note: Differential pairs\n2 and 3 have their polarity\nswapped to make layout easier."
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  (text "Layout note: place RBIAS resistor\nas close to USB3343 as possible."
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  (text "TODO:  VBUS_OUT should\nbe connected to something" (at 214.63 134.62 0)
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  (text "CFG_SEL[2] = 2'b01" (at 245.11 175.26 180)
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  (text "Layout note: place capacitors as\nclose to CRFILT and PLFILT as\npossible without using vias. See\nsections CRFILT and PLFILT of\nUSB2514B Schematic Checklist."
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