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WriteVHDLSyntax.py
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WriteVHDLSyntax.py
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from builtins import range
from TrackletGraph import MemModule, ProcModule, MemTypeInfoByKey
def getVMStubNCopy(memmod):
mem = memmod.inst;
if "VMSTE" in mem:
proc = memmod.downstreams[0].inst;
if "L1L2" in proc:
return 5;
if "L2L3" in proc:
return 2;
if "L3L4" in proc:
return 5;
if "L5L6" in proc:
return 3;
if "D1D2" in proc:
return 3;
if "D3D4" in proc:
return 2;
if "L1D1" in proc:
return 3;
if "L2D1" in proc:
return 2;
return "Error no match for "+proc
elif "VMSME" in mem:
if "L1" in mem:
return 4;
if "L2" in mem:
return 4;
if "L3" in mem:
return 4;
if "L4" in mem:
return 4;
if "L5" in mem:
return 4;
if "L6" in mem:
return 4;
if "D1" in mem:
return 4;
if "D2" in mem:
return 4;
if "D3" in mem:
return 4;
if "D4" in mem:
return 4;
if "D5" in mem:
return 4;
return "Error no match for "+mem
else:
return "Wrong memory module:"+mem
def writeTopPreamble(all=True):
string_preamble = "--! Standard libraries\n"
string_preamble += "library IEEE;\n"+"use IEEE.STD_LOGIC_1164.ALL;\n"
string_preamble += "--! User packages\n"
string_preamble += "use work.tf_pkg.all;\n"
if all:
string_preamble += "use work.memUtil_pkg.all;\n"
string_preamble += "\n"
return string_preamble
def writeModulesPreamble():
string_preamble = "\n"
string_preamble = "\nbegin\n\n"
return string_preamble
def writeTBPreamble():
string_preamble = "--! Standard library\n"
string_preamble += "library ieee;\n"
string_preamble += "--! Standard package\n"
string_preamble += "use ieee.std_logic_1164.all;\n"
string_preamble += "--! Signed/unsigned calculations\n"
string_preamble += "use ieee.numeric_std.all;\n"
string_preamble += "--! Math real\n"
string_preamble += "use ieee.math_real.all;\n"
string_preamble += "--! TextIO\n"
string_preamble += "use ieee.std_logic_textio.all;\n"
string_preamble += "--! Standard functions\n"
string_preamble += "library std;\n"
string_preamble += "--! Standard TextIO functions\n"
string_preamble += "use std.textio.all;\n"
string_preamble += "\n--! Xilinx library\n"
string_preamble += "library unisim;\n"
string_preamble += "--! Xilinx package\n"
string_preamble += "use unisim.vcomponents.all;\n"
string_preamble += "\n--! User packages\n"
string_preamble += "use work.tf_pkg.all;\n"
string_preamble += "use work.memUtil_pkg.all;\n\n"
return string_preamble
def writeTopModuleOpener(topmodule_name):
string_topmod_opener = "entity "+topmodule_name+" is\n port(\n"
return string_topmod_opener
def writeTBOpener(topfunc):
string_tb_opener = "--! @brief TB\n"
string_tb_opener += "entity " + topfunc + " is\n"
string_tb_opener += "end " + topfunc + ";\n\n"
string_tb_opener += "--! @brief TB\n"
string_tb_opener += "architecture behaviour of "+ topfunc +" is\n\n"
return string_tb_opener
def writeTopModuleEntityCloser(topmodule_name):
string_closer = "end "+topmodule_name+";\n\n"
string_closer += "architecture rtl of "+topmodule_name+" is\n\n"
return string_closer
def writeTBEntityBegin():
string_begin = "begin\n\n"
string_begin += "--! @brief Make clock ---------------------------------------\n"
string_begin += " clk <= not clk after CLK_PERIOD/2;\n\n"
return string_begin
def writeTopModuleCloser():
string_closer = "\n\nend rtl;\n"
return string_closer
def writeTBModuleCloser():
string_closer = "\nend behaviour;\n"
return string_closer
def writeTBMemoryStimulusProcess(initial_proc):
"""
# VHDL test-bench
# Stimulates reading and process start
"""
string_mem = " procStart : process(CLK)\n"
string_mem += " -- Process to start first module in chain & generate its BX counter input.\n"
string_mem += " -- Also releases reset flag.\n"
string_mem += " constant CLK_RESET : natural := 5; -- Any low number OK.\n"
string_mem += " variable CLK_COUNT : natural := 1;\n" if "IR" not in initial_proc else " variable CLK_COUNT : natural := MAX_ENTRIES - CLK_RESET;\n"
string_mem += " variable EVENT_COUNT : integer := -1;\n"
string_mem += " variable v_line : line; -- Line for debug\n"
string_mem += " begin\n\n"
string_mem += " if START_FIRST_" + ("WRITE" if "IR" not in initial_proc else "LINK") + " = '1' then\n"
string_mem += " if rising_edge(CLK) then\n"
string_mem += " if (CLK_COUNT < MAX_ENTRIES) then\n"
string_mem += " CLK_COUNT := CLK_COUNT + 1;\n"
string_mem += " else\n"
string_mem += " CLK_COUNT := 1;\n"
string_mem += " EVENT_COUNT := EVENT_COUNT + 1;\n\n"
string_mem += " -- " + initial_proc + " should start one TM period after time when first event starting being \n" if "IR" not in initial_proc else ""
string_mem += " -- written to first memory in chain, as it takes this long to write full event.\n" if "IR" not in initial_proc else ""
string_mem += " " + initial_proc + "_START <= '1';\n"
string_mem += " " + initial_proc + "_BX_IN <= std_logic_vector(to_unsigned(EVENT_COUNT, " + initial_proc + "_BX_IN'length));\n\n"
string_mem += " write(v_line, string'(\"=== Processing event \")); write(v_line,EVENT_COUNT); write(v_line, string'(\" at SIM time \")); write(v_line, NOW); writeline(output, v_line);\n"
string_mem += " end if;\n"
string_mem += " -- Releae\n"
string_mem += " if (CLK_COUNT = " + ("CLK_RESET" if "IR" not in initial_proc else "MAX_ENTRIES") + ") then \n"
string_mem += " RESET <= '0';\n"
string_mem += " end if;\n"
string_mem += " end if;\n"
string_mem += " end if;\n"
string_mem += " end process procStart;\n\n"
return string_mem
def writeTBMemoryReadInstance(mtypeB, memDict, bxbitwidth, is_initial, is_binned, split):
"""
# VHDL test-bench
# Reads memory text files
"""
str_len = 22 # length of string for formatting purposes
string_mem = ""
memList = memDict[mtypeB]
for memMod in memList :
mem = memMod.inst
if split and "in" not in mem:
continue
if "DL" in mtypeB and "AS" not in mtypeB: # Special case for DTC links that reads from FIFOs
string_mem += " read" + mem + " : entity work.FileReaderFIFO\n"
string_mem += " generic map (\n"
memtmp = mem.replace("twoS","2S")
string_mem += " FILE_NAME".ljust(str_len) + "=> FILE_IN_DL&\""+ memtmp + "\"&inputFileNameEnding,\n"
string_mem += " DELAY".ljust(str_len) + "=> " + mtypeB.split("_")[0] + "_DELAY*MAX_ENTRIES,\n"
string_mem += " FIFO_WIDTH".ljust(str_len) + "=> " + mtypeB.split("_")[1] + ",\n"
string_mem += " DEBUG".ljust(str_len) + "=> true,\n"
string_mem += " FILE_NAME_DEBUG".ljust(str_len) + "=> FILE_OUT_DL_debug&\""+ memtmp + "\"&debugFileNameEnding\n"
string_mem += " )\n"
string_mem += " port map (\n"
string_mem += " CLK".ljust(str_len) + "=> CLK,\n"
string_mem += " READ_EN".ljust(str_len) + "=> " + mem + "_link_read,\n"
string_mem += " DATA".ljust(str_len) + "=> " + mem + "_link_AV_dout,\n"
string_mem += " START".ljust(str_len) + "=> " + ("START_" + mem + ",\n" if is_initial else "open,\n")
string_mem += " EMPTY_NEG".ljust(str_len) + "=> " + mem + "_link_empty_neg\n"
else: # Standard case for BRAM
string_mem += " read" + mem + " : entity work.FileReader\n"
string_mem += " generic map (\n"
#FIXME Hack for reading the AS input memories
memtmp = mem.replace("in","n1")
if "MPAR" in mem :
memtmp = memtmp.replace("n1","")
# memtmp = "T"+mem[1:10]
string_mem += " FILE_NAME".ljust(str_len) + "=> FILE_IN_" + mtypeB+"&\""+ memtmp + "\"&inputFileNameEnding,\n"
string_mem += " DELAY".ljust(str_len) + "=> " + mtypeB.split("_")[0] + "_DELAY*MAX_ENTRIES,\n"
string_mem += " RAM_WIDTH".ljust(str_len) + "=> " + mtypeB.split("_")[1] + ",\n"
string_mem += " NUM_PAGES".ljust(str_len) + "=> " + str(2**bxbitwidth) + ",\n"
if "MPAR" in mem or "MPROJ" in mem:
string_mem += " NUM_TPAGES".ljust(str_len) + "=> 4,\n"
if "MPAR" in mem :
string_mem += " NUM_BINS".ljust(str_len) + "=> 4,\n"
else:
string_mem += " NUM_BINS".ljust(str_len) + "=> 8,\n" if is_binned else "" # FIX ME 16 for MEDISK
string_mem += " DEBUG".ljust(str_len) + "=> true,\n"
string_mem += " FILE_NAME_DEBUG".ljust(str_len) + "=> FILE_OUT_" + mtypeB+"&\""+ mem + "_debug\"&debugFileNameEnding\n"
string_mem += " )\n"
string_mem += " port map (\n"
string_mem += " CLK".ljust(str_len) + "=> CLK,\n"
string_mem += " ADDR".ljust(str_len) + "=> " + mem + "_writeaddr,\n"
string_mem += " DATA".ljust(str_len) + "=> " + mem + "_din,\n"
string_mem += " START".ljust(str_len) + "=> START_" + mem + ",\n" if is_initial else " START => open,\n"
string_mem += " WRITE_EN".ljust(str_len) + "=> " + mem + "_wea\n"
string_mem += " );\n"
return string_mem
def writeMemoryUtil(memDict, memInfoDict):
"""
# Produce VHDL package with utilities for memories that are specific
# to current chain.
# Inputs:
# memDict = dictionary of memories organised by type
# & no. of bits (TPROJ_58 etc.)
# memInfoDict = dictionary of info about each memory type.
"""
ss = writeTopPreamble(False)
ss += "package memUtil_pkg is\n\n"
ss += " -- ########################### Types ###########################\n\n"
for mtypeB in memDict:
memInfo = memInfoDict[mtypeB]
memList = memDict[mtypeB]
# Sort with memories connected to top-level interface first.
# (This required only for special case, where only a subset of
# memories of given type are interfaced to top-level function.
# It allows a VHDL enum of this subset to be a VHDL subtype of the
# enum of all memories of this type).
memList.sort(key=lambda m: int(m.is_initial or m.is_final), reverse=True)
# Define enum type listing all memory instances of this type.
enumName = "enum_"+mtypeB
ss += " type "+enumName+" is ("
for mem in memList:
ss += mem.var()+","
ss = ss.rstrip(",")
ss += ");\n\n"
"""
# FIX IF NEEDED:
# Needed only for special case where only a subset of memories of
# given type are interfaced to top-level function.
# Define enum subtype for them.
if memInfo.mixedIO:
varListExt = []
for mem in memList:
if mem.is_initial or mem.is_final:
varListExt.append(mem.var())
assert(len(varListExt()) > 0)
enumName = "enumPartial_"+mtypeB
ss += " subtype "+enumName+" is enum_"+mtypeB
ss += " range "+varList[0]
ss += " to " +varList[-1]+";\n\n"
"""
# Define array types indexed by enums above used for signals connecting to memories.
for mtypeB in memInfoDict:
memInfo = memInfoDict[mtypeB]
enumName = "enum_"+mtypeB
mtype = mtypeB.split("_")[0]
bitwidth = int(mtypeB.split("_")[1]);
num_pages = 2**memInfo.bxbitwidth
if memInfo.isFIFO:
tName = "t_"+mtypeB+"_1b"
ss += " subtype "+tName+" is std_logic;\n"
tName = "t_"+mtypeB+"_DATA"
ss += " subtype "+tName+" is std_logic_vector("+str(bitwidth-1)+" downto 0);\n"
else:
if memInfo.is_binned:
ncopy = 4
if memInfo.downstream_mtype_short == "TP" :
ncopy = 5
tName = "t_"+mtypeB+"_1b"
ss += " subtype "+tName+" is std_logic;\n"
tName = "t_"+mtypeB+"_A1b"
ss += " subtype "+tName+" is std_logic_vector("+str(ncopy-1)+" downto 0);\n"
tName = "t_"+mtypeB+"_ADDR"
ss += " subtype "+tName+" is std_logic_vector("+str(9+memInfo.bxbitwidth)+" downto 0);\n"
tName = "t_"+mtypeB+"_ADDRDISK"
ss += " subtype "+tName+" is std_logic_vector("+str(10+memInfo.bxbitwidth)+" downto 0);\n"
tName = "t_"+mtypeB+"_AADDR"
ss += " subtype "+tName+" is t_arr"+str(ncopy)+"_"+str(10+memInfo.bxbitwidth)+"b;\n"
tName = "t_"+mtypeB+"_AADDRDISK"
ss += " subtype "+tName+" is t_arr"+str(ncopy)+"_"+str(11+memInfo.bxbitwidth)+"b;\n"
tName = "t_"+mtypeB+"_DATA"
ss += " subtype "+tName+" is std_logic_vector("+str(bitwidth-1)+" downto 0);\n"
tName = "t_"+mtypeB+"_ADATA"
ss += " subtype "+tName+" is t_arr"+str(ncopy)+"_"+str(bitwidth)+"b;\n"
else:
tName = "t_"+mtypeB+"_1b"
ss += " subtype "+tName+" is std_logic;\n"
if "MPAR" in mtypeB or "MPROJ" in mtypeB:
tName = "t_"+mtypeB+"_ADDR"
ss += " subtype "+tName+" is std_logic_vector("+str(8+memInfo.bxbitwidth)+" downto 0);\n"
else:
tName = "t_"+mtypeB+"_ADDR"
ss += " subtype "+tName+" is std_logic_vector("+str(6+memInfo.bxbitwidth)+" downto 0);\n"
tName = "t_"+mtypeB+"_DATA"
ss += " subtype "+tName+" is std_logic_vector("+str(bitwidth-1)+" downto 0);\n"
if memInfo.is_binned:
varStr = "_64_4b"
else:
varStr = "_7b"
if "MPROJ" in tName:
tName = "t_"+mtypeB+"_MASK"
ss += " subtype "+tName+" is t_arr"+str(num_pages)+"_4b;\n"
tName = "t_"+mtypeB+"_NENT"
if memInfo.is_binned:
ss += " subtype "+tName+" is std_logic_vector(63 downto 0);\n"
tName = "t_"+mtypeB+"_NENTADDR"
nentaddrbits = "3"
ss += " subtype "+tName+" is std_logic_vector("+nentaddrbits+" downto 0);\n"
tName = "t_"+mtypeB+"_NENTADDRDISK"
nentaddrbits = "4"
ss += " subtype "+tName+" is std_logic_vector("+nentaddrbits+" downto 0);\n"
else:
#FIXME
tpages = 1
if "MPROJ" in tName or "MPAR" in tName:
tpages = 4
ss += " subtype "+tName+" is t_arr"+str(num_pages*tpages)+varStr+";\n"
if memInfo.is_binned:
varStr = "_64_1b"
tName = "t_"+mtypeB+"_MASK"
ss += " subtype "+tName+" is t_arr"+str(num_pages)+varStr+";\n"
tName = "t_"+mtypeB+"_MASK_"+str(num_pages)
ss += " subtype "+tName+" is std_logic_vector("+str(num_pages)+"*64-1 downto 0);\n"
varStr = "_128_1b"
tName = "t_"+mtypeB+"_MASKDISK"
ss += " subtype "+tName+" is t_arr"+str(num_pages)+varStr+";\n"
tName = "t_"+mtypeB+"_MASKDISK_"+str(num_pages)
ss += " subtype "+tName+" is std_logic_vector("+str(num_pages)+"*128-1 downto 0);\n"
vmstubwidth = memInfo.bitwidth
if "VMSTE" in mtypeB:
ss += " subtype "+tName+"_2 is std_logic_vector(2*64-1 downto 0);\n"
tName = "t_"+mtypeB+"_DATA"
ss += " subtype "+tName+"_2 is std_logic_vector(2*"+str(vmstubwidth)+"-1 downto 0);\n"
ss += " subtype "+tName+"_3 is std_logic_vector(3*"+str(vmstubwidth)+"-1 downto 0);\n"
ss += " subtype "+tName+"_4 is std_logic_vector(4*"+str(vmstubwidth)+"-1 downto 0);\n"
ss += " subtype "+tName+"_5 is std_logic_vector(5*"+str(vmstubwidth)+"-1 downto 0);\n"
if "VMSME" in mtypeB:
ss += " subtype "+tName+"_4 is std_logic_vector(4*64-1 downto 0);\n"
tName = "t_"+mtypeB+"_DATA"
ss += " subtype "+tName+"_2 is std_logic_vector(2*"+str(vmstubwidth)+"-1 downto 0);\n"
ss += " subtype "+tName+"_3 is std_logic_vector(3*"+str(vmstubwidth)+"-1 downto 0);\n"
ss += " subtype "+tName+"_4 is std_logic_vector(4*"+str(vmstubwidth)+"-1 downto 0);\n"
ss += "\n -- ########################### Functions ###########################\n\n"
ss += " -- Following functions are needed because VHDL doesn't preserve case when converting an enum to a string using image\n"
for mtypeB in memDict:
ss += " function memory_enum_to_string(val: enum_"+mtypeB+") return string;\n";
ss += "\nend package memUtil_pkg;\n\n"
ss += "package body memUtil_pkg is\n\n"
ss += " -- ########################### Functions ###########################\n\n"
for mtypeB in memDict:
memList = memDict[mtypeB]
ss += " function memory_enum_to_string(val: enum_"+mtypeB+") return string is\n";
ss += " begin\n"
ss += " case val is\n"
for mem in memList:
newvar = mem.var()
# Bodge explained in TrackletGraph::Node()
if (mem.inst.startswith("DL_twoS")):
newvar = newvar.replace("twoS","2S")
ss += " when "+mem.var()+" => return \""+newvar+"\";\n"
ss += " end case;\n"
ss += " return \"No conversion found.\";\n"
ss += " end memory_enum_to_string;\n\n"
ss += "end package body memUtil_pkg;\n"
return ss;
def writeTopLevelMemoryType(mtypeB, memList, memInfo, extraports, delay = 0, split = False):
"""
# Declaration of memories of type "mtype" (e.g. TPROJ) & associated wires
# Inputs:
# mTypeB = memory type & its bits width (TPROJ_58 etc.)
# memList = list of memories of given type & bit width
# memInfo = Info about each memory type (in MemTypeInfoByKey class)
"""
wirelist = ""
mem_str = ""
mtype = mtypeB.split("_")[0]
bitwidth = mtypeB.split("_")[1]
# Assume all memories of given type have same bxbitwidth.
bxbitwidth = memInfo.bxbitwidth
num_pages = 2**bxbitwidth
interface = int(memInfo.is_final) - int(memInfo.is_initial)
for memmod in memList:
nmem = 0
mem=memmod.inst
disk = ""
if memInfo.is_binned:
nmem = getVMStubNCopy(memmod)
if "VMSME_D" in mem:
disk="DISK"
if interface == 1:
assert memInfo.upstream_mtype_short != ""
sync_signal = memmod.upstreams[0].inst+"_done"
else:
assert memInfo.downstream_mtype_short != ""
sync_signal = memmod.downstreams[0].inst+"_start"
parameterlist = ""
portlist = ""
delay_parameterlist = ""
delay2_parameterlist = ""
delay_portlist_0 = ""
delay_portlist = ""
delay2_portlist = ""
#FIXME
if "MPAR" in mem and not "in" in mem:
interface = 0
extraports = False
if "AS" in mem and not "in" in mem:
interface = 0
extraports = False
# Write wires
if delay > 0:
if not memInfo.is_binned:
wirelist += " signal "+mem+"_bx : "
wirelist += "std_logic_vector(2 downto 0);\n"
wirelist += " signal "+mem+"_start : "
wirelist += "std_logic;\n"
wirelist += " signal "+mem+"_wea_delay_0 : "
wirelist += "t_"+mtypeB+"_1b;\n"
wirelist += " signal "+mem+"_writeaddr_delay_0 : "
wirelist += "t_"+mtypeB+"_ADDR"+disk+";\n"
wirelist += " signal "+mem+"_din_delay_0 : "
wirelist += "t_"+mtypeB+"_DATA;\n"
wirelist += " signal "+mem+"_wea_delay : "
wirelist += "t_"+mtypeB+"_1b;\n"
wirelist += " signal "+mem+"_writeaddr_delay : "
wirelist += "t_"+mtypeB+"_ADDR"+disk+";\n"
wirelist += " signal "+mem+"_din_delay : "
wirelist += "t_"+mtypeB+"_DATA;\n"
if (interface != -1 and not extraports):
wirelist += " signal "+mem+"_wea : "
wirelist += "t_"+mtypeB+"_1b;\n"
wirelist += " signal "+mem+"_writeaddr : "
wirelist += "t_"+mtypeB+"_ADDR"+disk+";\n"
wirelist += " signal "+mem+"_din : "
wirelist += "t_"+mtypeB+"_DATA;\n"
if interface != 1 :
if memInfo.is_binned :
wirelist += " signal "+mem+"_A_enb : "
wirelist += "t_"+mtypeB+"_A1b;\n"
wirelist += " signal "+mem+"_AV_readaddr : "
wirelist += "t_"+mtypeB+"_AADDR"+disk+";\n"
wirelist += " signal "+mem+"_AV_dout : "
wirelist += "t_"+mtypeB+"_ADATA;\n"
else:
wirelist += " signal "+mem+"_enb : "
wirelist += "t_"+mtypeB+"_1b;\n"
wirelist += " signal "+mem+"_V_readaddr : "
wirelist += "t_"+mtypeB+"_ADDR"+disk+";\n"
wirelist += " signal "+mem+"_V_dout : "
wirelist += "t_"+mtypeB+"_DATA;\n"
#FIXME this is a hack
if "MPAR" in mem and "in" in mem :
wirelist += " signal "+mem+"_V_tpar : "
wirelist += "t_"+mtypeB+"_DATA;\n"
wirelist += " signal "+mem+"_valid : "
wirelist += "STD_LOGIC;\n"
wirelist += " signal "+mem+"_trackletindex : "
wirelist += "STD_LOGIC_VECTOR(8 downto 0);\n"
wirelist += " signal "+mem+"_AV_dout_nent : "
wirelist += "t_arr_7b(0 to 31);\n"
#FIXME this is a hack
if "AS" in mem and "in" in mem :
wirelist += " signal "+mem+"_V_as : "
wirelist += "t_"+mtypeB+"_DATA;\n"
wirelist += " signal "+mem+"_valid : "
wirelist += "STD_LOGIC;\n"
wirelist += " signal "+mem+"_index : "
wirelist += "STD_LOGIC_VECTOR(31 downto 0);\n"
if memInfo.has_numEntries_out:
if memInfo.is_binned:
disk=""
if "VMSME_D" in mem:
disk="DISK"
wirelist += " signal "+mem+"_AV_dout_mask : "
wirelist += "t_"+mtypeB+"_MASK"+disk+"; -- (#page)(#bin)\n"
wirelist += " signal "+mem+"_enb_nent : "
wirelist += "t_"+mtypeB+"_1b;\n"
wirelist += " signal "+mem+"_V_addr_nent : "
wirelist += "t_"+mtypeB+"_NENTADDR"+disk+";\n"
wirelist += " signal "+mem+"_AV_dout_nent : "
wirelist += "t_"+mtypeB+"_NENT; -- (#page)(#bin)\n"
wirelist += " signal "+mem+"_V_datatmp : "
wirelist += "t_"+mtypeB+"_DATA_"+str(nmem)+";\n"
wirelist += " signal "+mem+"_V_masktmp : "
wirelist += "t_"+mtypeB+"_MASK"+disk+"_"+str(num_pages)+";\n"
else:
wirelist += " signal "+mem+"_AV_dout_nent : "
wirelist += "t_"+mtypeB+"_NENT; -- (#page)\n"
if "MPROJ" in mem:
wirelist += " signal "+mem+"_AV_dout_mask : "
wirelist += "t_"+mtypeB+"_MASK;\n"
else :
if memInfo.is_binned:
disk=""
if "VMSME_D" in mem:
disk="DISK"
wirelist += " signal "+mem+"_V_datatmp : "
wirelist += "t_"+mtypeB+"_DATA_"+str(nmem)+";\n"
wirelist += " signal "+mem+"_V_masktmp : "
wirelist += "t_"+mtypeB+"_MASK"+disk+"_"+str(num_pages)+";\n"
# Write parameters
parameterlist += " RAM_WIDTH => "+bitwidth+",\n"
parameterlist += " NUM_PAGES => "+str(num_pages)+",\n"
if "MPROJ" in mem or "MPAR" in mem:
parameterlist += " NUM_TPAGES => 4,\n"
parameterlist += " INIT_FILE => \"\",\n"
parameterlist += " INIT_HEX => true,\n"
parameterlist += " RAM_PERFORMANCE => \"HIGH_PERFORMANCE\",\n"
parameterlist += " NAME => \""+mem+"\",\n"
if delay > 0:
delay2_parameterlist +=" DELAY => " + str(delay*2) +",\n"
delay_parameterlist +=" DELAY => " + str(delay) +",\n"
#enable to use non-default delay value
if "MPAR" in mem or "MPROJ" in mem:
#special case for the merged memories
delay_parameterlist +=" NUM_PAGES => "+str(4*num_pages)+",\n"
else:
delay_parameterlist +=" NUM_PAGES => "+str(num_pages)+",\n"
if memInfo.is_binned:
disk=""
if "VMSME_D" in mem:
disk = "*2"
delay_parameterlist +=" RAM_DEPTH => "+str(num_pages)+disk+"*PAGE_LENGTH_CM,\n"
delay_parameterlist +=" RAM_WIDTH => "+bitwidth+",\n"
ncopy = getVMStubNCopy(memmod);
if "VMSTE_" in mem:
parameterlist += " ADDR_WIDTH => 4,\n"
parameterlist += " NUM_PHI_BINS => 8,\n"
parameterlist += " NUM_RZ_BINS => 8,\n"
parameterlist += " NUM_COPY => "+str(ncopy)+"\n"
if "VMSME_L" in mem: # VMSME memories have 16 bins in the disks
parameterlist += " ADDR_WIDTH => 4,\n"
parameterlist += " NUM_PHI_BINS => 8,\n"
parameterlist += " NUM_RZ_BINS => 8,\n"
parameterlist += " NUM_COPY => "+str(ncopy)+"\n"
if "VMSME_D" in mem: # VMSME memories have 16 bins in the disks
parameterlist += " ADDR_WIDTH => 4,\n"
parameterlist += " NUM_PHI_BINS => 8,\n"
parameterlist += " NUM_RZ_BINS => 16,\n"
parameterlist += " NUM_COPY => "+str(ncopy)+"\n"
#FIXME implement delay for disks
# Write ports
portlist += " clka => clk,\n"
if delay > 0:
portlist += " wea => "+mem+"_wea_delay,\n"
portlist += " addra => "+mem+"_writeaddr_delay,\n"
portlist += " dina => "+mem+"_din_delay,\n"
else:
portlist += " wea => "+mem+"_wea,\n"
portlist += " addra => "+mem+"_writeaddr,\n"
portlist += " dina => "+mem+"_din,\n"
if delay > 0:
delay2_portlist += " clk => clk,\n"
delay2_portlist += " reset => reset,\n"
#FIXME
if not "in" in mem :
if "VMSMER" in memmod.upstreams[0].mtype_short() or "PC" in memmod.upstreams[0].mtype_short():
delay2_portlist += " done => PC_done,\n"
delay2_portlist += " bx_out => PC_bx_out,\n"
else:
delay2_portlist += " done => "+memmod.upstreams[0].mtype_short()+"_done,\n"
delay2_portlist += " bx_out => "+memmod.upstreams[0].mtype_short()+"_bx_out,\n"
delay2_portlist += " bx => "+mem+"_bx,\n"
delay2_portlist += " start => "+mem+"_start,\n"
delay_portlist_0 += " clk => clk,\n"
delay_portlist_0 += " wea => "+mem+"_wea,\n"
delay_portlist_0 += " addra => "+mem+"_writeaddr,\n"
delay_portlist_0 += " dina => "+mem+"_din,\n"
delay_portlist_0 += " wea_out => "+mem+"_wea_delay_0,\n"
delay_portlist_0 += " addra_out => "+mem+"_writeaddr_delay_0,\n"
delay_portlist_0 += " dina_out => "+mem+"_din_delay_0,\n"
delay_portlist += " clk => clk,\n"
delay_portlist += " wea => "+mem+"_wea_delay_0,\n"
delay_portlist += " addra => "+mem+"_writeaddr_delay_0,\n"
delay_portlist += " dina => "+mem+"_din_delay_0,\n"
delay_portlist += " wea_out => "+mem+"_wea_delay,\n"
delay_portlist += " addra_out => "+mem+"_writeaddr_delay,\n"
delay_portlist += " dina_out => "+mem+"_din_delay,\n"
portlist += " clkb => clk,\n"
portlist += " rstb => '0',\n"
portlist += " regceb => '1',\n"
if not memInfo.is_binned :
portlist += " enb => "+mem+"_enb,\n"
portlist += " addrb => "+mem+"_V_readaddr,\n"
portlist += " doutb => "+mem+"_V_dout,\n"
if ("AS" in mem or "MPAR" in mem) and "in" in mem:
portlist += " sync_nent => PC_start,\n"
elif "MPAR" in mem and "in" not in mem:
portlist += " sync_nent => "+mem+"_start,\n"
else:
portlist += " sync_nent => "+sync_signal+",\n"
if memmod.has_numEntries_out:
if memList[0].is_binned:
ncopy = getVMStubNCopy(memmod);
portlist += " enb => ("
for i in reversed(range(0, ncopy)) :
if i != 0 :
portlist += mem+"_A_enb("+str(i)+"),"
else:
portlist += mem+"_A_enb("+str(i)+")),\n"
portlist += " addrb => ("
for i in reversed(range(0, ncopy)) :
if i !=0 :
portlist += mem+"_AV_readaddr("+str(i)+"),"
else:
portlist += mem+"_AV_readaddr("+str(i)+")),\n"
portlist += " doutb => "+mem+"_V_datatmp,\n"
portlist += " enb_nent => "+mem+"_enb_nent,\n"
portlist += " addr_nent => "+mem+"_V_addr_nent,\n"
portlist += " dout_nent => "+mem+"_AV_dout_nent,\n"
portlist += " mask_o => "+mem+"_V_masktmp,\n"
else:
portlist += " nent_o => "+mem+"_AV_dout_nent,\n"
if "MPROJ" in mem:
portlist += " mask_o => "+mem+"_AV_dout_mask,\n"
else:
portlist += " nent_o => open,\n"
if memList[0].is_binned:
vmstubwidth = str(memInfo.bitwidth)
nbx = 2**bxbitwidth
ncopy = getVMStubNCopy(memmod)
mem_str += " "+mem+"_dataformat : entity work.vmstub"+vmstubwidth+"dout"+str(ncopy)+"\n"
module = memList[0].downstreams[0].inst[0:3]
mem_str += " port map (\n"
mem_str += " datain => "+mem+"_V_datatmp,\n"
for i in range(0, ncopy) :
if i < ncopy-1 :
mem_str += " dataout"+str(i)+" => "+mem+"_AV_dout("+str(i)+"),\n"
else:
mem_str += " dataout"+str(i)+" => "+mem+"_AV_dout("+str(i)+")\n"
mem_str += " );\n\n"
disk = ""
if "VMSME_D" in mem:
disk = "DISK"
mem_str += " "+mem+"_maskformat : entity work.vmstub"+str(nbx)+"mask"+disk+"\n"
mem_str += " port map (\n"
mem_str += " datain => "+mem+"_V_masktmp,\n"
for i in range(0, nbx) :
if i < nbx-1 :
mem_str += " dataout"+str(i)+" => "+mem+"_AV_dout_mask("+str(i)+"),\n"
else:
mem_str += " dataout"+str(i)+" => "+mem+"_AV_dout_mask("+str(i)+")\n"
mem_str += " );\n\n"
mem_str += " "+mem+" : entity work.tf_mem_bin\n"
else:
if "MPROJ" in mem or "MPAR" in mem:
mem_str += " "+mem+" : entity work.tf_mem_tproj\n"
else:
mem_str += " "+mem+" : entity work.tf_mem\n"
mem_str += " generic map (\n"+parameterlist.rstrip(",\n")+"\n )\n"
mem_str += " port map (\n"+portlist.rstrip(",\n")+"\n );\n\n"
if delay > 0:
if not memInfo.is_binned and not "in" in mem:
mem_str += " "+mem+"_BX_GEN : entity work.CreateStartSignal\n"
mem_str += " generic map (\n"+delay2_parameterlist.rstrip(",\n")+"\n )\n"
mem_str += " port map (\n"+delay2_portlist.rstrip(",\n")+"\n );\n\n"
mem_str += " "+mem+"_DELAY : entity work.tf_pipe_delay\n"
mem_str += " generic map (\n"+delay_parameterlist.rstrip(",\n")+"\n )\n"
mem_str += " port map (\n"+delay_portlist.rstrip(",\n")+"\n );\n\n"
mem_str += " "+mem+"_DELAY0 : entity work.tf_pipe_delay\n"
mem_str += " generic map (\n"+delay_parameterlist.rstrip(",\n")+"\n )\n"
mem_str += " port map (\n"+delay_portlist_0.rstrip(",\n")+"\n );\n\n"
return wirelist,mem_str
def writeControlSignals_interface(initial_proc, final_procs, notfinal_procs, delay = 0):
"""
# Top-level interface: control signals
"""
final_proc_short = final_procs[0].split("_")[0]
string_ctrl_signals = ""
string_ctrl_signals += " clk : in std_logic;\n"
string_ctrl_signals += " reset : in std_logic;\n"
string_ctrl_signals += " "+initial_proc+"_start : in std_logic;\n"
string_ctrl_signals += " "+initial_proc+"_bx_in : in std_logic_vector(2 downto 0);\n"
string_ctrl_signals += " "+initial_proc+"_bx_out : out std_logic_vector(2 downto 0);\n"
string_ctrl_signals += " "+initial_proc+"_bx_out_vld : out std_logic;\n"
string_ctrl_signals += " "+initial_proc+"_done : out std_logic;\n"
string_ctrl_signals += " "+final_proc_short+"_bx_out : out std_logic_vector(2 downto 0);\n"
string_ctrl_signals += " "+final_proc_short+"_bx_out_vld : out std_logic;\n"
string_ctrl_signals += " "+final_proc_short+"_done : out std_logic;\n"
if final_proc_short == "FT":
for final_proc in final_procs:
string_ctrl_signals += " "+final_proc+"_last_track : out std_logic;\n"
string_ctrl_signals += " "+final_proc+"_last_track_vld : out std_logic;\n"
# Extra output ports if debug info must be sent to test-bench.
for mid_proc in notfinal_procs:
#Hack should probably not need the if statement here...
if mid_proc != "PC" :
string_ctrl_signals += " "+mid_proc+"_bx_out : out std_logic_vector(2 downto 0);\n"
string_ctrl_signals += " "+mid_proc+"_bx_out_vld : out std_logic;\n"
string_ctrl_signals += " "+mid_proc+"_done : out std_logic;\n"
return string_ctrl_signals
def writeMemoryLHSPorts_interface(memList, mtypeB, extraports=False):
"""
# Top-level interface: input memories' ports.
"""
if (extraports):
direction = "out" # carry debug info to test-bench
else:
direction = "in"
string_input_mems = ""
for memMod in memList:
mem = memMod.inst
disk = ""
if memMod.is_binned :
if "VMSME_D" in mem:
disk = "DISK"
#FIXME special cases
if "MPAR" in mem:
if "in" not in mem:
continue
if "AS" in mem:
if "in" not in mem:
continue
string_input_mems += " "+mem+"_wea : "+direction+" t_"+mtypeB+"_1b;\n"
string_input_mems += " "+mem+"_writeaddr : "+direction+" t_"+mtypeB+"_ADDR"+disk+";\n"
string_input_mems += " "+mem+"_din : "+direction+" t_"+mtypeB+"_DATA;\n"
return string_input_mems
def writeDTCLinkLHSPorts_interface(mtypeB, memDict):
"""
# Top-level interface: input DTC link ports.
"""
string_input_mems = ""
memList = memDict[mtypeB]
for memMod in memList :
mem = memMod.inst
string_input_mems += " "+mem+"_link_AV_dout : in t_"+mtypeB+"_DATA;\n"
string_input_mems += " "+mem+"_link_empty_neg : in t_"+mtypeB+"_1b;\n"
string_input_mems += " "+mem+"_link_read : out t_"+mtypeB+"_1b;\n"
return string_input_mems
def writeMemoryRHSPorts_interface(mtypeB, memInfo, memDict):
"""
# Top-level interface: output memories' ports.
# Inputs:
# mTypeB = memory type & its bits width (TPROJ_58 etc.)
# memInfo = Info about each memory type (in MemTypeInfoByKey class)
"""
# Assume all memories of given type have same bxbitwidth.
bxbitwidth = memInfo.bxbitwidth
memList = memDict[mtypeB]
string_output_mems = ""
for memMod in memList:
mem = memMod.inst
disk=""
if "VMSME_D" in mem:
disk="DISK"
if "VMSME" in mtypeB:
string_output_mems += " "+mem+"_A_enb : in t_"+mtypeB+"_A1b;\n"
string_output_mems += " "+mem+"_AV_readaddr : in t_"+mtypeB+"_AADDR"+disk+";\n"
string_output_mems += " "+mem+"_AV_dout : out t_"+mtypeB+"_ADATA;\n"
string_output_mems += " "+mem+"_AV_dout_mask : out t_"+mtypeB+"_MASK"+disk+";\n"
string_output_mems += " "+mem+"_enb_nent : out t_"+mtypeB+"_1b;\n"
string_output_mems += " "+mem+"_V_addr_nent : out t_"+mtypeB+"_NENTADDR"+disk+";\n"
string_output_mems += " "+mem+"_AV_dout_nent : out t_"+mtypeB+"_NENT;\n"
else:
string_output_mems += " "+mem+"_enb : in t_"+mtypeB+"_1b;\n"
string_output_mems += " "+mem+"_V_readaddr : in t_"+mtypeB+"_ADDR;\n"
string_output_mems += " "+mem+"_V_dout : out t_"+mtypeB+"_DATA;\n"
if memInfo.has_numEntries_out:
num_pages = 2**bxbitwidth
if memInfo.is_binned:
string_output_mems += " "+mem+"_AV_dout_nent : "
string_output_mems += "out t_"+mtypeB+"_NENT;\n"
string_output_mems += " "+mem+"_AV_dout_mask : "
string_output_mems += "out t_"+mtypeB+"_MASK;\n"
else:
string_output_mems += " "+mem+"_AV_dout_nent : "
string_output_mems += "out t_"+mtypeB+"_NENT;\n"
return string_output_mems
def writeTrackStreamRHSPorts_interface(mtypeB, memDict):
"""
# Top-level interface: output track stream ports.
# Inputs:
# mTypeB = memory type & its bits width (TPROJ_58 etc.)
"""
string_output_mems = ""
memList = memDict[mtypeB]
for memMod in memList :
mem = memMod.inst
string_output_mems += " "+mem+"_stream_AV_din : out t_"+mtypeB+"_DATA;\n"
string_output_mems += " "+mem+"_stream_A_full_neg : in t_"+mtypeB+"_1b;\n"
string_output_mems += " "+mem+"_stream_A_write : out t_"+mtypeB+"_1b;\n"
return string_output_mems
def writeTBConstants(memDict, memInfoDict, procs, emData_dir, sector, split):
"""
# VHDL test-bench: write the constants used by the test-bench
# Inputs:
# memDict: dictionary of memories organised by type
# & no. of bits (TPROJ_58 etc.)
# memInfoDict: dictionary of info (MemTypeInfoByKey) about each memory type.
# procs: list of processes in the order that they are positioned in the chain
# emData_dir: the directory for the emData/ folder
# sector: the sector/nonant number
"""
str_len = 32 # length of string for formatting purposes
string_constants = ""
string_constants += " -- ########################### Constant Definitions ###########################\n"
string_constants += " -- ############ Please change the constants in this section ###################\n\n"
string_constants += " --=========================================================================\n"
string_constants += " -- Specify version of chain to run from TB:\n"
string_constants += " -- 0 = SectorProcessor.vhd from python script.\n"
string_constants += " -- 1 = SectorProcessorFull.vhd from python script (gives intermediate MemPrints).\n"
string_constants += " -- N.B. Change this also in makeProject.tcl !\n"
string_constants += " constant INST_TOP_TF".ljust(str_len) + ": integer := 1; \n"
string_constants += " --=========================================================================\n\n"
string_constants += " constant CLK_PERIOD".ljust(str_len) + ": time := 4 ns; --! 250 MHz\n"
string_constants += " constant DEBUG".ljust(str_len) + ": boolean := False; --! Debug off/on\n"
# Write delay and input/output file name signals
string_input_tmp = " -- File directories and the start of the file names that memories have in common\n"
string_input_tmp += " -- Input files\n"
string_output_tmp = " -- Output files\n"
string_debug_tmp = " -- Debug output files to check input was correctly read.\n"
for mtypeB in memDict:
memInfo = memInfoDict[mtypeB]
if memInfo.is_initial:
# Avoid duplicate constants, e.g. for VMSTE
if memInfo.mtype_short not in string_input_tmp:
mem_dir = memInfo.mtype_long.replace("AllStubs", "Stubs").replace("Inner", "").replace("Outer", "").replace("DTCLink", "InputStubs").replace("InputLink", "InputStubs").replace("FullMatch", "Matches").replace("AllProj", "TrackletProjections").replace("CandidateMatch", "Matches") # Directory name for the memory testvectors. FIX ME, make this prettier?!
mem_file_start = memInfo.mtype_long.replace("ME", "").replace("TE","").replace("Inner", "").replace("Outer", "").replace("DTC", "").replace("InputLink", "InputStubs").replace("FullMatch", "FullMatches").replace("CandidateMatch", "CandidateMatches") # Testvector file name start. FIX ME, make this prettier?!
mem_delay = procs.index(memInfo.downstream_mtype_short) # The delay in number of bx. The initial process of the chain will have 0 delay, the second have 1 bx delay etc.
#FIXME - hack for fpga2 project
if split:
mem_delay = 0
string_constants += (" constant " + memInfo.mtype_short + "_DELAY").ljust(str_len) + ": integer := " + str(mem_delay) + "; --! Number of BX delays\n"
string_input_tmp += (" constant FILE_IN_" + mtypeB).ljust(str_len) + ": string := memPrintsDir&\"" + mem_dir + "/" + mem_file_start + "_\";\n"
if "VMSME_16" == mtypeB:
string_input_tmp += (" constant FILE_IN_VMSME_17").ljust(str_len) + ": string := memPrintsDir&\"" + mem_dir + "/" + mem_file_start + "_\";\n"
string_debug_tmp += (" constant FILE_OUT_" + memInfo.mtype_short + "_debug").ljust(str_len) + ": string := dataOutDir;\n"
#FIXME hack
string_output_tmp += (" constant FILE_OUT_" + mtypeB).ljust(str_len) + ": string := dataOutDir;\n"
if "VMSME_16" == mtypeB:
string_output_tmp += (" constant FILE_OUT_VMSME_17").ljust(str_len) + ": string := dataOutDir;\n"
else:
string_output_tmp += (" constant FILE_OUT_" + mtypeB).ljust(str_len) + ": string := dataOutDir;\n"
string_constants += "\n -- Paths of data files specified relative to Vivado project's xsim directory.\n"
string_constants += " -- e.g. IntegrationTests/PRMEMC/script/Work/Work.sim/sim_1/behav/xsim/\n"
string_constants += " constant memPrintsDir".ljust(str_len) + ": string := \"" + emData_dir + "\";\n"
string_constants += " constant dataOutDir".ljust(str_len) + ": string := \"../../../../../dataOut/\";\n\n"
string_constants += string_input_tmp
string_constants += string_output_tmp
string_constants += string_debug_tmp
string_constants += "\n -- File name endings\n"
string_constants += " constant inputFileNameEnding".ljust(str_len) + ": string := \"_" + sector + ".dat\"; -- " + sector + " specifies the nonant/sector the testvectors represent\n"
string_constants += " constant outputFileNameEnding".ljust(str_len) + ": string := \".txt\";\n"
string_constants += " constant debugFileNameEnding".ljust(str_len) + ": string := \".debug.txt\";\n\n"
string_constants += " signal dummy : STD_LOGIC := '0';\n\n -- dummy tb signal for inputs into sectorproc\n"
string_constants += " signal dummyaddr : t_as_36_addr := (others => '0');\n\n -- dummy tb signal for inputs into sectorproc"
return string_constants
def writeTBControlSignals(memDict, memInfoDict, initial_proc, final_procs, notfinal_procs, split = False):
"""
# VHDL test bench: write control signals
# Inputs:
# memDict: dictionary of memories organised by type
# & no. of bits (TPROJ_58 etc.)
# memInfoDict: dictionary of info (MemTypeInfoByKey) about each memory type.
# initial_proc: name of the first processing module of the chain
# final_proc: name of the last processing module of the chain
# notfinal_procs: a set of the names of processing modules not at the end of the chain
"""
str_len = 36 # length of string for formatting purposes
str_len2 = 21
string_ctrl_signals = "\n -- ########################### Signals ###########################\n"
string_ctrl_signals += " -- ### UUT signals ###\n"
string_ctrl_signals += " signal clk".ljust(str_len)+": std_logic := '0';\n"
string_ctrl_signals += " signal reset".ljust(str_len)+": std_logic := '1';\n"
string_ctrl_signals += (" signal "+initial_proc+"_start").ljust(str_len)+": std_logic := '0';\n"
string_ctrl_signals += (" signal "+initial_proc+"_idle").ljust(str_len)+": std_logic := '0';\n"
string_ctrl_signals += (" signal "+initial_proc+"_ready").ljust(str_len)+": std_logic := '0';\n"
string_ctrl_signals += (" signal "+initial_proc+"_bx_in").ljust(str_len)+": std_logic_vector(2 downto 0) := (others => '1');\n"
# Extra output ports if debug info must be sent to test-bench.
for mid_proc in notfinal_procs:
string_ctrl_signals += (" signal "+mid_proc+"_bx_out").ljust(str_len)+": std_logic_vector(2 downto 0) := (others => '1');\n"
string_ctrl_signals += (" signal "+mid_proc+"_bx_out_vld").ljust(str_len)+": std_logic := '0';\n"
string_ctrl_signals += (" signal "+mid_proc+"_done").ljust(str_len)+": std_logic := '0';\n"
string_ctrl_signals += (" signal "+final_procs[0].mtype_short()+"_bx_out").ljust(str_len)+": std_logic_vector(2 downto 0) := (others => '1');\n"
string_ctrl_signals += (" signal "+final_procs[0].mtype_short()+"_bx_out_vld").ljust(str_len)+": std_logic := '0';\n"
string_ctrl_signals += (" signal "+final_procs[0].mtype_short()+"_done").ljust(str_len)+": std_logic := '0';\n"
if final_procs[0].mtype_short().startswith("FT"):
for final_proc in final_procs:
string_ctrl_signals += (" signal "+final_proc.inst+"_last_track").ljust(str_len)+": std_logic := '0';\n"
string_ctrl_signals += (" signal "+final_proc.inst+"_last_track_vld").ljust(str_len)+": std_logic := '0';\n"
first_mem = "" # The first memory of the chain
found_first_mem = False
# Loop over all memory types
string_ctrl_signals += "\n -- Signals matching ports of top-level VHDL\n"
for mtypeB in memDict:
if split and ("TPROJ" in mtypeB or "VMSME" in mtypeB):
continue
memInfo = memInfoDict[mtypeB]