Extend verilator main loop to support clock generation in C++ #2108
Labels
category:performance
performance topics
category:simulators:verilator
Verilator
type:feature
new or enhanced functionality
Support a user-defined callback in the Pre-Active region of the time step.
This would allow users to create low-level clocks and avoid the VPI->Python overhead, thus improving simulation speed.
Something like below (this assumes #2105 main_time change):
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