systemVerilog - modelsim Altera starter - uses of interfaces

[FAIG2014]

interface avalon_st_if
  #(
    parameter DATAW        = 64,
    parameter NBYTES_LG2   = 3
    )
   ();
   
    logic                   valid;
    logic                   sop;
    logic                   eop;
    logic                    err;
    logic [NBYTES_LG2-1:0]  empty;   
    logic [DATAW-1:0]       data;
    logic                   ready;
    modport rx
    (
     input  valid,
     input  sop,
     input  eop,
     input  err,
     input  empty,
     input  data,
     output ready
     );
    
    modport tx 
    (
     output valid,
     output sop,
     output eop,
     output err,
     output empty,
     output data,
     input  ready
     );

endinterface // avalon_st_if


module icmp_reply (
    input                                  clk,
    input                                  reset_n,

    avalon_st_if.rx    st_in,
    avalon_st_if.tx    st_out
    
);

I would like to be able to simulate the module icmp_reply as defined previously.
I currently have weird errors:

# ** Fatal: (vsim-3695) /home/fgagnaire/workspace/cocotb/examples/ping_tun_tap/tests/../hdl/icmp_reply.sv(58): The interface port 'st_in' must be passed an actual interface.

[AlexanderSpirin]

I think it's impossible to have interfaces at DUT top level in simulation. As same as you can't use interfaces at top level in your design in synthesis. You have to create wrapper around module. It's certainly inconvenient, but I doubt that another solution exist.