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hns3_rxtx.c
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hns3_rxtx.c
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/* SPDX-License-Identifier: BSD-3-Clause
* Copyright(c) 2018-2019 HiSilicon Limited.
*/
#include <stdarg.h>
#include <stdbool.h>
#include <stdint.h>
#include <stdio.h>
#include <unistd.h>
#include <inttypes.h>
#include <rte_bus_pci.h>
#include <rte_byteorder.h>
#include <rte_common.h>
#include <rte_cycles.h>
#include <rte_dev.h>
#include <rte_eal.h>
#include <rte_ether.h>
#include <rte_vxlan.h>
#include <rte_ethdev_driver.h>
#include <rte_io.h>
#include <rte_ip.h>
#include <rte_gre.h>
#include <rte_net.h>
#include <rte_malloc.h>
#include <rte_pci.h>
#include "hns3_ethdev.h"
#include "hns3_rxtx.h"
#include "hns3_regs.h"
#include "hns3_logs.h"
#define HNS3_CFG_DESC_NUM(num) ((num) / 8 - 1)
#define DEFAULT_RX_FREE_THRESH 32
static void
hns3_rx_queue_release_mbufs(struct hns3_rx_queue *rxq)
{
uint16_t i;
/* Note: Fake rx queue will not enter here */
if (rxq->sw_ring) {
for (i = 0; i < rxq->nb_rx_desc; i++) {
if (rxq->sw_ring[i].mbuf) {
rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
rxq->sw_ring[i].mbuf = NULL;
}
}
}
}
static void
hns3_tx_queue_release_mbufs(struct hns3_tx_queue *txq)
{
uint16_t i;
/* Note: Fake rx queue will not enter here */
if (txq->sw_ring) {
for (i = 0; i < txq->nb_tx_desc; i++) {
if (txq->sw_ring[i].mbuf) {
rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
txq->sw_ring[i].mbuf = NULL;
}
}
}
}
static void
hns3_rx_queue_release(void *queue)
{
struct hns3_rx_queue *rxq = queue;
if (rxq) {
hns3_rx_queue_release_mbufs(rxq);
if (rxq->mz)
rte_memzone_free(rxq->mz);
if (rxq->sw_ring)
rte_free(rxq->sw_ring);
rte_free(rxq);
}
}
static void
hns3_tx_queue_release(void *queue)
{
struct hns3_tx_queue *txq = queue;
if (txq) {
hns3_tx_queue_release_mbufs(txq);
if (txq->mz)
rte_memzone_free(txq->mz);
if (txq->sw_ring)
rte_free(txq->sw_ring);
rte_free(txq);
}
}
void
hns3_dev_rx_queue_release(void *queue)
{
struct hns3_rx_queue *rxq = queue;
struct hns3_adapter *hns;
if (rxq == NULL)
return;
hns = rxq->hns;
rte_spinlock_lock(&hns->hw.lock);
hns3_rx_queue_release(queue);
rte_spinlock_unlock(&hns->hw.lock);
}
void
hns3_dev_tx_queue_release(void *queue)
{
struct hns3_tx_queue *txq = queue;
struct hns3_adapter *hns;
if (txq == NULL)
return;
hns = txq->hns;
rte_spinlock_lock(&hns->hw.lock);
hns3_tx_queue_release(queue);
rte_spinlock_unlock(&hns->hw.lock);
}
static void
hns3_fake_rx_queue_release(struct hns3_rx_queue *queue)
{
struct hns3_rx_queue *rxq = queue;
struct hns3_adapter *hns;
struct hns3_hw *hw;
uint16_t idx;
if (rxq == NULL)
return;
hns = rxq->hns;
hw = &hns->hw;
idx = rxq->queue_id;
if (hw->fkq_data.rx_queues[idx]) {
hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]);
hw->fkq_data.rx_queues[idx] = NULL;
}
/* free fake rx queue arrays */
if (idx == (hw->fkq_data.nb_fake_rx_queues - 1)) {
hw->fkq_data.nb_fake_rx_queues = 0;
rte_free(hw->fkq_data.rx_queues);
hw->fkq_data.rx_queues = NULL;
}
}
static void
hns3_fake_tx_queue_release(struct hns3_tx_queue *queue)
{
struct hns3_tx_queue *txq = queue;
struct hns3_adapter *hns;
struct hns3_hw *hw;
uint16_t idx;
if (txq == NULL)
return;
hns = txq->hns;
hw = &hns->hw;
idx = txq->queue_id;
if (hw->fkq_data.tx_queues[idx]) {
hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]);
hw->fkq_data.tx_queues[idx] = NULL;
}
/* free fake tx queue arrays */
if (idx == (hw->fkq_data.nb_fake_tx_queues - 1)) {
hw->fkq_data.nb_fake_tx_queues = 0;
rte_free(hw->fkq_data.tx_queues);
hw->fkq_data.tx_queues = NULL;
}
}
static void
hns3_free_rx_queues(struct rte_eth_dev *dev)
{
struct hns3_adapter *hns = dev->data->dev_private;
struct hns3_fake_queue_data *fkq_data;
struct hns3_hw *hw = &hns->hw;
uint16_t nb_rx_q;
uint16_t i;
nb_rx_q = hw->data->nb_rx_queues;
for (i = 0; i < nb_rx_q; i++) {
if (dev->data->rx_queues[i]) {
hns3_rx_queue_release(dev->data->rx_queues[i]);
dev->data->rx_queues[i] = NULL;
}
}
/* Free fake Rx queues */
fkq_data = &hw->fkq_data;
for (i = 0; i < fkq_data->nb_fake_rx_queues; i++) {
if (fkq_data->rx_queues[i])
hns3_fake_rx_queue_release(fkq_data->rx_queues[i]);
}
}
static void
hns3_free_tx_queues(struct rte_eth_dev *dev)
{
struct hns3_adapter *hns = dev->data->dev_private;
struct hns3_fake_queue_data *fkq_data;
struct hns3_hw *hw = &hns->hw;
uint16_t nb_tx_q;
uint16_t i;
nb_tx_q = hw->data->nb_tx_queues;
for (i = 0; i < nb_tx_q; i++) {
if (dev->data->tx_queues[i]) {
hns3_tx_queue_release(dev->data->tx_queues[i]);
dev->data->tx_queues[i] = NULL;
}
}
/* Free fake Tx queues */
fkq_data = &hw->fkq_data;
for (i = 0; i < fkq_data->nb_fake_tx_queues; i++) {
if (fkq_data->tx_queues[i])
hns3_fake_tx_queue_release(fkq_data->tx_queues[i]);
}
}
void
hns3_free_all_queues(struct rte_eth_dev *dev)
{
hns3_free_rx_queues(dev);
hns3_free_tx_queues(dev);
}
static int
hns3_alloc_rx_queue_mbufs(struct hns3_hw *hw, struct hns3_rx_queue *rxq)
{
struct rte_mbuf *mbuf;
uint64_t dma_addr;
uint16_t i;
for (i = 0; i < rxq->nb_rx_desc; i++) {
mbuf = rte_mbuf_raw_alloc(rxq->mb_pool);
if (unlikely(mbuf == NULL)) {
hns3_err(hw, "Failed to allocate RXD[%d] for rx queue!",
i);
hns3_rx_queue_release_mbufs(rxq);
return -ENOMEM;
}
rte_mbuf_refcnt_set(mbuf, 1);
mbuf->next = NULL;
mbuf->data_off = RTE_PKTMBUF_HEADROOM;
mbuf->nb_segs = 1;
mbuf->port = rxq->port_id;
rxq->sw_ring[i].mbuf = mbuf;
dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
rxq->rx_ring[i].addr = dma_addr;
rxq->rx_ring[i].rx.bd_base_info = 0;
}
return 0;
}
static int
hns3_buf_size2type(uint32_t buf_size)
{
int bd_size_type;
switch (buf_size) {
case 512:
bd_size_type = HNS3_BD_SIZE_512_TYPE;
break;
case 1024:
bd_size_type = HNS3_BD_SIZE_1024_TYPE;
break;
case 4096:
bd_size_type = HNS3_BD_SIZE_4096_TYPE;
break;
default:
bd_size_type = HNS3_BD_SIZE_2048_TYPE;
}
return bd_size_type;
}
static void
hns3_init_rx_queue_hw(struct hns3_rx_queue *rxq)
{
uint32_t rx_buf_len = rxq->rx_buf_len;
uint64_t dma_addr = rxq->rx_ring_phys_addr;
hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_L_REG, (uint32_t)dma_addr);
hns3_write_dev(rxq, HNS3_RING_RX_BASEADDR_H_REG,
(uint32_t)((dma_addr >> 31) >> 1));
hns3_write_dev(rxq, HNS3_RING_RX_BD_LEN_REG,
hns3_buf_size2type(rx_buf_len));
hns3_write_dev(rxq, HNS3_RING_RX_BD_NUM_REG,
HNS3_CFG_DESC_NUM(rxq->nb_rx_desc));
}
static void
hns3_init_tx_queue_hw(struct hns3_tx_queue *txq)
{
uint64_t dma_addr = txq->tx_ring_phys_addr;
hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_L_REG, (uint32_t)dma_addr);
hns3_write_dev(txq, HNS3_RING_TX_BASEADDR_H_REG,
(uint32_t)((dma_addr >> 31) >> 1));
hns3_write_dev(txq, HNS3_RING_TX_BD_NUM_REG,
HNS3_CFG_DESC_NUM(txq->nb_tx_desc));
}
void
hns3_update_all_queues_pvid_state(struct hns3_hw *hw)
{
uint16_t nb_rx_q = hw->data->nb_rx_queues;
uint16_t nb_tx_q = hw->data->nb_tx_queues;
struct hns3_rx_queue *rxq;
struct hns3_tx_queue *txq;
int pvid_state;
int i;
pvid_state = hw->port_base_vlan_cfg.state;
for (i = 0; i < hw->cfg_max_queues; i++) {
if (i < nb_rx_q) {
rxq = hw->data->rx_queues[i];
if (rxq != NULL)
rxq->pvid_state = pvid_state;
}
if (i < nb_tx_q) {
txq = hw->data->tx_queues[i];
if (txq != NULL)
txq->pvid_state = pvid_state;
}
}
}
void
hns3_enable_all_queues(struct hns3_hw *hw, bool en)
{
uint16_t nb_rx_q = hw->data->nb_rx_queues;
uint16_t nb_tx_q = hw->data->nb_tx_queues;
struct hns3_rx_queue *rxq;
struct hns3_tx_queue *txq;
uint32_t rcb_reg;
int i;
for (i = 0; i < hw->cfg_max_queues; i++) {
if (i < nb_rx_q)
rxq = hw->data->rx_queues[i];
else
rxq = hw->fkq_data.rx_queues[i - nb_rx_q];
if (i < nb_tx_q)
txq = hw->data->tx_queues[i];
else
txq = hw->fkq_data.tx_queues[i - nb_tx_q];
if (rxq == NULL || txq == NULL ||
(en && (rxq->rx_deferred_start || txq->tx_deferred_start)))
continue;
rcb_reg = hns3_read_dev(rxq, HNS3_RING_EN_REG);
if (en)
rcb_reg |= BIT(HNS3_RING_EN_B);
else
rcb_reg &= ~BIT(HNS3_RING_EN_B);
hns3_write_dev(rxq, HNS3_RING_EN_REG, rcb_reg);
}
}
static int
hns3_tqp_enable(struct hns3_hw *hw, uint16_t queue_id, bool enable)
{
struct hns3_cfg_com_tqp_queue_cmd *req;
struct hns3_cmd_desc desc;
int ret;
req = (struct hns3_cfg_com_tqp_queue_cmd *)desc.data;
hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_COM_TQP_QUEUE, false);
req->tqp_id = rte_cpu_to_le_16(queue_id & HNS3_RING_ID_MASK);
req->stream_id = 0;
hns3_set_bit(req->enable, HNS3_TQP_ENABLE_B, enable ? 1 : 0);
ret = hns3_cmd_send(hw, &desc, 1);
if (ret)
hns3_err(hw, "TQP enable fail, ret = %d", ret);
return ret;
}
static int
hns3_send_reset_tqp_cmd(struct hns3_hw *hw, uint16_t queue_id, bool enable)
{
struct hns3_reset_tqp_queue_cmd *req;
struct hns3_cmd_desc desc;
int ret;
hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, false);
req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
req->tqp_id = rte_cpu_to_le_16(queue_id & HNS3_RING_ID_MASK);
hns3_set_bit(req->reset_req, HNS3_TQP_RESET_B, enable ? 1 : 0);
ret = hns3_cmd_send(hw, &desc, 1);
if (ret)
hns3_err(hw, "Send tqp reset cmd error, ret = %d", ret);
return ret;
}
static int
hns3_get_reset_status(struct hns3_hw *hw, uint16_t queue_id)
{
struct hns3_reset_tqp_queue_cmd *req;
struct hns3_cmd_desc desc;
int ret;
hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_RESET_TQP_QUEUE, true);
req = (struct hns3_reset_tqp_queue_cmd *)desc.data;
req->tqp_id = rte_cpu_to_le_16(queue_id & HNS3_RING_ID_MASK);
ret = hns3_cmd_send(hw, &desc, 1);
if (ret) {
hns3_err(hw, "Get reset status error, ret =%d", ret);
return ret;
}
return hns3_get_bit(req->ready_to_reset, HNS3_TQP_RESET_B);
}
static int
hns3_reset_tqp(struct hns3_hw *hw, uint16_t queue_id)
{
#define HNS3_TQP_RESET_TRY_MS 200
uint64_t end;
int reset_status;
int ret;
ret = hns3_tqp_enable(hw, queue_id, false);
if (ret)
return ret;
/*
* In current version VF is not supported when PF is driven by DPDK
* driver, all task queue pairs are mapped to PF function, so PF's queue
* id is equals to the global queue id in PF range.
*/
ret = hns3_send_reset_tqp_cmd(hw, queue_id, true);
if (ret) {
hns3_err(hw, "Send reset tqp cmd fail, ret = %d", ret);
return ret;
}
ret = -ETIMEDOUT;
end = get_timeofday_ms() + HNS3_TQP_RESET_TRY_MS;
do {
/* Wait for tqp hw reset */
rte_delay_ms(HNS3_POLL_RESPONE_MS);
reset_status = hns3_get_reset_status(hw, queue_id);
if (reset_status) {
ret = 0;
break;
}
} while (get_timeofday_ms() < end);
if (ret) {
hns3_err(hw, "Reset TQP fail, ret = %d", ret);
return ret;
}
ret = hns3_send_reset_tqp_cmd(hw, queue_id, false);
if (ret)
hns3_err(hw, "Deassert the soft reset fail, ret = %d", ret);
return ret;
}
static int
hns3vf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id)
{
uint8_t msg_data[2];
int ret;
/* Disable VF's queue before send queue reset msg to PF */
ret = hns3_tqp_enable(hw, queue_id, false);
if (ret)
return ret;
memcpy(msg_data, &queue_id, sizeof(uint16_t));
return hns3_send_mbx_msg(hw, HNS3_MBX_QUEUE_RESET, 0, msg_data,
sizeof(msg_data), true, NULL, 0);
}
static int
hns3_reset_queue(struct hns3_adapter *hns, uint16_t queue_id)
{
struct hns3_hw *hw = &hns->hw;
if (hns->is_vf)
return hns3vf_reset_tqp(hw, queue_id);
else
return hns3_reset_tqp(hw, queue_id);
}
int
hns3_reset_all_queues(struct hns3_adapter *hns)
{
struct hns3_hw *hw = &hns->hw;
int ret, i;
for (i = 0; i < hw->cfg_max_queues; i++) {
ret = hns3_reset_queue(hns, i);
if (ret) {
hns3_err(hw, "Failed to reset No.%d queue: %d", i, ret);
return ret;
}
}
return 0;
}
void
hns3_set_queue_intr_gl(struct hns3_hw *hw, uint16_t queue_id,
uint8_t gl_idx, uint16_t gl_value)
{
uint32_t offset[] = {HNS3_TQP_INTR_GL0_REG,
HNS3_TQP_INTR_GL1_REG,
HNS3_TQP_INTR_GL2_REG};
uint32_t addr, value;
if (gl_idx >= RTE_DIM(offset) || gl_value > HNS3_TQP_INTR_GL_MAX)
return;
addr = offset[gl_idx] + queue_id * HNS3_TQP_INTR_REG_SIZE;
value = HNS3_GL_USEC_TO_REG(gl_value);
hns3_write_dev(hw, addr, value);
}
void
hns3_set_queue_intr_rl(struct hns3_hw *hw, uint16_t queue_id, uint16_t rl_value)
{
uint32_t addr, value;
if (rl_value > HNS3_TQP_INTR_RL_MAX)
return;
addr = HNS3_TQP_INTR_RL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;
value = HNS3_RL_USEC_TO_REG(rl_value);
if (value > 0)
value |= HNS3_TQP_INTR_RL_ENABLE_MASK;
hns3_write_dev(hw, addr, value);
}
static void
hns3_queue_intr_enable(struct hns3_hw *hw, uint16_t queue_id, bool en)
{
uint32_t addr, value;
addr = HNS3_TQP_INTR_CTRL_REG + queue_id * HNS3_TQP_INTR_REG_SIZE;
value = en ? 1 : 0;
hns3_write_dev(hw, addr, value);
}
/*
* Enable all rx queue interrupt when in interrupt rx mode.
* This api was called before enable queue rx&tx (in normal start or reset
* recover scenes), used to fix hardware rx queue interrupt enable was clear
* when FLR.
*/
void
hns3_dev_all_rx_queue_intr_enable(struct hns3_hw *hw, bool en)
{
struct rte_eth_dev *dev = &rte_eth_devices[hw->data->port_id];
uint16_t nb_rx_q = hw->data->nb_rx_queues;
int i;
if (dev->data->dev_conf.intr_conf.rxq == 0)
return;
for (i = 0; i < nb_rx_q; i++)
hns3_queue_intr_enable(hw, i, en);
}
int
hns3_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
if (dev->data->dev_conf.intr_conf.rxq == 0)
return -ENOTSUP;
hns3_queue_intr_enable(hw, queue_id, true);
return rte_intr_ack(intr_handle);
}
int
hns3_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
{
struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
if (dev->data->dev_conf.intr_conf.rxq == 0)
return -ENOTSUP;
hns3_queue_intr_enable(hw, queue_id, false);
return 0;
}
static int
hns3_dev_rx_queue_start(struct hns3_adapter *hns, uint16_t idx)
{
struct hns3_hw *hw = &hns->hw;
struct hns3_rx_queue *rxq;
int ret;
PMD_INIT_FUNC_TRACE();
rxq = (struct hns3_rx_queue *)hw->data->rx_queues[idx];
ret = hns3_alloc_rx_queue_mbufs(hw, rxq);
if (ret) {
hns3_err(hw, "Failed to alloc mbuf for No.%d rx queue: %d",
idx, ret);
return ret;
}
rxq->next_to_use = 0;
rxq->rx_free_hold = 0;
hns3_init_rx_queue_hw(rxq);
return 0;
}
static void
hns3_fake_rx_queue_start(struct hns3_adapter *hns, uint16_t idx)
{
struct hns3_hw *hw = &hns->hw;
struct hns3_rx_queue *rxq;
rxq = (struct hns3_rx_queue *)hw->fkq_data.rx_queues[idx];
rxq->next_to_use = 0;
rxq->rx_free_hold = 0;
hns3_init_rx_queue_hw(rxq);
}
static void
hns3_init_tx_queue(struct hns3_tx_queue *queue)
{
struct hns3_tx_queue *txq = queue;
struct hns3_desc *desc;
int i;
/* Clear tx bd */
desc = txq->tx_ring;
for (i = 0; i < txq->nb_tx_desc; i++) {
desc->tx.tp_fe_sc_vld_ra_ri = 0;
desc++;
}
txq->next_to_use = 0;
txq->next_to_clean = 0;
txq->tx_bd_ready = txq->nb_tx_desc - 1;
hns3_init_tx_queue_hw(txq);
}
static void
hns3_dev_tx_queue_start(struct hns3_adapter *hns, uint16_t idx)
{
struct hns3_hw *hw = &hns->hw;
struct hns3_tx_queue *txq;
txq = (struct hns3_tx_queue *)hw->data->tx_queues[idx];
hns3_init_tx_queue(txq);
}
static void
hns3_fake_tx_queue_start(struct hns3_adapter *hns, uint16_t idx)
{
struct hns3_hw *hw = &hns->hw;
struct hns3_tx_queue *txq;
txq = (struct hns3_tx_queue *)hw->fkq_data.tx_queues[idx];
hns3_init_tx_queue(txq);
}
static void
hns3_init_tx_ring_tc(struct hns3_adapter *hns)
{
struct hns3_hw *hw = &hns->hw;
struct hns3_tx_queue *txq;
int i, num;
for (i = 0; i < HNS3_MAX_TC_NUM; i++) {
struct hns3_tc_queue_info *tc_queue = &hw->tc_queue[i];
int j;
if (!tc_queue->enable)
continue;
for (j = 0; j < tc_queue->tqp_count; j++) {
num = tc_queue->tqp_offset + j;
txq = (struct hns3_tx_queue *)hw->data->tx_queues[num];
if (txq == NULL)
continue;
hns3_write_dev(txq, HNS3_RING_TX_TC_REG, tc_queue->tc);
}
}
}
static int
hns3_start_rx_queues(struct hns3_adapter *hns)
{
struct hns3_hw *hw = &hns->hw;
struct hns3_rx_queue *rxq;
int i, j;
int ret;
/* Initialize RSS for queues */
ret = hns3_config_rss(hns);
if (ret) {
hns3_err(hw, "Failed to configure rss %d", ret);
return ret;
}
for (i = 0; i < hw->data->nb_rx_queues; i++) {
rxq = (struct hns3_rx_queue *)hw->data->rx_queues[i];
if (rxq == NULL || rxq->rx_deferred_start)
continue;
ret = hns3_dev_rx_queue_start(hns, i);
if (ret) {
hns3_err(hw, "Failed to start No.%d rx queue: %d", i,
ret);
goto out;
}
}
for (i = 0; i < hw->fkq_data.nb_fake_rx_queues; i++) {
rxq = (struct hns3_rx_queue *)hw->fkq_data.rx_queues[i];
if (rxq == NULL || rxq->rx_deferred_start)
continue;
hns3_fake_rx_queue_start(hns, i);
}
return 0;
out:
for (j = 0; j < i; j++) {
rxq = (struct hns3_rx_queue *)hw->data->rx_queues[j];
hns3_rx_queue_release_mbufs(rxq);
}
return ret;
}
static void
hns3_start_tx_queues(struct hns3_adapter *hns)
{
struct hns3_hw *hw = &hns->hw;
struct hns3_tx_queue *txq;
int i;
for (i = 0; i < hw->data->nb_tx_queues; i++) {
txq = (struct hns3_tx_queue *)hw->data->tx_queues[i];
if (txq == NULL || txq->tx_deferred_start)
continue;
hns3_dev_tx_queue_start(hns, i);
}
for (i = 0; i < hw->fkq_data.nb_fake_tx_queues; i++) {
txq = (struct hns3_tx_queue *)hw->fkq_data.tx_queues[i];
if (txq == NULL || txq->tx_deferred_start)
continue;
hns3_fake_tx_queue_start(hns, i);
}
hns3_init_tx_ring_tc(hns);
}
/*
* Start all queues.
* Note: just init and setup queues, and don't enable queue rx&tx.
*/
int
hns3_start_queues(struct hns3_adapter *hns, bool reset_queue)
{
struct hns3_hw *hw = &hns->hw;
int ret;
if (reset_queue) {
ret = hns3_reset_all_queues(hns);
if (ret) {
hns3_err(hw, "Failed to reset all queues %d", ret);
return ret;
}
}
ret = hns3_start_rx_queues(hns);
if (ret) {
hns3_err(hw, "Failed to start rx queues: %d", ret);
return ret;
}
hns3_start_tx_queues(hns);
return 0;
}
int
hns3_stop_queues(struct hns3_adapter *hns, bool reset_queue)
{
struct hns3_hw *hw = &hns->hw;
int ret;
hns3_enable_all_queues(hw, false);
if (reset_queue) {
ret = hns3_reset_all_queues(hns);
if (ret) {
hns3_err(hw, "Failed to reset all queues %d", ret);
return ret;
}
}
return 0;
}
static void*
hns3_alloc_rxq_and_dma_zone(struct rte_eth_dev *dev,
struct hns3_queue_info *q_info)
{
struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
const struct rte_memzone *rx_mz;
struct hns3_rx_queue *rxq;
unsigned int rx_desc;
rxq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_rx_queue),
RTE_CACHE_LINE_SIZE, q_info->socket_id);
if (rxq == NULL) {
hns3_err(hw, "Failed to allocate memory for No.%d rx ring!",
q_info->idx);
return NULL;
}
/* Allocate rx ring hardware descriptors. */
rxq->queue_id = q_info->idx;
rxq->nb_rx_desc = q_info->nb_desc;
rx_desc = rxq->nb_rx_desc * sizeof(struct hns3_desc);
rx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx,
rx_desc, HNS3_RING_BASE_ALIGN,
q_info->socket_id);
if (rx_mz == NULL) {
hns3_err(hw, "Failed to reserve DMA memory for No.%d rx ring!",
q_info->idx);
hns3_rx_queue_release(rxq);
return NULL;
}
rxq->mz = rx_mz;
rxq->rx_ring = (struct hns3_desc *)rx_mz->addr;
rxq->rx_ring_phys_addr = rx_mz->iova;
hns3_dbg(hw, "No.%d rx descriptors iova 0x%" PRIx64, q_info->idx,
rxq->rx_ring_phys_addr);
return rxq;
}
static int
hns3_fake_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
uint16_t nb_desc, unsigned int socket_id)
{
struct hns3_adapter *hns = dev->data->dev_private;
struct hns3_hw *hw = &hns->hw;
struct hns3_queue_info q_info;
struct hns3_rx_queue *rxq;
uint16_t nb_rx_q;
if (hw->fkq_data.rx_queues[idx]) {
hns3_rx_queue_release(hw->fkq_data.rx_queues[idx]);
hw->fkq_data.rx_queues[idx] = NULL;
}
q_info.idx = idx;
q_info.socket_id = socket_id;
q_info.nb_desc = nb_desc;
q_info.type = "hns3 fake RX queue";
q_info.ring_name = "rx_fake_ring";
rxq = hns3_alloc_rxq_and_dma_zone(dev, &q_info);
if (rxq == NULL) {
hns3_err(hw, "Failed to setup No.%d fake rx ring.", idx);
return -ENOMEM;
}
/* Don't need alloc sw_ring, because upper applications don't use it */
rxq->sw_ring = NULL;
rxq->hns = hns;
rxq->rx_deferred_start = false;
rxq->port_id = dev->data->port_id;
rxq->configured = true;
nb_rx_q = dev->data->nb_rx_queues;
rxq->io_base = (void *)((char *)hw->io_base + HNS3_TQP_REG_OFFSET +
(nb_rx_q + idx) * HNS3_TQP_REG_SIZE);
rxq->rx_buf_len = HNS3_MIN_BD_BUF_SIZE;
rte_spinlock_lock(&hw->lock);
hw->fkq_data.rx_queues[idx] = rxq;
rte_spinlock_unlock(&hw->lock);
return 0;
}
static void*
hns3_alloc_txq_and_dma_zone(struct rte_eth_dev *dev,
struct hns3_queue_info *q_info)
{
struct hns3_hw *hw = HNS3_DEV_PRIVATE_TO_HW(dev->data->dev_private);
const struct rte_memzone *tx_mz;
struct hns3_tx_queue *txq;
struct hns3_desc *desc;
unsigned int tx_desc;
int i;
txq = rte_zmalloc_socket(q_info->type, sizeof(struct hns3_tx_queue),
RTE_CACHE_LINE_SIZE, q_info->socket_id);
if (txq == NULL) {
hns3_err(hw, "Failed to allocate memory for No.%d tx ring!",
q_info->idx);
return NULL;
}
/* Allocate tx ring hardware descriptors. */
txq->queue_id = q_info->idx;
txq->nb_tx_desc = q_info->nb_desc;
tx_desc = txq->nb_tx_desc * sizeof(struct hns3_desc);
tx_mz = rte_eth_dma_zone_reserve(dev, q_info->ring_name, q_info->idx,
tx_desc, HNS3_RING_BASE_ALIGN,
q_info->socket_id);
if (tx_mz == NULL) {
hns3_err(hw, "Failed to reserve DMA memory for No.%d tx ring!",
q_info->idx);
hns3_tx_queue_release(txq);
return NULL;
}
txq->mz = tx_mz;
txq->tx_ring = (struct hns3_desc *)tx_mz->addr;
txq->tx_ring_phys_addr = tx_mz->iova;
hns3_dbg(hw, "No.%d tx descriptors iova 0x%" PRIx64, q_info->idx,
txq->tx_ring_phys_addr);
/* Clear tx bd */
desc = txq->tx_ring;
for (i = 0; i < txq->nb_tx_desc; i++) {
desc->tx.tp_fe_sc_vld_ra_ri = 0;
desc++;
}
return txq;
}
static int
hns3_fake_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx,
uint16_t nb_desc, unsigned int socket_id)
{
struct hns3_adapter *hns = dev->data->dev_private;
struct hns3_hw *hw = &hns->hw;
struct hns3_queue_info q_info;
struct hns3_tx_queue *txq;
uint16_t nb_tx_q;
if (hw->fkq_data.tx_queues[idx] != NULL) {
hns3_tx_queue_release(hw->fkq_data.tx_queues[idx]);
hw->fkq_data.tx_queues[idx] = NULL;
}
q_info.idx = idx;
q_info.socket_id = socket_id;
q_info.nb_desc = nb_desc;
q_info.type = "hns3 fake TX queue";
q_info.ring_name = "tx_fake_ring";
txq = hns3_alloc_txq_and_dma_zone(dev, &q_info);
if (txq == NULL) {
hns3_err(hw, "Failed to setup No.%d fake tx ring.", idx);
return -ENOMEM;
}
/* Don't need alloc sw_ring, because upper applications don't use it */
txq->sw_ring = NULL;
txq->hns = hns;
txq->tx_deferred_start = false;
txq->port_id = dev->data->port_id;
txq->configured = true;