PCB Placement: Could not insert I/O cell in line zero

[mkexc]

Hi,
I tried to use PCBFlow on a VHDL design of mine. In particular, it is a complex adder(my implementation of the Pentium 4 Adder).
After some trial and error I've successfully completed phases 10 (HDL Analysis) and 20 (Synthesis).
The synthesis has been performed with the standard RT logic.
The problem comes in the placement: when I try to launch the bash script for the placement, the PCBPlace.py script return this error:

Exception during parsing of input file '209_synthesized_output.sp'
Conflicting line: '.SUBCKT carryselectblock_4 op1.0 op1.1 op1.2 op1.3 op2.0 op2.1 op2.2 op2.3 cin o.0 o.1 o.2 o.3'
Exception message: Could not insert I/O cell in line zero! Please increase the X-width of the cell array or correct FixedIO assignment.

I've tried digging a bit around but with my limited SPICE knowledge I couldn't figure out a proper solution.
I'm leaving in the attachment the synthesised SPICE and JSON netlists (I changed the extension from .sp and .json to .txt otherwise GitHub wouldn't let me upload it), resulting from Yosys synthesis as I think can be of help.
Please let me know if I can help in some way debugging the code or figuring out where the issue could be.

209_synthesized_output.json.txt
209_synthesized_output.sp.txt

[cpldcpu]

I/O pins are always inserted in the first line of the cellarray. If the cellarray is not wide enough you will get the exception above.

Right now, the cellarray size is configured in the python program itself:

PCBFlow/30_PLACE/PCBPlace.py

Line 984 in af07c3c

# Configuration area. Will be turned into commandline settings later

Obviously this is supposed to change at some point.

Looking at your design there may be other pitfalls. Right now the placement tool is not set up to deal with multiple subckt. Also, it could simply be that your design is too large in the end. How many cells did the synthesis report?

[mkexc]

Thanks for the quick reply.
I tried to increase the number of ArrayXwidth to a greater value and now it doesn't report anymore that error.
My design is not very big, since I set with the generics before synthesis to a bit parallelism of 8 bit. The synthesis did report 60 cells.

However, right now I'm getting this new error:

Exception during parsing of input file '209_synthesized_output.sp'
Conflicting line: 'X0 B.0 1 NOT'
Exception message: component outside of subckt

I think this one derives from the fact that the placement tool can't deal right now with multiple subckt, as you said before. Is it right? Can I workaround this by flattening the hierarchy of the circuit?

[cpldcpu]

Indeed. You could try to change the synthesis script so it flattens the design first. The netlist should only have a single subckt names "main" after synthesis.

I only tried design with single components/modules so far.

[cpldcpu]

I changed the synthesis scripts so that the design is automatically flattened now.

[mkexc]

Thank you for having modified the synthesis scripts. I was experimenting also a bit with the "flatten" command of Yosys the days before you did it and I did found a problem which happens both with your script and mine.

The problem is that after executing the flattening, the resulting SPICE netlist that is written by Yosys is not enclosed in a SUBCKT statement. This leads the script PCBPlace.py to fail, as it can't find a proper, single, SUBCKT to work with.
I've seen now your last commit which removes the "hierarchy -auto-top" command to address this issue. Unfortunately, if you remove either this or a command like "hierarchy -top top_entity_name", Yosys can't find automatically the top entity, at least in my case, and thus the synthesis script fails.

Then, I've manually added the SUBCKT statement giving it the name "main" and the proper I/Os and it appears to work semi-correctly.

In the sense that I've found another problem, in which in the placed design, every Input pin is connected to a net (to be routed of course) while some output pins are not. In my case, for example, not every bit of the output vector of the sum is connected to a net. On my adder of 8 bit parallelism, only the 2 MSBs of Y(the sum output) get connected, while the remaining 6 LSBs do not. But as you can observe in the synthesised netlist (SPICE and JSON), they actually are connected to outputs. So, I think this is a placement problem.

[cpldcpu]

I found that the design is only truely flattened when I set the "top" flag for one entity before flattening (e.g. hierachy -auto-top). When I do that I run exactly into the issue that you described where there is no subckt anymore. The problem is that the spice file then misses all information about I/O. The only way to recover from that would be to switch to JSON as an intermediate format instead of spice. That may be a wiser choice anyways, but requires quite extensive modifications.

The topic about this missing nets is a bit curious. You design has a lot of nets that are shunted with voltage source. These are eliminitated during placement. Currently the placement tool can only properly eliminate internal nets that are shunted to an I/O.

I tried to trace the Y.5 net in your source file
V149 sum_gen.csb_gen:1.csb_i.mux_21_4.mux_n:1.mux_i.und3.y Y.5 DC 0 V173 sum_gen.csb_gen:1.csb_i.mux_21_4.mux_n:1.mux_i.und3.y sum_gen.csb_gen:1.csb_i.mux_21_4.y.1 DC 0

The thing is, that the last net sum_gen.csb_gen:1.csb_i.mux_21_4.y.1 is not connected to anything? Not sure what is going on. I wonder whether it is possible to instruct yosys to combine all these nets, then the placement tool would not have to do it.

Edit: Can you try to add opt_clean -purge to your synthesis script to see whether it removes more unused nets?

[mkexc]

After having issue the command opt_clean -purge the synthesised netlist(SPICE and JSON) is much less complex and all those nets shunted with voltage sources have been removed.

I then tried to perform the placement and it appears to have been completed correctly!
Here you can find the extracted SPICE netlist.

The only step missing now is dealing with the flattening and the removal of the SUBCKT statement from the SPICE netlist. I think, however, that in the meantime using the workaround to manually adding the SUBCKT statement is enough! 👍

[cpldcpu]

Perfect! Thanks for looking into this. I will change the synthesis scripts. Much easier than to fix the net merging.

[mkexc]

You're welcome! As a last note I want to add that previously neither the SPICE simulation was working, while now with the optimized circuit it is!