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For the following module, the parser is unable to parse this. In your example from the README, it just outputs "Parse failed". I'm running version 0.12.0. It looks like it fails when using assign but is ok with always_comb. This is legal syntax as far as I can tell from IEEE Std 1800-2017. It's discussed in 9.4.5 on Intra-assignment timing controls. I believe it'll have to handle the # (delay) and @ (event) timing controls and even if it's also combined with repeat().
`defineDLY#10psmodulewire_with_delay (
inputlogic clk,
inputlogic a,
outputlogic y
);
assign y =#1 a; // failsassign y =`DLY a; // failsassign y =@(posedge clk) a; // failsassign y =repeat(2) @(posedge clk) a; // failsalways_comb y =`DLY a; // worksendmodule
The text was updated successfully, but these errors were encountered:
For the following module, the parser is unable to parse this. In your example from the README, it just outputs "Parse failed". I'm running version 0.12.0. It looks like it fails when using assign but is ok with always_comb. This is legal syntax as far as I can tell from IEEE Std 1800-2017. It's discussed in 9.4.5 on Intra-assignment timing controls. I believe it'll have to handle the
#
(delay) and@
(event) timing controls and even if it's also combined withrepeat()
.The text was updated successfully, but these errors were encountered: