/
usrp_reset_clocking.grc
714 lines (704 loc) · 14.8 KB
/
usrp_reset_clocking.grc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
options:
parameters:
author: Daniel Estevez
catch_exceptions: 'True'
category: '[GRC Hier Blocks]'
cmake_opt: ''
comment: ''
copyright: ''
description: ''
gen_cmake: 'On'
gen_linking: dynamic
generate_options: no_gui
hier_block_src_path: '.:'
id: usrp_reset_clocking
max_nouts: '0'
output_language: python
placement: (0,0)
qt_qss_theme: ''
realtime_scheduling: '1'
run: 'True'
run_command: '{python} -u {filename}'
run_options: run
sizing_mode: fixed
thread_safe_setters: ''
title: Set the USRP to 250 MHz MCR to reset problems caused by clocking
window_size: ''
states:
bus_sink: false
bus_source: false
bus_structure: null
coordinate: [8, 8]
rotation: 0
state: enabled
blocks:
- name: fc
id: variable
parameters:
comment: ''
value: 512e6
states:
bus_sink: false
bus_source: false
bus_structure: null
coordinate: [936, 12.0]
rotation: 0
state: true
- name: blocks_head_0_0
id: blocks_head
parameters:
affinity: ''
alias: ''
comment: ''
maxoutbuf: '0'
minoutbuf: '0'
num_items: '0'
type: complex
vlen: '1'
states:
bus_sink: false
bus_source: false
bus_structure: null
coordinate: [360, 276.0]
rotation: 0
state: true
- name: blocks_head_0_0_0
id: blocks_head
parameters:
affinity: ''
alias: ''
comment: ''
maxoutbuf: '0'
minoutbuf: '0'
num_items: '0'
type: complex
vlen: '1'
states:
bus_sink: false
bus_source: false
bus_structure: null
coordinate: [360, 332.0]
rotation: 0
state: true
- name: blocks_head_0_0_1
id: blocks_head
parameters:
affinity: ''
alias: ''
comment: ''
maxoutbuf: '0'
minoutbuf: '0'
num_items: '0'
type: complex
vlen: '1'
states:
bus_sink: false
bus_source: false
bus_structure: null
coordinate: [360, 404.0]
rotation: 0
state: true
- name: blocks_head_0_0_2
id: blocks_head
parameters:
affinity: ''
alias: ''
comment: ''
maxoutbuf: '0'
minoutbuf: '0'
num_items: '0'
type: complex
vlen: '1'
states:
bus_sink: false
bus_source: false
bus_structure: null
coordinate: [360, 468.0]
rotation: 0
state: true
- name: blocks_null_sink_0
id: blocks_null_sink
parameters:
affinity: ''
alias: ''
bus_structure_sink: '[[0,],]'
comment: ''
num_inputs: '1'
type: complex
vlen: '1'
states:
bus_sink: false
bus_source: false
bus_structure: null
coordinate: [512, 280.0]
rotation: 0
state: true
- name: blocks_null_sink_0_0
id: blocks_null_sink
parameters:
affinity: ''
alias: ''
bus_structure_sink: '[[0,],]'
comment: ''
num_inputs: '1'
type: complex
vlen: '1'
states:
bus_sink: false
bus_source: false
bus_structure: null
coordinate: [512, 336.0]
rotation: 0
state: true
- name: blocks_null_sink_0_1
id: blocks_null_sink
parameters:
affinity: ''
alias: ''
bus_structure_sink: '[[0,],]'
comment: ''
num_inputs: '1'
type: complex
vlen: '1'
states:
bus_sink: false
bus_source: false
bus_structure: null
coordinate: [512, 408.0]
rotation: 0
state: true
- name: blocks_null_sink_0_2
id: blocks_null_sink
parameters:
affinity: ''
alias: ''
bus_structure_sink: '[[0,],]'
comment: ''
num_inputs: '1'
type: complex
vlen: '1'
states:
bus_sink: false
bus_source: false
bus_structure: null
coordinate: [512, 472.0]
rotation: 0
state: true
- name: gaindB
id: parameter
parameters:
alias: ''
comment: ''
hide: none
label: rx gain in decibels
short_id: g
type: eng_float
value: '0'
states:
bus_sink: false
bus_source: false
bus_structure: null
coordinate: [392, 12.0]
rotation: 0
state: enabled
- name: import_0
id: import
parameters:
alias: ''
comment: ''
imports: import numpy as np
states:
bus_sink: false
bus_source: false
bus_structure: null
coordinate: [480, 160.0]
rotation: 0
state: true
- name: samp_rate
id: parameter
parameters:
alias: ''
comment: ''
hide: none
label: sampling rate [Hz]
short_id: b
type: eng_float
value: 25e6
states:
bus_sink: false
bus_source: false
bus_structure: null
coordinate: [216, 12.0]
rotation: 0
state: enabled
- name: snippet_2
id: snippet
parameters:
alias: ''
code: 'print(''>>> Setting LO sharing'')
self.uhd_usrp_source_0.set_lo_export_enabled(True, "lo1", 0)
self.uhd_usrp_source_0.set_rx_lo_dist(True, "LO_OUT_0")
self.uhd_usrp_source_0.set_rx_lo_dist(True, "LO_OUT_1")
self.uhd_usrp_source_0.set_lo_source("external", "lo1", 0)
self.uhd_usrp_source_0.set_lo_source("external", "lo1", 1)
self.uhd_usrp_source_0.set_lo_source("external", "lo1", 2)
self.uhd_usrp_source_0.set_lo_source("external", "lo1", 3)'
comment: ''
priority: '0'
section: main_after_init
states:
bus_sink: false
bus_source: false
bus_structure: null
coordinate: [664, 36.0]
rotation: 0
state: true
- name: uhd_usrp_source_0
id: uhd_usrp_source
parameters:
affinity: ''
alias: ''
ant0: TX/RX
ant1: TX/RX
ant10: ''
ant11: ''
ant12: ''
ant13: ''
ant14: ''
ant15: ''
ant16: ''
ant17: ''
ant18: ''
ant19: ''
ant2: TX/RX
ant20: ''
ant21: ''
ant22: ''
ant23: ''
ant24: ''
ant25: ''
ant26: ''
ant27: ''
ant28: ''
ant29: ''
ant3: TX/RX
ant30: ''
ant31: ''
ant4: ''
ant5: ''
ant6: ''
ant7: ''
ant8: ''
ant9: ''
bw0: '0'
bw1: '0'
bw10: '0'
bw11: '0'
bw12: '0'
bw13: '0'
bw14: '0'
bw15: '0'
bw16: '0'
bw17: '0'
bw18: '0'
bw19: '0'
bw2: '0'
bw20: '0'
bw21: '0'
bw22: '0'
bw23: '0'
bw24: '0'
bw25: '0'
bw26: '0'
bw27: '0'
bw28: '0'
bw29: '0'
bw3: '0'
bw30: '0'
bw31: '0'
bw4: '0'
bw5: '0'
bw6: '0'
bw7: '0'
bw8: '0'
bw9: '0'
center_freq0: fc
center_freq1: fc
center_freq10: '0'
center_freq11: '0'
center_freq12: '0'
center_freq13: '0'
center_freq14: '0'
center_freq15: '0'
center_freq16: '0'
center_freq17: '0'
center_freq18: '0'
center_freq19: '0'
center_freq2: fc
center_freq20: '0'
center_freq21: '0'
center_freq22: '0'
center_freq23: '0'
center_freq24: '0'
center_freq25: '0'
center_freq26: '0'
center_freq27: '0'
center_freq28: '0'
center_freq29: '0'
center_freq3: fc
center_freq30: '0'
center_freq31: '0'
center_freq4: '0'
center_freq5: '0'
center_freq6: '0'
center_freq7: '0'
center_freq8: '0'
center_freq9: '0'
clock_rate: '0.0'
clock_source0: ''
clock_source1: ''
clock_source2: ''
clock_source3: ''
clock_source4: ''
clock_source5: ''
clock_source6: ''
clock_source7: ''
comment: ''
dc_offs0: 0+0j
dc_offs1: 0+0j
dc_offs10: 0+0j
dc_offs11: 0+0j
dc_offs12: 0+0j
dc_offs13: 0+0j
dc_offs14: 0+0j
dc_offs15: 0+0j
dc_offs16: 0+0j
dc_offs17: 0+0j
dc_offs18: 0+0j
dc_offs19: 0+0j
dc_offs2: 0+0j
dc_offs20: 0+0j
dc_offs21: 0+0j
dc_offs22: 0+0j
dc_offs23: 0+0j
dc_offs24: 0+0j
dc_offs25: 0+0j
dc_offs26: 0+0j
dc_offs27: 0+0j
dc_offs28: 0+0j
dc_offs29: 0+0j
dc_offs3: 0+0j
dc_offs30: 0+0j
dc_offs31: 0+0j
dc_offs4: 0+0j
dc_offs5: 0+0j
dc_offs6: 0+0j
dc_offs7: 0+0j
dc_offs8: 0+0j
dc_offs9: 0+0j
dc_offs_enb0: default
dc_offs_enb1: default
dc_offs_enb10: default
dc_offs_enb11: default
dc_offs_enb12: default
dc_offs_enb13: default
dc_offs_enb14: default
dc_offs_enb15: default
dc_offs_enb16: default
dc_offs_enb17: default
dc_offs_enb18: default
dc_offs_enb19: default
dc_offs_enb2: default
dc_offs_enb20: default
dc_offs_enb21: default
dc_offs_enb22: default
dc_offs_enb23: default
dc_offs_enb24: default
dc_offs_enb25: default
dc_offs_enb26: default
dc_offs_enb27: default
dc_offs_enb28: default
dc_offs_enb29: default
dc_offs_enb3: default
dc_offs_enb30: default
dc_offs_enb31: default
dc_offs_enb4: default
dc_offs_enb5: default
dc_offs_enb6: default
dc_offs_enb7: default
dc_offs_enb8: default
dc_offs_enb9: default
dev_addr: '"addr0=10.11.1.20, addr1=10.11.1.22, clock_source=external, time_source=external,
ref_clk_freq=10e6, master_clock_rate=250e6"'
dev_args: '""'
gain0: gaindB
gain1: gaindB
gain10: '0'
gain11: '0'
gain12: '0'
gain13: '0'
gain14: '0'
gain15: '0'
gain16: '0'
gain17: '0'
gain18: '0'
gain19: '0'
gain2: gaindB
gain20: '0'
gain21: '0'
gain22: '0'
gain23: '0'
gain24: '0'
gain25: '0'
gain26: '0'
gain27: '0'
gain28: '0'
gain29: '0'
gain3: gaindB
gain30: '0'
gain31: '0'
gain4: '0'
gain5: '0'
gain6: '0'
gain7: '0'
gain8: '0'
gain9: '0'
gain_type0: default
gain_type1: default
gain_type10: default
gain_type11: default
gain_type12: default
gain_type13: default
gain_type14: default
gain_type15: default
gain_type16: default
gain_type17: default
gain_type18: default
gain_type19: default
gain_type2: default
gain_type20: default
gain_type21: default
gain_type22: default
gain_type23: default
gain_type24: default
gain_type25: default
gain_type26: default
gain_type27: default
gain_type28: default
gain_type29: default
gain_type3: default
gain_type30: default
gain_type31: default
gain_type4: default
gain_type5: default
gain_type6: default
gain_type7: default
gain_type8: default
gain_type9: default
iq_imbal0: 0+0j
iq_imbal1: 0+0j
iq_imbal10: 0+0j
iq_imbal11: 0+0j
iq_imbal12: 0+0j
iq_imbal13: 0+0j
iq_imbal14: 0+0j
iq_imbal15: 0+0j
iq_imbal16: 0+0j
iq_imbal17: 0+0j
iq_imbal18: 0+0j
iq_imbal19: 0+0j
iq_imbal2: 0+0j
iq_imbal20: 0+0j
iq_imbal21: 0+0j
iq_imbal22: 0+0j
iq_imbal23: 0+0j
iq_imbal24: 0+0j
iq_imbal25: 0+0j
iq_imbal26: 0+0j
iq_imbal27: 0+0j
iq_imbal28: 0+0j
iq_imbal29: 0+0j
iq_imbal3: 0+0j
iq_imbal30: 0+0j
iq_imbal31: 0+0j
iq_imbal4: 0+0j
iq_imbal5: 0+0j
iq_imbal6: 0+0j
iq_imbal7: 0+0j
iq_imbal8: 0+0j
iq_imbal9: 0+0j
iq_imbal_enb0: default
iq_imbal_enb1: default
iq_imbal_enb10: default
iq_imbal_enb11: default
iq_imbal_enb12: default
iq_imbal_enb13: default
iq_imbal_enb14: default
iq_imbal_enb15: default
iq_imbal_enb16: default
iq_imbal_enb17: default
iq_imbal_enb18: default
iq_imbal_enb19: default
iq_imbal_enb2: default
iq_imbal_enb20: default
iq_imbal_enb21: default
iq_imbal_enb22: default
iq_imbal_enb23: default
iq_imbal_enb24: default
iq_imbal_enb25: default
iq_imbal_enb26: default
iq_imbal_enb27: default
iq_imbal_enb28: default
iq_imbal_enb29: default
iq_imbal_enb3: default
iq_imbal_enb30: default
iq_imbal_enb31: default
iq_imbal_enb4: default
iq_imbal_enb5: default
iq_imbal_enb6: default
iq_imbal_enb7: default
iq_imbal_enb8: default
iq_imbal_enb9: default
lo_export0: 'False'
lo_export1: 'False'
lo_export10: 'False'
lo_export11: 'False'
lo_export12: 'False'
lo_export13: 'False'
lo_export14: 'False'
lo_export15: 'False'
lo_export16: 'False'
lo_export17: 'False'
lo_export18: 'False'
lo_export19: 'False'
lo_export2: 'False'
lo_export20: 'False'
lo_export21: 'False'
lo_export22: 'False'
lo_export23: 'False'
lo_export24: 'False'
lo_export25: 'False'
lo_export26: 'False'
lo_export27: 'False'
lo_export28: 'False'
lo_export29: 'False'
lo_export3: 'False'
lo_export30: 'False'
lo_export31: 'False'
lo_export4: 'False'
lo_export5: 'False'
lo_export6: 'False'
lo_export7: 'False'
lo_export8: 'False'
lo_export9: 'False'
lo_source0: internal
lo_source1: internal
lo_source10: internal
lo_source11: internal
lo_source12: internal
lo_source13: internal
lo_source14: internal
lo_source15: internal
lo_source16: internal
lo_source17: internal
lo_source18: internal
lo_source19: internal
lo_source2: internal
lo_source20: internal
lo_source21: internal
lo_source22: internal
lo_source23: internal
lo_source24: internal
lo_source25: internal
lo_source26: internal
lo_source27: internal
lo_source28: internal
lo_source29: internal
lo_source3: internal
lo_source30: internal
lo_source31: internal
lo_source4: internal
lo_source5: internal
lo_source6: internal
lo_source7: internal
lo_source8: internal
lo_source9: internal
maxoutbuf: '0'
minoutbuf: '0'
nchan: '4'
num_mboards: '2'
otw: sc16
rx_agc0: Default
rx_agc1: Default
rx_agc10: Default
rx_agc11: Default
rx_agc12: Default
rx_agc13: Default
rx_agc14: Default
rx_agc15: Default
rx_agc16: Default
rx_agc17: Default
rx_agc18: Default
rx_agc19: Default
rx_agc2: Default
rx_agc20: Default
rx_agc21: Default
rx_agc22: Default
rx_agc23: Default
rx_agc24: Default
rx_agc25: Default
rx_agc26: Default
rx_agc27: Default
rx_agc28: Default
rx_agc29: Default
rx_agc3: Default
rx_agc30: Default
rx_agc31: Default
rx_agc4: Default
rx_agc5: Default
rx_agc6: Default
rx_agc7: Default
rx_agc8: Default
rx_agc9: Default
samp_rate: samp_rate
sd_spec0: ''
sd_spec1: ''
sd_spec2: ''
sd_spec3: ''
sd_spec4: ''
sd_spec5: ''
sd_spec6: ''
sd_spec7: ''
show_lo_controls: 'False'
start_time: '-1.0'
stream_args: ''
stream_chans: '[]'
sync: sync
time_source0: ''
time_source1: ''
time_source2: ''
time_source3: ''
time_source4: ''
time_source5: ''
time_source6: ''
time_source7: ''
type: fc32
states:
bus_sink: false
bus_source: false
bus_structure: null
coordinate: [72, 228.0]
rotation: 0
state: enabled
connections:
- [blocks_head_0_0, '0', blocks_null_sink_0, '0']
- [blocks_head_0_0_0, '0', blocks_null_sink_0_0, '0']
- [blocks_head_0_0_1, '0', blocks_null_sink_0_1, '0']
- [blocks_head_0_0_2, '0', blocks_null_sink_0_2, '0']
- [uhd_usrp_source_0, '0', blocks_head_0_0, '0']
- [uhd_usrp_source_0, '1', blocks_head_0_0_0, '0']
- [uhd_usrp_source_0, '2', blocks_head_0_0_1, '0']
- [uhd_usrp_source_0, '3', blocks_head_0_0_2, '0']
metadata:
file_format: 1
grc_version: 3.10.8.0