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UART.syr
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UART.syr
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Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.20 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.20 secs
--> Reading design: UART.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "UART.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "UART"
Output Format : NGC
Target Device : xc3s400-4-ft256
---- Source Options
Top Module Name : UART
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : Yes
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : Yes
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : Auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 8
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/Users/david/Desktop/88/UART/UART.vhd" in Library work.
Entity <uart> compiled.
Entity <uart> (Architecture <behavioral>) compiled.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <UART> in library <work> (architecture <behavioral>).
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <UART> in library <work> (Architecture <behavioral>).
Entity <UART> analyzed. Unit <UART> generated.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <UART>.
Related source file is "C:/Users/david/Desktop/88/UART/UART.vhd".
Found finite state machine <FSM_0> for signal <estado_actual_1>.
-----------------------------------------------------------------------
| States | 3 |
| Transitions | 6 |
| Inputs | 1 |
| Outputs | 1 |
| Clock | CLK (rising_edge) |
| Reset | RESET (positive) |
| Reset type | asynchronous |
| Reset State | cero |
| Power Up State | cero |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
Found finite state machine <FSM_1> for signal <estado_actual_2>.
-----------------------------------------------------------------------
| States | 3 |
| Transitions | 5 |
| Inputs | 2 |
| Outputs | 4 |
| Clock | CLK (rising_edge) |
| Reset | RESET (positive) |
| Reset type | asynchronous |
| Reset State | idle |
| Power Up State | idle |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
Found finite state machine <FSM_2> for signal <estado_actual_3>.
-----------------------------------------------------------------------
| States | 4 |
| Transitions | 6 |
| Inputs | 2 |
| Outputs | 3 |
| Clock | CLK (rising_edge) |
| Reset | RESET (positive) |
| Reset type | asynchronous |
| Reset State | idle |
| Power Up State | idle |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
Found 1-bit register for signal <TX_READY>.
Found 8-bit register for signal <RX_DATA>.
Found 1-bit register for signal <RX_NEWDATA>.
Found 1-bit register for signal <ACTUALIZACION_RX>.
Found 13-bit comparator less for signal <ACTUALIZACION_RX$cmp_lt0000> created at line 329.
Found 1-bit register for signal <ACTUALIZACION_TX>.
Found 1-bit register for signal <BTN>.
Found 13-bit up counter for signal <cont_5209>.
Found 13-bit comparator less for signal <cont_5209$cmp_lt0000> created at line 100.
Found 13-bit up counter for signal <cont_5209_2>.
Found 4-bit comparator less for signal <estado_actual_2$cmp_lt0000> created at line 252.
Found 4-bit comparator less for signal <estado_actual_3$cmp_lt0000> created at line 314.
Found 8-bit register for signal <RSR>.
Found 4-bit up counter for signal <RX_nbits>.
Found 10-bit register for signal <TSR>.
Found 4-bit up counter for signal <TX_nbit>.
Summary:
inferred 3 Finite State Machine(s).
inferred 4 Counter(s).
inferred 31 D-type flip-flop(s).
inferred 4 Comparator(s).
Unit <UART> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Counters : 4
13-bit up counter : 2
4-bit up counter : 2
# Registers : 8
1-bit register : 5
10-bit register : 1
8-bit register : 2
# Comparators : 4
13-bit comparator less : 2
4-bit comparator less : 2
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Analyzing FSM <FSM_2> for best encoding.
Optimizing FSM <estado_actual_3/FSM> on signal <estado_actual_3[1:2]> with gray encoding.
-----------------------
State | Encoding
-----------------------
idle | 00
rx_inicio | 01
rx_datos | 11
rx_fin | 10
-----------------------
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <estado_actual_2/FSM> on signal <estado_actual_2[1:2]> with user encoding.
-----------------------
State | Encoding
-----------------------
idle | 00
tx_inicio | 01
tx_datos | 10
-----------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <estado_actual_1/FSM> on signal <estado_actual_1[1:3]> with one-hot encoding.
--------------------
State | Encoding
--------------------
cero | 001
flanco | 010
uno | 100
--------------------
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# FSMs : 3
# Counters : 4
13-bit up counter : 2
4-bit up counter : 2
# Registers : 31
Flip-Flops : 31
# Comparators : 4
13-bit comparator less : 2
4-bit comparator less : 2
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <UART> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block UART, actual ratio is 1.
Final Macro Processing ...
=========================================================================
Final Register Report
Macro Statistics
# Registers : 71
Flip-Flops : 71
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : UART.ngr
Top Level Output File Name : UART
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : No
Design Statistics
# IOs : 23
Cell Usage :
# BELS : 148
# GND : 1
# INV : 7
# LUT1 : 8
# LUT2 : 11
# LUT3 : 41
# LUT4 : 10
# MUXCY : 42
# MUXF5 : 1
# VCC : 1
# XORCY : 26
# FlipFlops/Latches : 71
# FDC : 7
# FDCE : 61
# FDE : 1
# FDP : 2
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 22
# IBUF : 11
# OBUF : 11
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s400ft256-4
Number of Slices: 51 out of 3584 1%
Number of Slice Flip Flops: 71 out of 7168 0%
Number of 4 input LUTs: 77 out of 7168 1%
Number of IOs: 23
Number of bonded IOBs: 23 out of 173 13%
Number of GCLKs: 1 out of 8 12%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
CLK | BUFGP | 71 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
RESET | IBUF | 70 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -4
Minimum period: 8.131ns (Maximum Frequency: 122.986MHz)
Minimum input arrival time before clock: 5.191ns
Maximum output required time after clock: 7.165ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'CLK'
Clock period: 8.131ns (frequency: 122.986MHz)
Total number of paths / destination ports: 3110 / 130
-------------------------------------------------------------------------
Delay: 8.131ns (Levels of Logic = 24)
Source: cont_5209_0 (FF)
Destination: cont_5209_12 (FF)
Source Clock: CLK rising
Destination Clock: CLK rising
Data Path: cont_5209_0 to cont_5209_12
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDCE:C->Q 2 0.720 1.216 cont_5209_0 (cont_5209_0)
LUT1:I0->O 1 0.551 0.000 Mcompar_cont_5209_cmp_lt0000_cy<0>_rt (Mcompar_cont_5209_cmp_lt0000_cy<0>_rt)
MUXCY:S->O 1 0.500 0.000 Mcompar_cont_5209_cmp_lt0000_cy<0> (Mcompar_cont_5209_cmp_lt0000_cy<0>)
MUXCY:CI->O 1 0.064 0.000 Mcompar_cont_5209_cmp_lt0000_cy<1> (Mcompar_cont_5209_cmp_lt0000_cy<1>)
MUXCY:CI->O 1 0.064 0.000 Mcompar_cont_5209_cmp_lt0000_cy<2> (Mcompar_cont_5209_cmp_lt0000_cy<2>)
MUXCY:CI->O 1 0.064 0.000 Mcompar_cont_5209_cmp_lt0000_cy<3> (Mcompar_cont_5209_cmp_lt0000_cy<3>)
MUXCY:CI->O 1 0.064 0.000 Mcompar_cont_5209_cmp_lt0000_cy<4> (Mcompar_cont_5209_cmp_lt0000_cy<4>)
MUXCY:CI->O 1 0.064 0.000 Mcompar_cont_5209_cmp_lt0000_cy<5> (Mcompar_cont_5209_cmp_lt0000_cy<5>)
MUXCY:CI->O 1 0.064 0.000 Mcompar_cont_5209_cmp_lt0000_cy<6> (Mcompar_cont_5209_cmp_lt0000_cy<6>)
MUXCY:CI->O 1 0.064 0.000 Mcompar_cont_5209_cmp_lt0000_cy<7> (Mcompar_cont_5209_cmp_lt0000_cy<7>)
MUXCY:CI->O 15 0.281 1.188 Mcompar_cont_5209_cmp_lt0000_cy<8> (Mcompar_cont_5209_cmp_lt0000_cy<8>)
INV:I->O 1 0.551 0.801 Mcompar_cont_5209_cmp_lt0000_cy<8>_inv_INV_0 (ACTUALIZACION_TX_mux0001_inv)
MUXCY:CI->O 1 0.064 0.000 Mcount_cont_5209_cy<0> (Mcount_cont_5209_cy<0>)
MUXCY:CI->O 1 0.064 0.000 Mcount_cont_5209_cy<1> (Mcount_cont_5209_cy<1>)
MUXCY:CI->O 1 0.064 0.000 Mcount_cont_5209_cy<2> (Mcount_cont_5209_cy<2>)
MUXCY:CI->O 1 0.064 0.000 Mcount_cont_5209_cy<3> (Mcount_cont_5209_cy<3>)
MUXCY:CI->O 1 0.064 0.000 Mcount_cont_5209_cy<4> (Mcount_cont_5209_cy<4>)
MUXCY:CI->O 1 0.064 0.000 Mcount_cont_5209_cy<5> (Mcount_cont_5209_cy<5>)
MUXCY:CI->O 1 0.064 0.000 Mcount_cont_5209_cy<6> (Mcount_cont_5209_cy<6>)
MUXCY:CI->O 1 0.064 0.000 Mcount_cont_5209_cy<7> (Mcount_cont_5209_cy<7>)
MUXCY:CI->O 1 0.064 0.000 Mcount_cont_5209_cy<8> (Mcount_cont_5209_cy<8>)
MUXCY:CI->O 1 0.064 0.000 Mcount_cont_5209_cy<9> (Mcount_cont_5209_cy<9>)
MUXCY:CI->O 1 0.064 0.000 Mcount_cont_5209_cy<10> (Mcount_cont_5209_cy<10>)
MUXCY:CI->O 0 0.064 0.000 Mcount_cont_5209_cy<11> (Mcount_cont_5209_cy<11>)
XORCY:CI->O 1 0.904 0.000 Mcount_cont_5209_xor<12> (Mcount_cont_520912)
FDCE:D 0.203 cont_5209_12
----------------------------------------
Total 8.131ns (4.926ns logic, 3.205ns route)
(60.6% logic, 39.4% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'
Total number of paths / destination ports: 12 / 12
-------------------------------------------------------------------------
Offset: 5.191ns (Levels of Logic = 2)
Source: RESET (PAD)
Destination: ACTUALIZACION_RX (FF)
Destination Clock: CLK rising
Data Path: RESET to ACTUALIZACION_RX
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 71 0.821 2.416 RESET_IBUF (RESET_IBUF)
LUT2:I0->O 1 0.551 0.801 ACTUALIZACION_RX_and00001 (ACTUALIZACION_RX_and0000)
FDE:CE 0.602 ACTUALIZACION_RX
----------------------------------------
Total 5.191ns (1.974ns logic, 3.217ns route)
(38.0% logic, 62.0% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
Total number of paths / destination ports: 11 / 11
-------------------------------------------------------------------------
Offset: 7.165ns (Levels of Logic = 1)
Source: TX_READY (FF)
Destination: TX_READY (PAD)
Source Clock: CLK rising
Data Path: TX_READY to TX_READY
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDP:C->Q 1 0.720 0.801 TX_READY (TX_READY_OBUF)
OBUF:I->O 5.644 TX_READY_OBUF (TX_READY)
----------------------------------------
Total 7.165ns (6.364ns logic, 0.801ns route)
(88.8% logic, 11.2% route)
=========================================================================
Total REAL time to Xst completion: 5.00 secs
Total CPU time to Xst completion: 5.69 secs
-->
Total memory usage is 4550156 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)