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UART_map.map
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UART_map.map
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Release 14.7 Map P.20131013 (nt64)
Xilinx Map Application Log File for Design 'UART'
Design Information
------------------
Command Line : map -intstyle ise -p xc3s400-ft256-4 -cm area -ir off -pr off
-c 100 -o UART_map.ncd UART.ngd UART.pcf
Target Device : xc3s400
Target Package : ft256
Target Speed : -4
Mapper Version : spartan3 -- $Revision: 1.55 $
Mapped Date : Tue Jul 09 08:51:13 2019
Mapping design into LUTs...
Running directed packing...
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
slice components. The resulting carry chain will have suboptimal timing.
Mcompar_ACTUALIZACION_RX_cmp_lt0000_cy<8>
Mcount_cont_5209_2_cy<0>
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
slice components. The resulting carry chain will have suboptimal timing.
Mcompar_cont_5209_cmp_lt0000_cy<8>
Mcount_cont_5209_cy<0>
Running delay-based LUT packing...
Running related packing...
Updating timing models...
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 2
Logic Utilization:
Number of Slice Flip Flops: 71 out of 7,168 1%
Number of 4 input LUTs: 66 out of 7,168 1%
Logic Distribution:
Number of occupied Slices: 51 out of 3,584 1%
Number of Slices containing only related logic: 51 out of 51 100%
Number of Slices containing unrelated logic: 0 out of 51 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 74 out of 7,168 1%
Number used as logic: 66
Number used as a route-thru: 8
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
Number of bonded IOBs: 23 out of 173 13%
Number of BUFGMUXs: 1 out of 8 12%
Average Fanout of Non-Clock Nets: 3.25
Peak Memory Usage: 4417 MB
Total REAL time to MAP completion: 1 secs
Total CPU time to MAP completion: 1 secs
NOTES:
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
Mapping completed.
See MAP report file "UART_map.mrp" for details.